E0852E20 (Elpida) - • Double-data-rate architecture; two data transfers perclock cycle• The high-speed data transfer is realized by the 4 bitsprefetch pipelined architecture• Bi-directional differential data strobe (DQS and /DQS)is transmitted/received with data for capturing data atthe receiver• DQS is edge-aligned with data for READs; centeralignedwith data for WRITEs• Differential clock inputs (CK and /CK)• DLL aligns DQ and DQS transitions with CKtransitions, DDR2 SDRAM

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E0852E20 (Elpida)

Electronic component documentation (datasheet) «E0852E20» (DDR2 SDRAM), manufacturer Elpida. Download datasheet file:

Datasheet E0852E20 manufacturer Elpida

Partname	E0852E20
Description	• Double-data-rate architecture; two data transfers perclock cycle• The high-speed data transfer is realized by the 4 bitsprefetch pipelined architecture• Bi-directional differential data strobe (DQS and /DQS)is transmitted/received with data for capturing data atthe receiver• DQS is edge-aligned with data for READs; centeralignedwith data for WRITEs• Differential clock inputs (CK and /CK)• DLL aligns DQ and DQS transitions with CKtransitions
Functional	DDR2 SDRAM
Manufacturer	Elpida Memory
Site	www.elpida.com

Size	Pages: 68, 722.21Kb
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