A-Data

ADABC1608

PC-133 SDRAM Unbuffered DIMM

16Mx64bits SDRAM DIMM based on 16Mx8, 4Bank, 4K Refresh, 3.3V SDRAM

General Description

The ADABC1608 is 16Mx64 bits Synchronous DRAM
Modules, The modules are composed of eight 16Mx8
bits CMOS Synchronous DRAMs in TSOP-II 400mil
54pin package and one 2Kbit EEPROM in 8pin
TSSOP(TSOP) package on a 168pin glassepoxy
printed circuit board.
The A-Data is a Dual In-line Memory Module and is
intended for mounting onto 168-pins edge connector
sockets. Fully synchronous operation referenced to
the positive edge of the clock. All inputs and outputs
are synchronized with the rising edge of the clock.
The data paths are internally pipelined to achieve very
high bandwidth.

Features

PC-133 support

Auto refresh and self refresh

4096 refresh cycles / 64ms

Single 3.3±0.3V power supply

All device pins are compatible with LVTTL
interface

Data mask function by DQM

Serial Presence Detect with EEPROM

Module bank :one physical bank

PCB : B6986RAB,Height (28.00mm),single
sided component, Four layers

Ordering Information.

Part No.

Frequency

Bank

Ref.

Package

ADABC1608

133Mhz

4 Banks

TSOP II

Pin Assignment

FRONT SIDE

BACK SIDE

PIN NAME PIN

NAME

PIN NAME PIN NAME PIN NAME PIN NAME

NAME

1 VSS 22 *CB1 43 VSS 64

VSS

VSS 106 *CB5 127 VSS 148 VSS

2 DQ0 23 VSS 44 DU 65 DQ21 86 DQ32 107 VSS 128 CKE0

149

DQ53

3 DQ1 24 NC 45 /CS2 66 DQ22 87 DQ33 108

NC 129 */CS3 150 DQ54

4 DQ2 25 NC 46

DQM2

67 DQ23 88 DQ34 109

NC 130 DQM6

151

DQ55

5 DQ3 26 VDD 47 DQM3 68

VSS

89 DQ35 110 VDD 131 DQM7

152 VSS

6 VDD 27 /WE 48 DU 69 DQ24 90

VDD 111 /CAS 132 *A13

153

DQ56

7 DQ4 28 DQM0 49 VDD 70 DQ25 91 DQ36 112 DQM4 133 VDD 154 DQ57
8 DQ5 29 DQM1 50 NC 71 DQ26 92 DQ37 113 DQM5 134

NC 155 DQ58

9 DQ6 30 /CS0 51 NC 72 DQ27 93 DQ38 114 */CS1 135

NC 156 DQ59

10 DQ7 31 DU 52 *CB2 73

VDD

94 DQ39 115 /RAS 136 *CB6 157 VDD

11 DQ8 32 VSS 53 *CB3 74 DQ28 95 DQ40 116 VSS 137 *CB7 158

DQ60

12 VSS 33 A0 54 VSS 75 DQ29 96

VSS 117

A1 138 VSS 159

DQ61

13 DQ9 34 A2 55 DQ16 76 DQ30 97 DQ41 118

A3 139 DQ48

160

DQ62

14 DQ10 35 A4 56 DQ17 77 DQ31 98 DQ42 119

A5 140 DQ49 161 DQ63

15 DQ11 36 A6 57 DQ18 78

VSS

99 DQ43 120

A7 141 DQ50 162 VSS

16 DQ12 37 A8 58 DQ19 79

CK2 100 DQ44 121

A9 142 DQ51 163 *CK3

17 DQ13 38 A10/AP 59 VDD 80

NC 101 DQ45 122 BA0 143 VDD 164 NC

18 VDD 39 BA1 60 DQ20 81

102 VDD 123

A11

144 DQ52 165

**SA0

19 DQ14 40 VDD 61 NC 82 *SDA 103 DQ46 124 VCC 145

NC 166 **SA1

20 DQ15 41 VDD 62 *VREF 83

*SCL 104 DQ47 125 *CK1 146 *VREF 167 **SA2

21 *CB0 42 CK0 63 *CKE1 84

VDD 105 *CB4 126 *A12 147

NC 168 VDD

* These pins are not used in this module.

** These pins should be NC in the system which does not support SPD.

Rev 2 April, 2002

A-Data

ADABC1608

Pin Description

PIN NAME

FUNCTION

CK0,CK2 System Clock

Active on the positive edge to sample all inputs.

CKE0 Clock

Enable

Masks system clock to freeze operation from the next clock cycle. CKE

should be enabled at least on cycle prior new command. Disable input

buffers for power down in standby

/CS0,/CS2 Chip Select

Disables or Enables device operation by masking or enabling all input

except CK, CKE and L(U)DQM

A0~A11 Address

Row / Column address are multiplexed on the same pins.

BA0~BA1 Banks Select

Selects bank to be activated during row address latch time.

Selects bank for read / write during column address latch time.

DQ0~DQ63 Data

Data inputs / outputs are multiplexed on the same pins.

DQM0~7 Data Mask

Makes data output Hi-Z,

/RAS

Row Address Strobe

Latches row addresses on the positive edge of the CLK with /RAS low

/CAS

Column Address Strobe

Latches Column addresses on the positive edge of the CLK with /CAS low

/WE

Write Enable

Enables write operation and row recharge.

VDD/VSS Power Supply/Ground

Power and Ground for the input buffers and the core logic.

SDA

Serial data I/O

EEPROM serial data I/O

SCL

Serial clock

EEPROM clock input

SA0~2

Address in EEPROM

EEPROM address input

Write Protect for EEPROM

Write Protect for Serial Presence Detect on DIMM

No Connection

This pin is recommended to be left No Connection on the device.

Rev 2 April, 2002

A-Data

ADABC1608

Block Diagram

DQ40

DQ41

DQ42

DQ43

DQ44

DQ45

DQ46

DQ47

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ48

DQ49

DQ50

DQ51

DQ52

DQ53

DQ54

DQ55

DQ56

DQ57

DQ58

DQ59

DQ60

DQ61

DQ62

DQ63

DQ32

DQ33

DQ34

DQ35

DQ36

DQ37

DQ38

DQ39

DQM

/CS

/CS2

/CS0

/CS

DQM

DQM0

DQM1

DQM7

DQM6

DQM5

DQM4

/RAS

VSS

SCL

SPD

47K Ohms

SA0 SA1 SA2

A0 A1 A2

SDA

VCC

/WE

/CAS

/RAS : D0 ~D7

/WE : D0 ~D7

/CAS : D0 ~D7

A0~A11

BA0/BA1:D0~D7

BA0/BA1

A0~A11:D0~D7

D0~D7

CK : 2 SDRAMs

CKE : D0~D7

CKE0

CK2

CK1

CK3

CK0

3.3 pF

10 Ohm

Rev 2 April, 2002

A-Data

ADABC1608

Absolute Maximum Ratings

Parameter Symbol

Value

Unit

Voltage on any pin relative to Vss

, V

out

-1.0

4.6

Voltage on VDD supply relative to Vss

, V

DDQ

-1.0

4.6

Storage temperature

STG

-55 ~ +150

Power dissipation

Short circuit current

Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATING are exceeded.

Functional operation should be restricted to recommended operating condition.

Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

DC Operating Condition

Voltage referenced to Vss = 0V, T

= 0 to 70

Parameter Symbol

Min

Typ

Max

Unit

Note

Supply voltage

, V

DDQ

3.0 3.3 3.6

Input logic high voltage

2.0 3.0

+0.3 V

Input logic low voltage

-0.3 0 0.8

V 2

Output logic high voltage

2.4 -

- V

=-2mA

Output logic low voltage

- - 0.4

=2mA

Input leakage current

-5 - 5

Output leakage current

-5 - 5

Note : 1. V

(max)=4.6V AC for pulse width 10ns acceptable.

2.V

(min)=-1.5V AC for pulse width 10ns acceptable.

3.Any

input

+ 0.3V, all other pins are not under test = 0V.

4.Dout is disabled, 0V V

OUT

AC Operating Condition

Voltage referenced to Vss = 0V, T

= 0 to 70

Parameter Symbol

Value

Unit

Note

AC input high / low level voltage

/ V

2.4 / 0.4

Input timing measurement reference level voltage

Vtrip

1.4

Input rise / fall time

TR / tF

Output timing measurement reference level

Voutfef

1.4

Output load capacitance for access time measurement

Note: 1. 3.15V V

3.6V

2. Output load to measure access times is equivalent to two TTL gates and one capacitor (30pF). For details,

refer to AC/DC output load circuit.

Rev 2 April, 2002

A-Data

ADABC1608

Capacitance

TA=25, f-=1Mhz, VDD=3.3V

Parameter Pin

Symbol

Min

Max

Unit

CLK Cl1

Input capacitance

A0~A11,BA0,BA1,CKE,/CS,/RAS,

/CAS,/WE,DQM

Cl2 40

Data input / output capacitance DQM

CI/O

Output load circuit

(DC) = 2.4V,I

= -2mA

(DC) = 0.4V,I

= 2mA

3.3 V

1200 ohms

870 ohms

50 pF

Output

DC Characteristics I

Parameter Symbol

Min

Max

Unit

Note

Input leakage current

-1

Output leakage current

-1

Output high voltage

2.4

= -4mA

Output low voltage

0.4

= 4mA

Note : 1.V

= 0 TO 3.6V, All other pins are not tested under V

= 0V.

2.D

OUT

is disabled, V

OUT

= 0 to 3.6.

Rev 2 April, 2002

A-Data

ADABC1608

DC Characteristics II

Parameter Symbol

Test

condition

Speed

Unit

Note

Operating Current

IDD1

Burst length=1, One bank active

tRCtRC(min),I

=0mA

700 mA

IDD2P

CKEV

(max), tCK=min

Precharge standby

current in power

down mode

IDD2PS CKEV

(max), tCK=

IDD2N

CKEV

(min), /CSV

(min),

tCK=min input signals are

changed one time during 2clks.

All other pins VDD-0.2V or

0.2V

160

Precharge standby

current in Non power

down mode

IDD2NS

CKEV

(min), tCK=

Input signals are stable.

IDD3P

CKEV

(max), tCK=min

Active standby

current in power

down mode

IDD3PS CKEV

(max), tCK=

IDD3N

CKEV

(min), /CSV

(min),

tCK=min input signals are

changed one time during 2clks.

All other pins VDD-0.2V or

0.2V

320

Active standby

current in Non power

down mode

IDD3NS

CKEV

(min), tCK=

Input signals are stable.

320

Burst mode operating

current

IDD4

(min),I

=0 mA

All banks active

800 mA

Auto refresh current IDD5

tRRCtRRC(min), All banks

active

1,920 mA

Self refresh current

IDD6

CKE0.2V

16 mA

Note: 1. IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output

open.

2. Min. of tRRC is shown at AC characteristics.

Rev 2 April, 2002

A-Data

ADABC1608

AC Characteristics

ADABC1608

Parameter Symbol

Min Max

Unit Note

/CAS Latency = 3

tCK3

7.5

System clock

Cycle time

/CAS Latency = 2

tCK2

1000 ns

Clock high pulse width

tCHW

2.5

Clock low pulse width

tCLW

2.5

/CAS Latency = 3

tAC3

5.4

Access time form

clock

/CAS Latency = 2

tAC2

ns 2

Operation tRC

/RAS cycle time

Auto Refresh

tRRC

/RAS to /CAS delay

tRCD

/RAS active time

tRAS

100K

/RAS precharge time

tRP

/RAS to /RAS bank active delay

tRRD

/CAS to /CAS delay

tCCD

CLK

Write command to data in delay

tWTL

CLK

Data in to precharge command

tDPL

CLK

Data in active command

tDAL

CLK

DQM to data out Hi-Z

tDQZ

CLK

DQM to data in mask

tDQM

CLK

Data out hold time

tOH

2.7

Data input setup time

tDS

1.5

Data input hold time

tDH

0.8

Address setup time

tAS

1.5

Address hold time

tAH

0.8

CKE setup time

tCKS

1.5

CKE hold time

tCKH

0.8

Command setup time

tCS

1.5

Command hold time

tCH

0.8

CLK to data output in low Z-time

tOLZ

MRS to new command

tMRD

CLK

Power down exit time

tPDE

CLK

Self refresh exit time

tSRE

CLK

Refresh time

tREF

Note : 1. Assume tR / tF (input rise and fall time) is 1 ns.

2. Access times to be measured with input signals of 1v / ns edge rate.

3.A new command can be given tRRC after self refresh exit.

Rev 2 April, 2002

A-Data

ADABC1608

Command Truth-Table

Command CKEn-1

CKEn

/CS

/RAS

/CAS

/WE

DQM

ADDR

A10/AP

Mode

Set

H X L L L L X

code

H X X X

No Operation

L H H H

X X

Bank Active

Read

Read with Auto Precharge

H X L H L H X CA

Write

Write with Auto Precharge

H X L H L L X CA

Precharge All Bank

H X

Precharge select Bank

H X L L H L X X

L V

Burst

Stop

H X L H H L X

DQM H

Auto

Refresh

H H L L L H X

Entry

H L L L L H X

H X X X

Self Refresh

Exit L H

L H H H

H X X X

Entry

H L

L H H H

H X X X

Precharge

Power down

Exit L H

L H H H

H X X X

Entry

H L

L V V V

Clock Suspend

Exit L H

Rev 2 April, 2002

A-Data

ADABC1608

Package Information

0.100 Max

0.050 ± 0.0039

(1.270 ± 0.10)

0.250

(6.350)

Detail A

0.123 ± 0.005

(3.125 ± 0.125)

0.250

(6.350)

Detail B

0.123 ± 0.005

(3.125 ± 0.125)

0.079 ± 0.004

(2.000 ± 0.100)

0.079 ± 0.004

(2.000 ± 0.100)

0 M

i
n

8
Mi

n
)

(2.54 Max)

5.250

5.014

Units : Inches (Millimeters)

R 0.079

(R 2.000)

0.250

(6.350)

1.450

(36.830)

2.150

(54.61)

118

0
0
)

0.350

0 M

i
n

4
0
Mi

n
)

700

(
1
7.

0
)

.118DIA ± 0.004

(3.000DIA ± 0.100)

(8.890)

0.250

(6.350)

.450

(11.430)

4.550

(115.57)

0.157 ± 0.004

(4.000 ± 0.100)

0.089

(2.26)

(127.350)

(133.350)

(
2
8.

000

)

0.118

(3.000)

0.050

0.008 ± 0.006

(0.200 ± 0.150)

(1.270)

0
M

i
n

.
5
4
0
Mi

n
)

Detail C

0.039 ± 0.002

(1.000 ± 0.050)

Rev 2 April, 2002

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: ADABC1616

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: ADABC1616