A-Data
ADD6616A4A
Revision History
Revision 1 ( Dec. 2001 )
1.Fister release.
Revision 2 ( Apr. 2002 )
1. Changed module current specification.
2. Add Performance range.
3.
Changed AC Characteristics.
4.
Changed typo size on module PCB in package dimensions.
Rev 2 April, 2002
1
A-Data
ADD6616A4A
Double Data Rate SDRAM
1M x 16 Bit x 4 Banks
General Description
The ADD6616A4A are four-bank Double Data
Rate(DDR) Synchronous DRAMs organized as
1,048,576 words x 16 bits x 4 banks.
Synchronous design allows precise cycle control
with the use of system clock I/O transactions are
possible on every clock cycle.
Data outputs occur at both rising edges of CK and
/CK.
Range of operating frequencies, programmable
burst length and programmable latencies allow the
same device to be useful for a variety of high
bandwidth high performance memory system
applications
Features
2.5V for VDD power supply
SSTL_2 interface
MRS Cycle with address key programs
-CAS Latency (2, 2.5 )
-Burst Length (2,4 &8)
-Burst Type (sequential & Interleave)
4 banks operation
Differential clock input (CK, /CK) operation
Double data rate interface
Auto & Self refresh
4096 refresh cycle
DQM for masking
Package:66-pins 400 mil TSOP-Type II
Ordering Information.
Part No.
Frequency
Interface
Package
ADD6616A4A-4B 250Mhz
ADD6616A4A-5B 200Mhz
SSTL_2 400mil
66pin
TSOPII
Pin Assignment
1
2
3
4
5
6
7
8
9
V
D D
D Q0
V
D D Q
N C
D Q 1
V
S S Q
N C
D Q 2
V
D D Q
6
4
3
62
61
60
5 9
5 8
V
S S
DQ7
V
S SQ
NC
DQ6
V
D D Q
NC
DQ5
V
S SQ
10
11
12
13
14
15
16
17
18
19
20
N C
D Q 3
V
S S Q
N C
NC
V
D D Q
N C
W E
C A S
R A S
C S
NC
D Q 4
V
D D Q
N C
N C
V
S S Q
D Q S
N C
V
D M
A 6
A5
A4
V
S S
R E F
V
S S
21
22
23
24
25
26
27
28
29
NC
B S 0
B S 1
A10/AP
A 0
A 1
A 2
V
D D
30
31
32
33
34
35
3 6
37
3 8
39
NC 1
A 3
N C
40
41
42
43
CK
CK
CKE
NC
NC
A11
A9
A 8
A7
5 7
56
55
54
5 3
52
5 1
5 0
4 9
4 8
47
46
4 5
44
6
65
6
6
7
N C
D D
V
66-pin plastic TSOP II 400 mil
Rev 2 April, 2002
2
A-Data
ADD6616A4A
Pin Description
PIN NAME
FUNCTION
CK, /CK
System Clock
Differential clock input.
CKE Clock
Enable
Masks system clock to freeze operation from the next clock cycle. CKE
should be enabled at least on cycle prior new command. Disable input
buffers for power down in standby
/CS
Chip Select
Disables or Enables device operation by masking or enabling all input
except CK, CKE and L(U)DQM
A0~A11
Address
Row / Column address are multiplexed on the same pins.
Row address : A0~A11
Column address : A0~A7
BA0~BA1 Banks Select
Selects bank to be activated during row address latch time.
Selects bank for read / write during column address latch time.
DQ0~DQ15 Data
Data inputs / outputs are multiplexed on the same pins.
L(U)DQM Data Mask
Makes data output Hi-Z,
LDQS,UDQS Data Strobe
Bi-directional Data Strobe.
/RAS
Row Address Strobe
Latches row addresses on the positive edge of the CLK with /RAS low
/CAS
Column Address Strobe
Latches Column addresses on the positive edge of the CLK with /CAS
low
/WE
Write Enable
Enables write operation and row recharge.
VDD/VSS Power Supply/Ground
Power and Ground for the input buffers and the core logic.
V
DDQ
/V
SSQ
Data Output Power/Ground Power supply for output buffers.
VREF
Reference Voltage
Reference voltage for inputs for SSTL interface.
NC
No Connection
This pin is recommended to be left No Connection on the device.
Block Diagram
Command
Decoder
CK
/CK
CKE
/CS
/RAS
/CAS
/WE
LDM
Address
Buffer
A0 ~ A11
Bank
Control
1Mx16/Bank0
Column Decoder
Column Address
Counter
Sense AMP
2-b
i
t
Prefetch
Unit
1Mx16/Bank1
1Mx16/Bank2
1Mx16/Bank3
Mode
Register
Row
Decoder
Inp
ut Buff
er
O
utpu
t Buff
er
DLL
Block
Mode
Register
Data Strobe
Transmitter
Data Strobe
Receiver
LDQS, UDQS
CLK
DS
Write Data Register
2-bit Prefetch Unit
DS
DQ[0:15]
32
16
16
32
CLK_DLL
UDM
BA0, BA1
Rev 2 April, 2002
3
A-Data
ADD6616A4A
Absolute Maximum Ratings
Parameter Symbol
Value
Unit
Voltage on any pin relative to Vss
V
IN
, V
out
-0.5
~
3.6
V
Voltage on VDD supply relative to Vss
V
DD
, V
DDQ
-0.5
~
3.6
V
Storage temperature
T
STG
-55 ~ +125
Power dissipation
P
D
1
W
Short circuit current
I
OS
50
mA
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATING are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC Operating Condition
Voltage referenced to Vss = 0V, T
A
= 0 to 70
Parameter Symbol
Min
Typ
Max
Unit
Note
Supply voltage
V
DD
3.15 3.3 3.45
V
Supply voltage
V
DDQ
2.3 2.5 2.7
1
Input logic high voltage
V
IH
V
REF
+0.15
- V
DDQ
+0.3 V
Input logic low voltage
V
IL
-0.3 -
V
REF
-0.15
V 2
Output logic high voltage
V
OH
V
TT
+0.75 -
- V
I
OH
=-15.2mA
Output logic low voltage
V
OL
- -
V
TT
-0.75- V I
OL
=15.2mA
Input leakage current
I
IL
-5 - 5
uA
3
Output leakage current
I
OL
-5 - 5
uA
4
Reference Voltage
V
REF
0.49*
V
DDQ
0.5* V
DDQ
0.51*
V
DDQ
V
Termination Voltage
V
TT
V
REF
-0.04
V
RE
V
REF
+0.04
5
Note : 1. V
DDQ
must not exceed the level of V
DDQ
.
2.V
IL
(min)=-1.5V AC for pulse width 5ns acceptable.
3.Any
input
0V
V
IN
3.6V, all other pins are not under test = 0V.
4.Dout is disabled, 0V V
OUT
2.7V.
5.
V
REF
is expected to be equal to 0.5* V
DDQ
of the transmitting device, and to track variations in the DC level of
the same. Peak to peak noise on V
REF
may not exceed 2% of the DC value.
Rev 2 April, 2002
4
A-Data
ADD6616A4A
AC Operating Condition
Voltage referenced to Vss = 0V, T
A
= 0 to 70
Parameter Symbol
Value
Unit
Note
AC input high / low level voltage
V
IH
/ V
IL
2.4 / 0.4
V
Input timing measurement reference level voltage
Vtrip
1.4
V
Input rise / fall time
TR / tF
1
Ns
Output timing measurement reference level
Voutfef
1.4
V
Output load capacitance for access time measurement
CL
50
pF
2
Note: 1. 3.15V V
DD
3.6V is applied for ADD6616A4A5.
2. Output load to measure access times is equivalent to two TTL gates and one capacitor (30pF). For details,
refer to AC/DC output load circuit.
Capacitance
TA=25, f-=1Mhz
Parameter Pin
Symbol
Min
Max
Unit
CK, /CK
Cl1
2
3
pF
Input capacitance
A0~A11,BA0,BA1,CKE,/CS,/RAS,
/CAS,/WE,DQM
Cl2 2
3
pF
Data input / output capacitance DQM
CI/O
4
5
pF
Output load circuit
Output Load Circuit (SSTL_2)
Output
Z0=50
C
LOAD
=30pF
V
REF
=0.5*V
DDQ
R
T
=50
V
tt
=0.5*V
DDQ
Rev 2 April, 2002
5
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