V-Data
VDS6632A4A
Synchronous DRAM
512K x 32 Bit x 4 Banks
General Description
The VDS6632A4A are four-bank Synchronous
DRAMs organized as 524,288 words x 32 bits x 4
banks,
Synchronous design allows precise cycle control
with the use of system clock I/O transactions are
possible on every clock cycle.
Range of operating frequencies, programmable
burst length and programmable latencies allow the
same device to be useful for a variety of high
bandwidth high performance memory system
applications
Features
JEDEC standard LVTTL 3.3V power supply
MRS Cycle with address key programs
-CAS Latency (2 & 3)
-Burst Length (1,2,3,8,& full page)
-Burst Type (sequential & Interleave)
4 banks operation
All inputs are sampled at the positive edge of
the system clock
Burst Read single write operation
Auto & Self refresh
4096 refresh cycle
DQM for masking
Package:86-pins 400 mil TSOP-Type II
Ordering Information.
Part No.
Frequency
Interface
Package
VDS6632A4A-5 200Mhz LVTTL
400mil
86pin
TSOPII
VDS6632A4A-5.5 183Mhz
LVTTL 400mil
86pin
TSOPII
VDS6632A4A-6 166Mhz LVTTL
400mil
86pin
TSOPII
Pin Assignment
1
2
3
4
5
6
7
8
9
V
D D
D Q0
V
D D Q
D Q1
D Q2
V
S S Q
D Q3
D Q4
V
D D Q
86
85
84
83
82
81
80
79
78
66
65
64
63
62
61
60
59
58
V
S S
DQ15
V
S SQ
DQ14
DQ13
V
D D Q
DQ12
DQ11
V
S SQ
10
11
12
13
14
15
16
17
18
19
20
D Q 5
D Q 6
V
S S Q
D Q 7
N C
V
D D
D Q M 0
W E
CA S
RA S
CS
77
76
75
74
73
72
71
70
69
68
67
DQ10
D Q 9
V
D D Q
D Q 8
N C
V
S S
D Q M 1
N C
N C
C L K
C K E
N C
DQ31
V
D D Q
DQ30
DQ29
V
S S Q
DQ28
DQ27
V
D D Q
DQ26
DQ25
V
S S Q
DQ24
V
S S
21
22
23
24
25
26
27
28
29
N C
B A 0
B A 1
A1 0/A P
A 0
A 1
A 2
D QM 2
V
D D
30
31
32
33
34
35
36
37
38
39
NC
DQ 16
V
S SQ
DQ 17
DQ 18
V
D D Q
DQ 19
DQ 20
V
S SQ
DQ 21
DQ 22
4 0
4 1
4 2
4 3
V
D D Q
D Q 23
V
D D
A9
A8
A7
A6
A5
A4
A3
D Q M 3
V
S S
57
56
55
54
53
52
51
50
49
48
47
46
45
44
86-pin plastic TSOP II 400mil
Rev 1.0 April, 2001
1
V-Data
VDS6632A4A
Pin Description
PIN NAME
FUNCTION
CLK
System Clock
Active on the positive edge to sample all inputs.
CKE Clock
Enable
Masks system clock to freeze operation from the next clock cycle. CKE
should be enabled at least on cycle prior new command. Disable input
buffers for power down in standby
/CS
Chip Select
Disables or Enables device operation by masking or enabling all input
except CLK, CKE and DQM0 ~ DQM3
A0~A11 Address
Row / Column address are multiplexed on the same pins.
Row address : RA0~RA10
Column address : CA0~CA7
BA0~BA1 Banks Select
Selects bank to be activated during row address latch time.
Selects bank for read / write during column address latch time.
DQ0~DQ31 Data
Data inputs / outputs are multiplexed on the same pins.
DQM0~3 Data Mask
Makes data output Hi-Z,
/RAS
Row Address Strobe
Latches row addresses on the positive edge of the CLK with /RAS low
/CAS
Column Address Strobe
Latches Column addresses on the positive edge of the CLK with /CAS low
/WE
Write Enable
Enables write operation and row recharge.
VDD/VSS Power Supply/Ground
Power and Ground for the input buffers and the core logic.
V
DDQ
/V
SSQ
Data Output Power/Ground Power supply for output buffers.
NC
No Connection
This pin is recommended to be left No Connection on the device.
Block Diagram
CLK
CKE
Clock
Generator
Address
/CS
/RAS
/CAS
/WE
DQM
Mode
Register
Command
Decoder
Control
Logic
Row
Decoder
Address
Buffer
&
Refresh
Counter
Column
Address
Buffer
&
Refresh
Counter
Bank0
Bank2
Bank3
Bank1
Amplifier
Column Decoder
Data Control Circuit
Data
Latch
DQ
Rev 1.0 April, 2001
2
V-Data
VDS6632A4A
Absolute Maximum Ratings
Parameter Symbol
Value
Unit
Voltage on any pin relative to Vss
V
IN
, V
out
-1.0
~
4.6
V
Voltage on VDD supply relative to Vss
V
DD
, V
DDQ
-1.0
~
4.6
V
Storage temperature
T
STG
-55 ~ +150
Power dissipation
P
D
1
W
Short circuit current
I
OS
50
mA
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATING are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC Operating Condition
Voltage referenced to Vss = 0V, T
A
= 0 to 70
Parameter Symbol
Min
Typ
Max
Unit
Note
Supply voltage
V
DD
, V
DDQ
3.0 3.3 3.6
V
Input logic high voltage
V
IH
2.0 3.0
V
DD
+0.3 V
1
Input logic low voltage
V
IL
-0.3 0 0.8
V 2
Output logic high voltage
V
OH
2.4 -
- V
I
OH
=-2mA
Output logic low voltage
V
OL
- - 0.4
V
I
OL
=2mA
Input leakage current
I
IL
-5 - 5
uA
3
Output leakage current
I
OL
-5 - 5
uA
4
Note : 1. V
IH
(max)=4.6V AC for pulse width 10ns acceptable.
2.V
IL
(min)=-1.5V AC for pulse width 10ns acceptable.
3.Any
input
0V
V
IN
V
DD
+ 0.3V, all other pins are not under test = 0V.
4.Dout is disabled, 0V V
OUT
V
DD
.
AC Operating Condition
Voltage referenced to Vss = 0V, T
A
= 0 to 70
Parameter Symbol
Value
Unit
Note
AC input high / low level voltage
V
IH
/ V
IL
2.4 / 0.4
V
Input timing measurement reference level voltage
Vtrip
1.4
V
Input rise / fall time
TR / tF
1
Ns
Output timing measurement reference level
Voutfef
1.4
V
Output load capacitance for access time measurement
CL
30
pF
2
Note: 1. 3.15V V
DD
3.6V is applied for VDS6632A4A5.
2. Output load to measure access times is equivalent to two TTL gates and one capacitor (30pF). For details,
refer to AC/DC output load circuit.
Rev 1.0 April, 2001
3
V-Data
VDS6632A4A
Capacitance
TA=25, f-=1Mhz, VDD=3.3V
Parameter Pin
Symbol
Min
Max
Unit
CLK Cl1
2.5
4
pF
Input capacitance
A0~A11,BA0,BA1,CKE,/CS,/RAS,
/CAS,/WE,DQM
Cl2 2.5
5
pF
Data input / output capacitance DQM
CI/O
4
6.5
pF
Output load circuit
V
OH
(DC) = 2.4V,I
OH
= -2mA
V
OL
(DC) = 0.4V,I
OL
= 2mA
3.3 V
1200 ohms
870 ohms
50 pF
Output
DC Characteristics I
Parameter Symbol
Min
Max
Unit
Note
Input leakage current
I
LI
-1
1
uA
1
Output leakage current
I
LO
-1.5
1.5
uA
2
Output high voltage
V
OH
2.4
-
V
I
OH
= -2mA
Output low voltage
V
OL
-
0.4
V
I
OL
= 2mA
Note : 1.V
IN
= 0 TO 3.6V, All other pins are not tested under V
IN
= 0V.
2.D
OUT
is disabled, V
OUT
= 0 to 3.6.
Rev 1.0 April, 2001
4
V-Data
VDS6632A4A
DC Characteristics II
Speed
Parameter Symbol
Test
condition
-5 -5.5 -6
Unit Note
Operating Current
IDD1
Burst length=1, One bank active
tRCtRC(min),I
OL
=0mA
210 200 190 mA 1
IDD2P
CKEV
IL
(max), tCK=min
2
Precharge standby
current in power down
mode
IDD2PS
CKEV
IL
(max), tCK=
2
mA
IDD2N
CKEV
IH
(min), /CSV
IH
(min),
tCK=min input signals are
changed one time during 2clks. All
other pins VDD-0.2V or
0.2V
15
Precharge standby
current in Non power
down mode
IDD2NS
CKEV
IH
(min), tCK=
Input signals are stable.
12
mA
IDD3P
CKEV
IL
(max), tCK=min
6
Active standby current
in power down mode IDD3PS
CKEV
IL
(max), tCK=
5
mA
IDD3N
CKEV
IH
(min), /CSV
IH
(min),
tCK=min input signals are
changed one time during 2clks. All
other pins VDD-0.2V or
0.2V
30
Active standby current
in Non power down
mode
IDD3NS
CKEV
IH
(min), tCK=
Input signals are stable.
20
mA
Burst mode operating
current
IDD4
t
CK
t
CK
(min),I
OL
=0 mA
All banks active
280 270 260 mA 1
Auto refresh current
IDD5
tRRCtRRC(min), All banks
active
250 240 230 mA 2
Self refresh current
IDD6
CKE0.2V
1 mA
Note: 1. IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output
open.
2. Min. of tRRC is shown at AC characteristics.
Rev 1.0 April, 2001
5
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