Document Outline

• ProASIC3 Flash Family FPGAs
  • Features and Benefits
    • Table 1 . ProASIC3 Product Family
  • Ordering Information
    • Figure 1 . Ordering Information
• Introduction and Overview
  • General Description
    • Figure 1-1 . ProASIC3 Device Architecture Overview with Two I/O Banks (A3P030, A3P060, A3P125)
    • Figure 1-2 . ProASIC3 Device Architecture Overview with Four I/O Banks (A3P250, A3P400, A3P600, and A3P1000)
    • Figure 1-3 . VersaTile Configurations
  • Related Documents
• Device Architecture
  • Introduction
    • Figure 2-1 . ProASIC3 Flash-Based Switch
  • Device Overview
    • Figure 2-2 . ProASIC3 Device Architecture Overview with Two I/O Banks (A3P030, A3P060, A3P125)
    • Figure 2-3 . ProASIC3 Device Architecture Overview with Four I/O Banks (A3P250, A3P400, A3P600, A3P1000)
    • Figure 2-4 . ProASIC3 Core VersaTile
    • Table 2-1 . ProASIC3 Array Coordinates
    • Figure 2-5 . Array Coordinates for A3P600
    • Figure 2-6 . Ultra-Fast Local Lines Connected to the Eight Nearest Neighbors
    • Figure 2-7 . Efficient Long-Line Resources
    • Figure 2-8 . Very-Long-Line Resources
    • Figure 2-9 . Overview of ProASIC3 VersaNet Global Network
    • Figure 2-10 . Global Network Architecture
    • Table 2-2 . ProASIC3 Globals/Spines/Rows by Device
    • Figure 2-11 . Spines in a Global Clock Tree Network
    • Clock Aggregation
      • Figure 2-12 . Spine Selection MUX of Global Tree
      • Figure 2-13 . Clock Aggregation Tree Architecture
    • Clock Conditioning Circuits
      • Figure 2-14 . ProASIC3 CCC Options
      • Figure 2-15 . Clock Input Sources Including CLKBUF, CLKBUF_LVDS/LVPECL, and CLKINT
      • Figure 2-16 . CLKBUF and CLKINT
      • Table 2-3 . Available Selections of I/O Standards within CLKBUF and CLKBUF_LVDS/LVPECL Macros
      • Figure 2-17 . CCC/PLL Macro
      • Figure 2-18 . CLKDLY
      • Table 2-4 . ProASIC3 CCC/PLL Specification
      • Figure 2-19 . PLL Block
    • Nonvolatile Memory (NVM)
      • Figure 2-20 . FROM Architecture
    • SRAM and FIFO
      • Figure 2-21 . Supported Basic RAM Macros
      • Figure 2-22 . ProASIC3 RAM Block with Embedded FIFO Controller
      • Table 2-5 . Allowable Aspect Ratio Settings for WIDTHA[1:0]
      • Table 2-6 . Address Pins Used for Various Supported Bus Widths
      • Table 2-7 . Data Pins Used for Various Supported Bus Widths
      • Table 2-8 . Aspect Ratio Settings for WW[1:0]
      • Table 2-9 . Aspect Ratio Settings for WW[2:0]
      • Table 2-10 . Input Data Signal Usage for Different Aspect Ratios
      • Table 2-11 . ProASIC3 Supported I/O Standards
      • Table 2-12 . VCCI Voltages and Compatible Standards
      • Table 2-13 . I/O Features
      • Table 2-14 . Maximum I/O Frequency for Single-Ended and Differential I/Os (maximum drive strength and high slew selected)
      • Figure 2-23 . I/O Block Logical Representation
      • Figure 2-24 . DDR Input Register Support in ProASIC3 Devices
      • Figure 2-25 . DDR Output Support for ProASIC3 Devices
      • Table 2-15 . Levels of Hot-Swap Support
      • Table 2-16 . ProASIC3I/O Hot-Swap and 5 V Input Tolerance Capabilities
      • Figure 2-26 . Solution 1
      • Figure 2-27 . Solution 2
      • Figure 2-28 . Solution 3
      • Figure 2-29 . Solution 4
      • Table 2-17 . Comparison Table for 5 V Compliant Receiver Scheme
    • Selectable Skew between Output Buffer Enable/Disable Time
      • Figure 2-30 . Block Diagram of Output Enable Path
      • Figure 2-31 . Timing Diagram (Option1: Bypasses Skew Circuit)
      • Figure 2-32 . Timing Diagram (Option 2: With Skew Circuit Selected)
      • Figure 2-33 . Example of Implementation of Skew Circuits in Bidirectional Transmission Systems Using ProASIC3 Devices
      • Figure 2-34 . Timing Diagram (Bypasses Skew Circuit)
      • Figure 2-35 . Timing Diagram (with Skew Circuit Selected)
      • Table 2-18 . I/O Attributes vs. I/O Standard Applications
      • Table 2-19 . I/O Default Attributes
      • Table 2-20 . A3P030 I/O Standards-OUT_DRIVE Settings
      • Table 2-21 . ProASIC3 Device I/O Standards-SLEW and OUT_DRIVE Settings
      • Figure 2-36 . Naming Conventions of ProASIC3 Devices with Two I/O Banks
      • Figure 2-37 . Naming Conventions of ProASIC3 Devices with Four I/O Banks
  • Pin Descriptions
  • Software Tools
  • Programming
  • Security
  • ISP
    • Figure 2-38 . Boundary-Scan Chain in ProASIC3
    • Table 2-22 . Boundary-Scan Opcodes
• DC and Switching Characteristics
  • General Specifications
    • Table 3-1 . Absolute Maximum Ratings
    • Table 3-2 . Recommended Operating Conditions
    • Table 3-3 . Overshoot and Undershoot Limits (as measured on quiet I/Os)1
    • Table 3-4 . Flash Programming, Storage, and Operating Limits
    • I/O Power-Up and Supply Voltage Thresholds for Power-On Reset (Commercial and Industrial)
      • Figure 3-1 . I/O State as a Function of VCCI and VCC Voltage Levels
    • Thermal Characteristics
      • Table 3-5 . Package Thermal Resistivities
      • Table 3-6 . Temperature and Voltage Derating Factors for Timing Delays (Normalized to TJ = 70C, VCC = 1.425 V)
  • Calculating Power Dissipation
    • Table 3-7 . Quiescent Supply Current Characteristics
    • Table 3-8 . Summary of I/O Input Buffer Power (Per Pin) - Default I/O Software Settings
    • Table 3-9 . Summary of I/O Output Buffer Power (Per Pin) - Default I/O Software Settings1
    • Power Consumption of Various Internal Resources
      • Table 3-10 . Different Components Contributing to Dynamic Power Consumption in ProASIC3 Devices
    • Power Calculation Methodology
      • Table 3-11 . Toggle Rate Guidelines Recommended for Power Calculation
      • Table 3-12 . Enable Rate Guidelines Recommended for Power Calculation
  • User I/O Characteristics
    • Figure 3-2 . Timing Model Operating Conditions: -2 Speed, Commercial Temperature Range (TJ = 70C), Worst Case VCC =1.425 V
    • Figure 3-3 . Input Buffer Timing Model and Delays (example)
    • Figure 3-4 . Output Buffer Model and Delays (example)
    • Figure 3-5 . Tristate Output Buffer Timing Model and Delays (example)
    • Overview of I/O Performance
      • Table 3-13 . Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and Industrial Conditions
      • Table 3-14 . Summary of Maximum and Minimum DC Input Levels Applicable to Commercial and Industrial Conditions
      • Table 3-15 . Summary of AC Measuring Points
      • Table 3-16 . I/O AC Parameter Definitions
      • Table 3-17 . Summary of I/O Timing Characteristics-Software Default Settings Commercial-Case Conditions: TJ = 70C, Worst Case VCC = 1.425 V, Worst Case VCCI = 3.0 V
      • Table 3-18 . Input Capacitance
      • Table 3-19 . I/O Output Buffer Maximum Resistances1
      • Table 3-20 . I/O Weak Pull-Up/Pull-Down Resistances Minimum and Maximum Weak Pull-Up/Pull-Down Resistance Values
      • Table 3-21 . I/O Short Currents IOSH/IOSL
      • Table 3-22 . Short Current Event Duration before Failure
      • Table 3-23 . I/O Input Rise Time, Fall Time, and Related I/O Reliability
    • Single Ended I/O Characteristics
      • Table 3-24 . Minimum and Maximum DC Input and Output Levels
      • Figure 3-6 . AC Loading
      • Table 3-25 . AC Waveforms, Measuring Points and Capacitive Loads
      • Table 3-26 . 3.3 V LVTTL / 3.3 V LVCMOS Low Slew Commercial-Case Conditions: TJ = 70C, Worst Case VCC = 1.425 V, Worst Case VCCI = 3.0 V
      • Table 3-27 . 3.3 V LVTTL / 3.3 V LVCMOS High Slew Commercial-Case Conditions: TJ = 70C, Worst Case VCC = 1.425 V, Worst Case VCCI = 3.0 V
      • Table 3-28 . Minimum and Maximum DC Input and Output Levels
      • Figure 3-7 . AC Loading
      • Table 3-29 . AC Waveforms, Measuring Points and Capacitive Loads
      • Table 3-30 . 2.5 V LVCMOS Low Slew Commercial-Case Conditions: TJ = 70C, Worst Case VCC = 1.425 V, Worst Case VCCI = 2.3 V
      • Table 3-31 . 2.5 V LVCMOS High Slew Commercial-Case Conditions: TJ = 70C, Worst Case VCC = 1.425 V, Worst Case VCCI = 2.3 V
      • Table 3-32 . Minimum and Maximum DC Input and Output Levels
      • Figure 3-8 . AC Loading
      • Table 3-33 . AC Waveforms, Measuring Points and Capacitive Loads
      • Table 3-34 . 1.8 V LVCMOS Low Slew Commercial-Case Conditions: TJ = 70C, Worst Case VCC = 1.425 V, Worst Case VCCI = 1.7 V
      • Table 3-35 . 1.8 V LVCMOS High Slew Commercial-Case Conditions: TJ = 70C, Worst Case VCC = 1.425 V, Worst Case VCCI = 1.7 V
      • Table 3-36 . Minimum and Maximum DC Input and Output Levels
      • Figure 3-9 . AC Loading
      • Table 3-37 . AC Waveforms, Measuring Points and Capacitive Loads
      • Table 3-38 . 1.5 V LVCMOS Low Slew Commercial-Case Conditions: TJ = 70C, Worst Case VCC = 1.425 V, Worst Case VCCI = 1.4 V
      • Table 3-39 . 1.5 V LVCMOS High Slew Commercial-Case Conditions: TJ = 70C, Worst Case VCC = 1.425 V, Worst Case VCCI = 1.4 V
      • Table 3-40 . Minimum and Maximum DC Input and Output Levels
      • Figure 3-10 . AC Loading
      • Table 3-41 . AC Waveforms, Measuring Points and Capacitive Loads
      • Table 3-42 . 3.3 V PCI/PCI-X Commercial-Case Conditions: TJ = 70C, Worst Case VCC = 1.425 V, Worst Case VCCI = 3.0 V
    • Differential I/O Characteristics
      • Figure 3-11 . LVDS Circuit Diagram and Board-Level Implementation
      • Table 3-43 . Minimum and Maximum DC Input and Output Levels
      • Table 3-44 . AC Waveforms, Measuring Points and Capacitive Loads
      • Table 3-45 . LVDS Commercial-Case Conditions: TJ = 70C, Worst Case VCC = 1.425 V, Worst Case VCCI = 2.3 V
      • Figure 3-12 . LVPECL Circuit Diagram and Board-Level Implementation
      • Table 3-46 . Minimum and Maximum DC Input and Output Levels
      • Table 3-47 . AC Waveforms, Measuring Points and Capacitive Loads
      • Table 3-48 . LVPECL Commercial-Case Conditions: TJ = 70C, Worst Case VCC = 1.425 V, Worst Case VCCI = 3.0 V
    • I/O Register Specifications
      • Figure 3-13 . Timing Model of Registered I/O Buffers with Synchronous Enable and Asynchronous Preset
      • Table 3-49 . Parameter Definition and Measuring Nodes
      • Figure 3-14 . Timing Model of the Registered I/O Buffers with Synchronous Enable and Asynchronous Clear
      • Table 3-50 . Parameter Definition and Measuring Nodes
      • Figure 3-15 . Input Register Timing Diagram
      • Table 3-51 . Input Data Register Propagation Delays Commercial-Case Conditions: TJ = 70C, Worst Case VCC = 1.425 V
      • Figure 3-16 . Output Register Timing Diagram
      • Table 3-52 . Output Data Register Propagation Delays Commercial-Case Conditions: TJ = 70C, Worst Case VCC = 1.425 V
      • Figure 3-17 . Output Enable Register Timing Diagram
      • Table 3-53 . Output Enable Register Propagation Delays Commercial-Case Conditions: TJ = 70C, Worst Case VCC = 1.425 V
    • DDR Module Specifications
      • Figure 3-18 . Input DDR Timing Model
      • Table 3-54 . Parameter Definitions
      • Table 3-55 . Input DDR Timing Diagram
      • Table 3-56 . Input DDR Propagation Delays Commercial-Case Conditions: TJ = 70C, Worst Case VCC = 1.425 V
      • Figure 3-19 . Output DDR Timing Model
      • Table 3-57 . Parameter Definitions
      • Figure 3-20 . Output DDR Timing Diagram
      • Table 3-58 . Output DDR Propagation Delays Commercial-Case Conditions: TJ = 70C, Worst Case VCC = 1.425 V
  • VersaTile Characteristics
    • Figure 3-21 . Sample of Combinatorial Cells
    • Figure 3-22 . Timing Model and Waveforms
    • Table 3-59 . Combinatorial Cell Propagation Delays Commercial-Case Conditions: TJ = 70C, Worst Case VCC = 1.425 V
    • Figure 3-23 . Sample of Sequential Cells
    • Figure 3-24 . Timing Model and Waveforms
    • Table 3-60 . Register Delays Commercial-Case Conditions: TJ = 70C, Worst Case VCC = 1.425 V
  • Global Resource Characteristics
    • Figure 3-25 . Example of Global Tree Use in an A3P250 Device for Clock Routing
    • Global Tree Timing Characteristics
      • Table 3-61 . A3P030 Global Resource Commercial-Case Conditions: TJ = 70C, VCC = 1.425 V
      • Table 3-62 . A3P060 Global Resource Commercial-Case Conditions: TJ = 70C, VCC = 1.425 V
      • Table 3-63 . A3P125 Global Resource Commercial-Case Conditions: TJ = 70C, VCC = 1.425 V
      • Table 3-64 . A3P250 Global Resource Commercial-Case Conditions: TJ = 70C, VCC = 1.425V
      • Table 3-65 . A3P400 Global Resource Commercial-Case Conditions: TJ = 70C, VCC = 1.425 V
      • Table 3-66 . A3P600 Global Resource Commercial-Case Conditions: TJ = 70C, VCC = 1.425 V
      • Table 3-67 . A3P1000 Global Resource Commercial-Case Conditions: TJ = 70C, VCC = 1.425 V
  • Embedded SRAM and FIFO Characteristics
    • Figure 3-26 . RAM Models
    • Figure 3-27 . RAM Read for Flow-Through Output
    • Figure 3-28 . RAM Read for Pipelined Output
    • Figure 3-29 . RAM Write, Output Retained (WMODE = 0)
    • Figure 3-30 . RAM Write, Output as Write Data (WMODE = 1)
    • Figure 3-31 . One Port Write/Other Port Read Same
    • Figure 3-32 . RAM Reset
    • Table 3-68 . RAM4K9 Commercial-Case Conditions: TJ = 70C, Worst Case VCC = 1.425 V
    • Table 3-69 . RAM512X18 Commercial-Case Conditions: TJ = 70C, Worst Case VCC = 1.425 V
    • Figure 3-33 . FIFO Model
    • Figure 3-34 . FIFO Reset
    • Figure 3-35 . FIFO Reset, Empty Flag, and Almost-Empty Flag
    • Figure 3-36 . FIFO FULL and AFULL Flag
    • Figure 3-37 . EMPTY Flag and AEMPTY Flag Deassertion
    • Figure 3-38 . FULL and ALFULL Deassertion
    • Table 3-70 . FIFO Commercial-Case Conditions: TJ = 70C, VCC = 1.425 V
  • Embedded FROM Characteristics
    • Figure 3-39 . Timing Diagram
    • Table 3-71 . Embedded FROM Access Time
  • JTAG 1532 Characteristics
    • Table 3-72 . JTAG 1532 Commercial-Case Conditions: TJ = 70C, worst-case VCC = 1.425 V
• Package Pin Assignments
  • 132-Pin QFN
  • 100-Pin VQFP
  • 144-Pin TQFP
  • 208-Pin PQFP
  • 144-Pin FBGA
  • 256-Pin FBGA
  • 484-Pin FBGA
• Datasheet Information
  • Datasheet Categories
  • International Traffic in Arms Regulations (ITAR) and Export Administration Regulations (EAR)