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Электронный компонент: 5962-8964701PA

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CONNECTION DIAGRAM
Plastic DIP (N),
Small Outline (R) and
Cerdip (Q) Packages
REV. F
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
High Speed, Low Power
Monolithic Op Amp
AD847
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
FEATURES
Superior Performance
High Unity Gain BW: 50 MHz
Low Supply Current: 5.3 mA
High Slew Rate: 300 V/ s
Excellent Video Specifications
0.04% Differential Gain (NTSC and PAL)
0.19 Differential Phase (NTSC and PAL)
Drives Any Capacitive Load
Fast Settling Time to 0.1% (10 V Step): 65 ns
Excellent DC Performance
High Open-Loop Gain 5.5 V/mV (R
LOAD
= 1 k )
Low Input Offset Voltage: 0.5 mV
Specified for 5 V and 15 V Operation
Available in a Wide Variety of Options
Plastic DIP and SOIC Packages
Cerdip Package
Die Form
MIL-STD-883B Processing
Tape & Reel (EIA-481A Standard)
Dual Version Available: AD827 (8 Lead)
Enhanced Replacement for LM6361
Replacement for HA2544, HA2520/2/5 and EL2020
APPLICATIONS
Video Instrumentation
Imaging Equipment
Copiers, Fax, Scanners, Cameras
High Speed Cable Driver
High Speed DAC and Flash ADC Buffers
PRODUCT DESCRIPTION
The AD847 represents a breakthrough in high speed amplifiers
offering superior ac & dc performance and low power, all at low
cost. The excellent dc performance is demonstrated by its
5 V
6
4
0
20
5.5
4.5
5
5
10
15
SUPPLY VOLTAGE
Volts
QUIESCENT CURRENT mA
Quiescent Current vs. Supply Voltage
specifications which include an open-loop gain of 3500 V/V
(500
load) and low input offset voltage of 0.5 mV. Common-
mode rejection is a minimum of 78 dB. Output voltage swing is
3 V into loads as low as 150
. Analog Devices also offers
over 30 other high speed amplifiers from the low noise AD829
(1.7 nV/
Hz
) to the ultimate video amplifier, the AD811, which
features 0.01% differential gain and 0.01
differential phase.
APPLICATION HIGHLIGHTS
1. As a buffer the AD847 offers a full-power bandwidth of
12.7 MHz (5 V p-p with
5 V supplies) making it outstand-
ing as an input buffer for flash A/D converters.
2. The low power and small outline package of the AD847
make it very well suited for high density applications such as
multiple pole active filters.
3. The AD847 is internally compensated for unity gain opera-
tion and remains stable when driving any capacitive load.
AD847 Driving Capacitive Loads
AD847SPECIFICATIONS
REV. F
2
(@ T
A
= +25 C, unless otherwise noted)
Model
AD847J
AD847AR
Conditions
V
S
Min
Typ
Max
Min
Typ
Max
Units
INPUT OFFSET VOLTAGE
1
5 V
0.5
1
0.5
1
mV
T
MIN
to T
MAX
3.5
4
mV
Offset Drift
15
15
V/
C
INPUT BIAS CURRENT
5 V,
15 V
3.3
6.6
3.3
6.6
A
T
MIN
to T
MAX
7.2
10
A
INPUT OFFSET CURRENT
5 V,
15 V
50
300
50
300
nA
T
MIN
to T
MAX
400
500
nA
Offset Current Drift
0.3
0.3
nA/
C
OPEN-LOOP GAIN
V
OUT
=
2.5 V
5 V
R
LOAD
= 500
2
3.5
2
3.5
V/mV
T
MIN
to T
MAX
1
1
V/mV
R
LOAD
= 150
1.6
1.6
V/mV
V
OUT
=
10 V
15 V
R
LOAD
= 1 k
3
5.5
3
5.5
V/mV
T
MIN
to T
MAX
1.5
1.5
V/mV
DYNAMIC PERFORMANCE
Unity Gain Bandwidth
5 V
35
35
MHz
15 V
50
50
MHz
Full Power Bandwidth
2
V
OUT
= 5 V p-p
R
LOAD
= 500
,
5 V
12.7
12.7
MHz
V
OUT
= 20 V p-p,
R
LOAD
= 1 k
15 V
4.7
4.7
MHz
Slew Rate
3
R
LOAD
= 1 k
5 V
200
200
V/
s
15 V
225
300
225
300
V/
s
Settling Time
to 0.1%, R
LOAD
= 250
2.5 V to +2.5 V
5 V
65
65
ns
10 V Step, A
V
= 1
15 V
65
65
ns
to 0.01%, R
LOAD
= 250
2.5 V to +2.5 V
5 V
140
140
ns
10 V Step, A
V
= 1
15 V
120
120
ns
Phase Margin
C
LOAD
= 10 pF
15 V
R
LOAD
= 1 k
50
50
Degree
Differential Gain
f
4.4 MHz, R
LOAD
= 1 k
15 V
0.04
0.04
%
Differential Phase
f
4.4 MHz, R
LOAD
= 1 k
15 V
0.19
0.19
Degree
COMMON-MODE REJECTION
V
CM
=
2.5 V
5 V
78
95
78
95
dB
V
CM
=
12 V
15 V
78
95
78
95
dB
T
MIN
to T
MAX
75
75
dB
POWER SUPPLY REJECTION
V
S
=
5 V to
15 V
75
86
75
86
dB
T
MIN
to T
MAX
72
72
dB
INPUT VOLTAGE NOISE
f = 10 kHz
15 V
15
15
nV/
Hz
INPUT CURRENT NOISE
f = 10 kHz
15 V
1.5
1.5
pA/
Hz
INPUT COMMON-MODE
VOLTAGE RANGE
5 V
+4.3
+4.3
V
3.4
3.4
V
15 V
+14.3
+14.3
V
13.4
13.4
V
OUTPUT VOLTAGE SWING
R
LOAD
= 500
5 V
3.0
3.6
3.0
3.6
V
R
LOAD
= 150
5 V
2.5
3
2.5
3
V
R
LOAD
= 1 k
15 V
12
12
V
R
LOAD
= 500
15 V
10
10
V
Short-Circuit Current
15 V
32
32
mA
INPUT RESISTANCE
300
300
k
INPUT CAPACITANCE
1.5
1.5
pF
OUTPUT RESISTANCE
Open Loop
15
15
POWER SUPPLY
Operating Range
4.5
18
4.5
18
V
Quiescent Current
5 V
4.8
6.0
4.8
6.0
mA
T
MIN
to T
MAX
7.3
7.3
mA
15 V
5.3
6.3
5.3
6.3
mA
T
MIN
to T
MAX
7.6
7.6
mA
N
OTES
l
Input Offset Voltage Specifications are guaranteed after 5 minutes at T
A
= +25
C.
2
Full Power Bandwidth = Slew Rate/2
V
PEAK
.
3
Slew Rate is measured on rising edge.
All min and max specifications are guaranteed. Specifications in boldface are 100% tested at final electrical test.
Specifications subject to change without notice.
AD847
REV. F
3
Model
AD847AQ
AD847S
Conditions
V
S
Min
Typ
Max
Min
Typ
Max
Units
INPUT OFFSET VOLTAGE
1
5 V
0.5
1
0.5
1
mV
T
MIN
to T
MAX
4
4
mV
Offset Drift
15
15
V/
C
INPUT BIAS CURRENT
5 V,
15 V
3.3
5
3.3
5
A
T
MIN
to T
MAX
7.5
7.5
A
INPUT OFFSET CURRENT
5 V,
15 V
50
300
50
300
nA
T
MIN
to T
MAX
400
400
nA
Offset Current Drift
0.3
0.3
nA/
C
OPEN-LOOP GAIN
V
OUT
=
2.5 V
5 V
R
LOAD
= 500
2
3.5
2
3.5
V/mV
T
MIN
to T
MAX
1
1
V/mV
R
LOAD
= 150
1.6
1.6
V/mV
V
OUT
= =
10 V
15 V
R
LOAD
= 1 k
3
5.5
3
5.5
V/mV
T
MIN
to T
MAX
1.5
1.5
V/mV
DYNAMIC PERFORMANCE
Unity Gain Bandwidth
5 V
35
35
MHz
15 V
50
50
MHz
Full Power Bandwidth
2
V
OUT
= 5 V p-p
R
LOAD
= 500
,
5 V
12.7
12.7
MHz
V
OUT
= 20 V p-p,
R
LOAD
= 1 k
15 V
4.7
4.7
MHz
Slew Rate
3
R
LOAD
= 1 k
5 V
200
200
V/
s
15 V
225
300
225
300
V/
s
Settling Time
to 0.1%, R
LOAD
= 250
2.5 V to +2.5 V
5 V
65
65
ns
10 V Step, A
V
= 1
15 V
65
65
ns
to 0.01%, R
LOAD
= 250
2.5 V to +2.5 V
5 V
140
140
ns
10 V Step, A
V
= 1
15 V
120
120
ns
Phase Margin
C
LOAD
= 10 pF
15 V
R
LOAD
= 1 k
50
50
Degree
Differential Gain
f
4.4 MHz, R
LOAD
= 1 k
15 V
0.04
0.04
%
Differential Phase
f
4.4 MHz, R
LOAD
= 1 k
15 V
0.19
0.19
Degree
COMMON-MODE REJECTION
V
CM
=
2.5 V
5 V
80
95
80
95
dB
V
CM
=
12 V
15 V
80
95
80
95
dB
T
MIN
to T
MAX
75
75
dB
POWER SUPPLY REJECTION
V
S
=
5 V to
15 V
75
86
75
86
dB
T
MIN
to T
MAX
72
72
dB
INPUT VOLTAGE NOISE
f = 10 kHz
15 V
15
15
nV/
Hz
INPUT CURRENT NOISE
f = 10 kHz
15 V
1.5
1.5
pA/
Hz
INPUT COMMON-MODE
VOLTAGE RANGE
5 V
+4.3
+4.3
V
3.4
3.4
V
15 V
+14.3
+14.3
V
13.4
13.4
V
OUTPUT VOLTAGE SWING
R
LOAD
= 500
5 V
3.0
3.6
3.0
3.6
V
R
LOAD
= 150
5 V
2.5
3
2.5
3
V
R
LOAD
= 1 k
15 V
12
12
V
R
LOAD
= 500
15 V
10
10
V
Short-Circuit Current
15 V
32
32
mA
INPUT RESISTANCE
300
300
k
INPUT CAPACITANCE
1.5
1.5
pF
OUTPUT RESISTANCE
Open Loop
15
15
POWER SUPPLY
Operating Range
4.5
18
4.5
18
V
Quiescent Current
5 V
4.8
5.7
4.8
5.7
mA
T
MIN
to T
MAX
7.0
7.8
mA
15 V
5.3
6.3
5.3
6.3
mA
T
MIN
to T
MAX
7.6
8.4
mA
AD847
REV. F
4
ABSOLUTE MAXIMUM RATINGS
1
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18 V
Internal Power Dissipation
2
Plastic (N) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Watts
Small Outline (R) . . . . . . . . . . . . . . . . . . . . . . . . . 0.8 Watts
Cerdip (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Watts
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
V
S
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . .
6 V
Storage Temperature Range (Q) . . . . . . . . . 65
C to +150
C
(N, R) . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
C to +125
C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 175
C
Lead Temperature Range (Soldering 60 sec) . . . . . . . +300
C
NOTES
1
Stresses above those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only, and functional
operation of the device at these or any other conditions above those indicated in
the operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2
Mini-DIP Package:
JA
= 100
C/Watt;
JC
= 33
C/Watt
Cerdip Package:
JA
= 110
C/Watt;
JC
= 30
C/Watt
Small Outline Package:
JA
= 155
C/Watt;
JC
= 33
C/Watt
ESD SUSCEPTIBILITY
ESD (electrostatic discharge) sensitive device. Electrostatic
charges as high as 4000 volts, which readily accumulate on the
human body and on test equipment, can discharge without de-
tection. Although the AD847 features proprietary ESD protec-
tion circuitry, permanent damage may still occur on these
devices if they are subjected to high energy electrostatic dis-
charges. Therefore, proper ESD precautions are recommended
to avoid any performance degradation or loss of functionality.
METALIZATION PHOTOGRAPH
Contact factory for latest dimensions.
Dimensions shown in inches and (mm).
ORDERING GUIDE
Temperature
Package
Package
Models*
Range C
Description
Option
AD847JN
0 to +70
Plastic
N-8
AD847JR
0 to +70
SOIC
R-8
AD847AQ
40 to +85
Cerdip
Q-8
AD847AR
40 to +85
SOIC
R-8
AD847SQ
55 to +125
Cerdip
Q-8
AD847SQ/883B
55 to +125
Cerdip
Q-8
5962-8964701PA
55 to +125
Cerdip
Q-8
*AD847 also available in J and S grade chips, and AD847JR and AD847AR are available
*
in tape and reel.
AD847
REV. F
5
Typical Characteristics
(@ +25 C and V
S
= 15 V, unless otherwise noted)
20
0
0
20
15
5
5
10
10
15
INPUT COMMON-MODE RANGE
Volts
SUPPLY VOLTAGE
Volts
V
IN
+V
IN
Figure 1. Input Common-Mode Range vs. Supply Voltage
15 V SUPPLIES
30
0
10k
15
5
100
10
10
20
1k
25
LOAD RESISTANCE
OUTPUT VOLTAGE SWING Volts p-p
5V SUPPLIES
Figure 3. Output Voltage Swing vs. Load Resistance
60
140
40
120
100
80
60
40
20
0
20
5
4
3
2
TEMPERATURE
C
INPUT BIAS CURRENT
A
V =
5V
S
Figure 5. Input Bias Current vs. Temperature
20
0
0
20
15
5
5
10
10
15
SUPPLY VOLTAGE
Volts
OUTPUT VOLTAGE SWING Volts
+V
OUT
V
OUT
R = 500
LOAD
Figure 2. Output Voltage Swing vs. Supply Voltage
6
4
0
20
5.5
4.5
5
5
10
15
SUPPLY VOLTAGE
Volts
QUIESCENT CURRENT mA
Figure 4. Quiescent Current vs. Supply Voltage
100
0.01
10k
100M
10
0.1
100k
1
1M
10M
FREQUENCY Hz
OUTPUT IMPEDANCE
Figure 6. Output Impedance vs. Frequency
AD847Typical Characteristics
(@ +25 C and V
S
= 15 V, unless otherwise noted)
REV. F
6
35
15
140
20
40
60
25
30
120
100
80
60
40
20
0
20
AMBIENT TEMPERATURE
C
SHORT CIRCUIT CURRENT LIMIT mA
Figure 8. Short-Circuit Current Limit vs. Temperature
100
20
100M
40
0
1k
20
100
80
60
10M
1M
100k
10k
+100
+80
+60
+40
+20
0
PHASE MARGIN DEGREES
FREQUENCY Hz
OPEN -LOOP GAIN dB
15V SUPPLIES
5V SUPPLIES
1k
LOAD
500
LOAD
Figure 10. Open-Loop Gain and Phase Margin
vs. Frequency
100
0
100M
60
20
10k
40
1k
80
10M
1M
100k
+SUPPLY
SUPPLY
FREQUENCY Hz
POWER SUPPLY REJECTION dB
Figure 12. Power Supply Rejection vs. Frequency
7
3
140
4
40
60
5
6
120
100
80
60
40
20
0
20
TEMPERATURE
C
QUIESCENT CURRENT mA
V =
5V
S
Figure 7. Quiescent Current vs. Temperature
52
48
60
140
51
49
40
50
100
120
80
60
40
20
0
20
TEMPERATURE
C
UNITY GAIN BANDWIDTH MHz
Figure 9. Gain Bandwidth Product vs. Temperature
80
50
10k
65
55
100
60
10
75
70
1k
V =
5V
S
V =
15V
S
LOAD RESISTANCE
OPEN-LOOP GAIN dB
Figure 11. Open-Loop Gain vs. Load Resistance
AD847
REV. F
7
30
0
100M
15
10M
10
1M
25
20
5
INPUT FREQUENCY Hz
OUTPUT VOLTAGE Volts pp
R = 1k
L
Figure 14. Large Signal Frequency Response
70
130
100
100k
90
110
1k
10k
80
100
120
HARMONIC DISTORTION dB
FREQUENCY Hz
3V RMS
R =1k
L
2ND HARMONIC
3RD HARMONIC
Figure 16. Harmonic Distortion vs. Frequency
450
150
140
300
200
40
250
60
400
350
120
80
60
40
100
20
0
20
TEMPERATURE
C
SLEW RATE V/
s
Figure 18. Slew Rate vs. Temperature
100
0
100M
60
20
10k
40
1k
80
10M
1M
100k
FREQUENCY Hz
CMR dB
V =
1V p-p
CM
Figure 13. Common-Mode Rejection vs. Frequency
10
10
160
4
8
20
6
0
2
2
0
4
6
8
140
120
100
80
60
40
OUTPUT SWING FROM 0 TO
V
SETTLING TIME ns
1%
0.1%
1%
0.1%
Figure 15. Output Swing and Error vs. Settling Time
50
0
10M
30
10
100
20
10
40
1M
100k
10k
1k
FREQUENCY Hz
INPUT VOLTAGE NOISE nV/
Hz
Figure 17. Input Voltage Noise Spectral Density
AD847
REV. F
8
Figure 19. Inverting Amplifier Configuration
Figure 19a. Inverter Large
Signal Pulse Response
Figure 19b. Inverter Small
Signal Pulse Response
Figure 20. Noninverting Amplifier Configuration
Figure 20a. Noninverting
Large Signal Pulse Response
Figure 20b. Noninverting
Small Signal Pulse Response
AD847
REV. F
9
OFFSET NULLING
The input offset voltage of the AD847 is very low for a high
speed op amp, but if additional nulling is required, the circuit
shown in Figure 21 can be used.
Figure 21. Offset Nulling
INPUT CONSIDERATIONS
An input resistor (R
IN
in Figure 20) is required in circuits where
the input to the AD847 will be subjected to transient or con-
tinuous overload voltages exceeding the
6 V maximum differ-
ential limit. This resistor provides protection for the input
transistors by limiting the maximum current that can be forced
into their bases.
For high performance circuits it is recommended that a resistor
(R
B
in Figures 19 and 20) be used to reduce bias current errors
by matching the impedance at each input. The offset voltage er-
ror will be reduced by more than an order of magnitude.
THEORY OF OPERATION
The AD847 is fabricated on Analog Devices' proprietary
complementary bipolar (CB) process which enables the con-
struction of pnp and npn transistors with similar f
T
s in the
600 MHz to 800 MHz region. The AD847 circuit (Figure 22)
includes an npn input stage followed by fast pnps in the folded
cascode intermediate gain stage. The CB pnps are also used in
the current amplifying output stage. The internal compensation
capacitance that makes the AD847 unity gain stable is provided
by the junction capacitances of transistors in the gain stage.
The capacitor, C
F
, in the output stage mitigates the effect of ca-
pacitive loads. At low frequencies and with low capacitive
loads, the gain from the compensation node to the output is
very close to unity. In this case C
F
is bootstrapped and does not
contribute to the compensation capacitance of the part. As the
capacitive load is increased, a pole is formed with the output
impedance of the output stage. This reduces the gain, and
therefore, C
F
is incompletely bootstrapped. Some fraction of C
F
contributes to the compensation capacitance, and the unity gain
bandwidth falls. As the load capacitance is increased, the band-
width continues to fall, and the amplifier remains stable.
C
F
IN
+IN
NULL 1
NULL 8
OUTPUT
+V
S
V
S
Figure 22. AD847 Simplified Schematic
GROUNDING AND BYPASSING
In designing practical circuits with the AD847, the user must
remember that whenever high frequencies are involved, some
special precautions are in order. Circuits must be built with
short interconnect leads. A large ground plane should be used
whenever possible to provide a low resistance, low inductance
circuit path, as well as minimizing the effects of high frequency
coupling. Sockets should be avoided because the increased
interlead capacitance can degrade bandwidth.
Feedback resistors should be of low enough value to assure that
the time constant formed with the capacitance at the amplifier
summing junction will not limit the amplifier performance.
Resistor values of less than 5 k
are recommended. If a larger
resistor must be used, a small (<10 pF) feedback capacitor in
parallel with the feedback resistor, R
F
, may be used to compen-
sate for the input capacitances and optimize the dynamic perfor-
mance of the amplifier.
Power supply leads should be bypassed to ground as close as
possible to the amplifier pins. Ceramic disc capacitors of
0.1
F are recommended.
AD847
REV. F
10
VIDEO LINE DRIVER
The AD847 functions very well as a low cost, high speed line
driver for either terminated or unterminated cables. Figure 23
shows the AD847 driving a doubly terminated cable in a fol-
lower configuration.
The termination resistor, R
T
, (when equal to the cable's charac-
teristic impedance) minimizes reflections from the far end of the
cable. While operating from
5 V supplies, the AD847 main-
tains a typical slew rate of 200 V/
s, which means it can drive a
1 V, 30 MHz signal into a terminated cable.
0.1
F
0.1
F
500
500
75
AD847
75
75
R
T
R
BT
C
C
SEE TABLE I
+V
S
V
IN
V
OUT
V
S
IN
R
100
75
COAX
75
COAX
Figure 23. Video Line Driver
Table I. Video Line Driver Performance Chart
Over-
V
IN
*
V
SUPPLY
C
C
3 dB B
W
shoot
0 dB or
500 mV Step
15
20 pF
23 MHz
4%
0 dB or
500 mV Step
15
15 pF
21 MHz
0%
0 dB or
500 mV Step
15
0 pF
13 MHz
0%
0 dB or
500 mV Step
5
20 pF
18 MHz
2%
0 dB or
500 mV Step
5
15 pF
16 MHz
0%
0 dB or
500 mV Step
5
0 pF
11 MHz
0%
*3 dB bandwidth numbers are for the 0 dBm signal input. Overshoot numbers
are the percent overshoot of the 1 volt step input.
A back-termination resistor (R
BT
, also equal to the characteristic
impedance of the cable) may be placed between the AD847 out-
put and the cable input, in order to damp any reflected signals
caused by a mismatch between R
T
and the cable's characteristic
impedance. This will result in a flatter frequency response, al-
though this requires that the op amp supply
2 V to the output
in order to achieve a
1 V swing at resistor R
T
.
Figure 24 shows the AD847 driving 100 pF and 1000 pF loads.
Figure 24. AD847 Driving Capacitive Loads
FLASH ADC INPUT BUFFER
The 35 MHz unity gain bandwidth of the AD847 makes it an
excellent choice for buffering the input of high speed flash A/D
converters, such as the AD9048.
Figure 25 shows the AD847 as a unity inverter for the input to
the AD9048.
AD9048
50
1.5k
10k
2k
0.1
0.1
100
27
2N3906
AD741
5
0.1
F
R
B
R
T
V
IN
V
CC
AD847
1.5k
V
EE
ANALOG
INPUT
(0V TO +2V)
TTL
CONVERT
SIGNAL
0.1
F
0.1
F
5.2V +5.0V
CONVERT
D1
(MSB)
D8
(LSB)
5.2V
43
1k
1k
AD589
Figure 25. Flash ADC Input Buffer
AD847
REV. F
11
A High Speed, Three Op-Amp In-Amp
The circuit of Figure 26 lends itself well to CCD imaging and
other video speed applications. It uses two high speed CB pro-
cess op-amps: Amplifier A3, the output amplifier, is an AD847.
The input amplifier (A1 and A2) is an AD827, which is a dual
version of the AD847. This circuit has the optional flexibility of
both dc and ac trims for common-mode rejection, plus the abil-
ity to adjust for minimum settling time.
PIN 7 AD847,
PIN 8 AD827
1
F
1
F
0.1
F
0.1
F
0.1
F
0.1
F
EACH
AMPLIFIER
+15V
15V
COMM
+V
S
V
S
10
F
10
F
PIN 4
AD847 & AD827
AD847
28pF
SETTLING TIME
AC CMR ADJUST
2k
1.87k
2k
2k
5pF
R
G
V
OUT
200
DC CMR
ADJUST
2k
R
L
CIRCUIT GAIN = + 1
2000
G
R
IN
+V
2
3
1
A1
1/2
AD827
1k
V
IN
6
5
7
A2
1/2
AD827
1k
2
3
6
A3
100Hz
1kHz
10kHz
100kHz
1MHz
88.3dB
87.4dB
86.2dB
67.4dB
47.1dB
INPUT
FREQUENCY
CMRR
THD + NOISE
BELOW INPUT
LEVEL
@ 10kHz
1
2
10
100
OPEN
2k
226
20
28
28
28
28
16.1MHz
14.7MHz
4.5MHz
660kHz
200ns
200ns
370ns
2.5
s
82dB
82dB
81dB
71dB
GAIN
R
G
SMALL
SIGNAL
BANDWIDTH
SETTLING
TIME
TO 0.1%
C
(pF)
ADJ
BANDWIDTH, SETTLING TIME AND TOTAL HARMONIC DISTORTION VS. GAIN
Figure 26. A High Speed In-Amp Circuit for Data Acquisition
AD847
REV. F
12
C1191f109/92
PRINTED IN U.S.A.
HIGH SPEED DAC BUFFER
The wide bandwidth and fast settling time of the AD847 makes
it a very good output buffer for high speed current-output D/A
converters like the AD668. As shown in Figure 27, the op amp
establishes a summing node at ground for the DAC output. The
output voltage is determined by the amplifier's feedback resistor
(10.24 V for a 1 k
resistor). Note that since the DAC gener-
ates a positive current to ground, the voltage at the amplifier
output will be negative. A 100
series resistor between the
noninverting amplifier input and ground minimizes the offset
effects of op amp input bias currents.
1
2
3
7
24
23
22
18
8
9
10
17
16
15
11
12
14
13
4
5
21
20
6
19
AD668
+15V
10
F
TO ANALOG
GROUND PLANE
0.1
F
+
1V NOMINAL
REFERENCE INPUT
10k
1k
100
AD847
ANALOG GROUND PLANE
ANALOG
OUTPUT
ANALOG
SUPPLY
GROUND
0.1
F
10
F
15V
+5V
1k
100pF
DIGITAL
INPUTS
MSB
LSB
V
REFCOM
REFIN1
REFIN2
R
ACOM
LCOM
IBPO
V
THCOM
VTH
EE
LOAD
OUT
CC
I
Figure 27. High Speed DAC Buffer
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
All brand or product names mentioned are trademarks or registered trademarks of their respective holders.
Cerdip (Q-8) Package
0.320 (8.13)
0.290 (7.37)
0.015 (0.38)
0.008 (0.20)
15
0
0.005 (0.13) MIN
0.055 (1.40) MAX
1
PIN 1
4
5
8
0.310 (7.87)
0.220 (5.59)
0.405 (10.29) MAX
0.200
(5.08)
MAX
SEATING
PLANE
0.023 (0.58)
0.014 (0.36)
0.070 (1.78)
0.030 (0.76)
0.060 (1.52)
0.015 (0.38)
0.150
(3.81)
MIN
0.200 (5.08)
0.125 (3.18)
0.100
(2.54)
BSC
Mini-DIP (N-8) Package
0.0110.003
(0.280.08)
0.30 (7.62)
REF
15
0
PIN 1
4
5
8
1
0.25
(6.35)
0.31
(7.87)
0.10
(2.54)
BSC
SEATING
PLANE
0.0350.01
(0.890.25)
0.180.03
(4.570.76)
0.033
(0.84)
NOM
0.0180.003
(0.460.08)
0.125
(3.18)
MIN
0.1650.01
(4.190.25)
0.39 (9.91) MAX
Small Outline (R-8) Package
0.019 (0.48)
0.014 (0.36)
0.050
(1.27)
BSC
0.102 (2.59)
0.094 (2.39)
0.197 (5.01)
0.189 (4.80)
0.010 (0.25)
0.004 (0.10)
0.098 (0.2482)
0.075 (0.1905)
0.190 (4.82)
0.170 (4.32)
0.030 (0.76)
0.018 (0.46)
10
0
0.090
(2.29)
8
0
0.020 (0.051) x 45
CHAMF
1
8
5
4
PIN 1
0.157 (3.99)
0.150 (3.81)
0.244 (6.20)
0.228 (5.79)
0.150 (3.81)