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CONNECTION DIAGRAM
8-Pin Plastic Mini-DIP (N),
Cerdip (Q) and SOIC (R) Packages
X1
X2
Y1
Y2
V
P
OUT
NC
V
N
AD830
NC = NO CONNECT
1
2
3
4
8
7
6
5
A=1
V
1
V
1
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
High Speed, Video
Difference Amplifier
AD830
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
FEATURES
Differential Amplification
Wide Common-Mode Voltage Range: +12.8 V, 12 V
Differential Voltage Range: 2 V
High CMRR: 60 dB @ 4 MHz
Built-in Differential Clipping Level: 2.3 V
Fast Dynamic Performance
85 MHz Unity Gain Bandwidth
35 ns Settling Time to 0.1%
360 V/ s Slew Rate
Symmetrical Dynamic Response
Excellent Video Specifications
Differential Gain Error: 0.06%
Differential Phase Error: 0.08
15 MHz (0.1 dB) Bandwidth
Flexible Operation
High Output Drive of 50 mA min
Specified with Both 5 V and 15 V Supplies
Low Distortion: THD = 72 dB @ 4 MHz
Excellent DC Performance: 3 mV max Input Offset
Voltage
APPLICATIONS
Differential Line Receiver
High Speed Level Shifter
High Speed In-Amp
Differential to Single Ended Conversion
Resistorless Summation and Subtraction
High Speed A/D Driver
PRODUCT DESCRIPTION
The AD830 is a wideband, differencing amplifier designed for
use at video frequencies but also useful in many other applica-
tions. It accurately amplifies a fully differential signal at the
FREQUENCY Hz
CMRR dB
110
30
10M
50
40
1k
70
60
80
90
100
1M
100k
10k
V
S
=
15V
V
S
=
5V
Common-Mode Rejection Ratio vs. Frequency
input and produces an output voltage referred to a user-chosen
level. The undesired common-mode signal is rejected, even at
high frequencies. High impedance inputs ease interfacing to fi-
nite source impedances and thus preserve the excellent
common-mode rejection. In many respects, it offers significant
improvements over discrete difference amplifier approaches, in
particular in high frequency common-mode rejection.
The wide common-mode and differential-voltage range of the
AD830 make it particularly useful and flexible in level shifting
applications, but at lower power dissipation than discrete solu-
tions. Low distortion is preserved over the many possible differ-
ential and common-mode voltages at the input and output.
Good gain flatness and excellent differential gain of 0.06% and
phase of 0.08
make the AD830 suitable for many video system
applications. Furthermore, the AD830 is suited for general pur-
pose signal processing from dc to 10 MHz.
9
6
21
100k
1G
10M
1M
10k
3
0
3
6
18
15
12
9
FREQUENCY Hz
GAIN dB
100M
V
S
=
5V
R
L
= 150
C
L
= 4.7pF
C
L
= 15pF
C
L
= 33pF
Closed-Loop Gain vs. Frequency, Gain = +1
REV. A
2
AD830SPECIFICATIONS
(V
S
= 15 V, R
LOAD
= 150
, C
LOAD
= 5 pF, T
A
= +25 C unless otherwise noted)
AD830J/A
AD830S
1
Parameter
Conditions
Min
Typ
Max
Min
Typ
Max
Units
DYNAMIC CHARACTERISTICS
3 dB Small Signal Bandwidth
Gain = 1, V
OUT
= 100 mV rms
75
85
75
85
MHz
0.1 dB Gain Flatness Frequency
Gain = 1, V
OUT
= 100 mV rms
11
15
11
15
MHz
Differential Gain Error
0 to +0.7 V, Frequency = 4.5 MHz
0.06
0.09
0.06
0.09
%
Differential Phase Error
0 to +0.7 V, Frequency = 4.5 MHz
0.08
0.12
0.08
0.12
Degrees
Slew Rate
2 V Step, R
L
= 500
360
360
V/
s
4 V Step, R
L
= 500
350
350
V/
s
3 dB Large Signal Bandwidth
Gain = 1, V
OUT
= 1 V rms
38
45
38
45
MHz
Settling Time, Gain = 1
V
OUT
= 2 V Step, to 0.1%
25
25
ns
V
OUT
= 4 V Step, to 0.1%
35
35
ns
Harmonic Distortion
2 V p-p, Frequency = 1 MHz
82
82
dBc
2 V p-p, Frequency = 4 MHz
72
72
dBc
Input Voltage Noise
Frequency = 10 kHz
27
27
nV/
Hz
Input Current Noise
1.4
1.4
pA/
Hz
DC PERFORMANCE
Offset Voltage
Gain = 1
1.5
3
1.5
3
mV
Gain = 1, T
MIN
T
MAX
5
7
mV
Open Loop Gain
DC
64
69
64
69
dB
Gain Error
R
L
= 1 k
, G =
1
0.1
0.6
0.1
0.6
%
Peak Nonlinearity, R
L
= 1 k
,
1 V
X
+1 V
0.01
0.03
0.01
0.03
% FS
Gain = 1
1.5 V
X
+1.5 V
0.035
0.07
0.035
0.07
% FS
2 V
X
+2 V
0.15
0.4
0.15
0.4
% FS
Input Bias Current
V
IN
= 0 V, +25
C to T
MAX
5
10
5
10
A
V
IN
= 0 V, T
MIN
7
13
8
17
A
Input Offset Current
V
IN
= 0 V, T
MIN
T
MAX
0.1
1
0.1
1
A
INPUT CHARACTERISTICS
Differential Voltage Range
V
CM
= 0
2.0
2.0
V
Differential Clipping Level
2
Pins 1 and 2 Inputs Only
2.1
2.3
2.1
2.3
V
Common-Mode Voltage Range
V
DM
=
1 V
12.0
+12.8
12.0
+12.8
V
CMRR
DC, Pins 1, 2,
10 V
90
100
90
100
dB
DC, Pins 1, 2,
10 V, T
MIN
T
MAX
88
86
dB
Frequency = 4 MHz
55
60
55
60
dB
Input Resistance
370
370
k
Input Capacitance
2
2
pF
OUTPUT CHARACTERISTICS
Output Voltage Swing
R
L
1 k
12
+13.8, 13.8
12
+13.8, 13.8
V
R
L
1 k
,
16.5 V
S
13
+15.3, 14.7
13
+15.3, 14.7
V
Short Circuit Current
Short to Ground
80
80
mA
Output Current
R
L
= 150
50
50
mA
POWER SUPPLIES
Operating Range
4
16.5
4
16.5
V
Quiescent Current
T
MIN
T
MAX
14.5
17
14.5
17
mA
+ PSRR (to V
P
)
DC, G = 1
86
86
dB
PSRR (to V
N
)
DC, G = 1
68
68
dB
PSRR
DC, G = 1,
5 to
15 V
S
66
71
66
71
dB
PSRR
DC, G = 1,
5 to
15 V
S
,
T
MIN
T
MAX
62
68
60
68
dB
NOTES
1
See Standard Military Drawing 5962-9313001MPA for specifications.
2
Clipping level function on X channel only.
Specifications subject to change without notice.
AD830
REV. A
3
(V
S
= 5 V, R
LOAD
= 150
, C
LOAD
= 5 pF, T
A
= +25 C unless otherwise noted)
AD830J/A
AD830S
1
Parameter
Conditions
Min
Typ
Max
Min
Typ
Max
Units
DYNAMIC CHARACTERISTICS
3 dB Small Signal Bandwidth
Gain = 1, V
OUT
= 100 mV rms
35
40
35
40
MHz
0.1 dB Gain Flatness Frequency
Gain = 1, V
OUT
= 100 mV rms
5
6.5
5
6.5
MHz
Differential Gain Error
0 to +0.7 V, Frequency = 4.5 MHz,
G = +2
0.14
0.18
0.14
0.18
%
Differential Phase Error
0 to +0.7 V, Frequency = 4.5 MHz,
G = +2
0.32
0.4
0.32
0.4
Degrees
Slew Rate, Gain = 1
2 V Step, R
L
= 500
210
210
V/
s
4 V Step, R
L
= 500
240
240
V/
s
3 dB Large Signal Bandwidth
Gain = 1, V
OUT
= 1 V rms
30
36
30
36
MHz
Settling Time
V
OUT
= 2 V Step, to 0.1%
35
35
ns
V
OUT
= 4 V Step, to 0.1%
48
48
ns
Harmonic Distortion
2 V p-p, Frequency = 1 MHz
69
69
dBc
2 V p-p, Frequency = 4 MHz
56
56
dBc
Input Voltage Noise
Frequency = 10 kHz
27
27
nV/
Hz
Input Current Noise
1.4
1.4
pA/
Hz
DC PERFORMANCE
Offset Voltage
Gain = 1
1.5
3
1.5
3
mV
Gain = 1, T
MIN
T
MAX
4
5
mV
Open Loop Gain
DC
60
65
60
65
dB
Unity Gain Accuracy
R
L
= 1 k
0.1
0.6
0.1
0.6
%
Peak Nonlinearity, R
L
= 1 k
1 V
X
+1 V
0.01
0.03
0.01
0.03
% FS
1.5 V
X
+1.5 V
0.045
0.07
0.045
0.07
% FS
2 V
X
+2 V
0.23
0.4
0.23
0.4
% FS
Input Bias Current
V
IN
= 0 V, +25
C to T
MAX
5
10
5
10
A
V
IN
= 0 V, T
MIN
7
13
8
17
A
Input Offset Current
V
IN
= 0 V, T
MIN
T
MAX
0.1
1
0.1
1
A
INPUT CHARACTERISTICS
Differential Voltage Range
V
CM
= 0
2.0
2.0
V
Differential Clipping Level
2
Pins 1 and 2 Inputs Only
2.0
2.2
2.0
2.2
V
Common-Mode Voltage Range
V
DM
=
1 V
2.0
+2.9
2.0
+2.9
V
CMRR
DC, Pins 1, 2, +4 V to 2 V
90
100
90
100
dB
DC, Pins 1, 2, +4 V to 2 V,
T
MIN
T
MAX
88
86
dB
Frequency = 4 MHz
55
60
55
60
dB
Input Resistance
370
370
k
Input Capacitance
2
2
pF
OUTPUT CHARACTERISTICS
Output Voltage Swing
R
L
150
3.2
3.5
3.2
3.5
V
R
L
150
,
4 V
S
2.2
+2.7, 2.4
2.2
+2.7, 2.4
V
Short Circuit Current
Short to Ground
55, +70
55, +70
mA
Output Current
40
40
mA
POWER SUPPLIES
Operating Range
4
16.5
4
16.5
V
Quiescent Current
T
MIN
T
MAX
13.5
16
13.5
16
mA
+ PSRR (to V
P
)
DC, G = 1, Offset
86
86
dB
PSRR (to V
N
)
DC, G = 1, Offset
68
68
dB
PSRR (Dual Supply)
DC, G = 1,
5 to
15 V
S
66
71
66
71
dB
PSRR (Dual Supply)
DC, G = 1,
5 to
15 V
S
,
T
MIN
T
MAX
62
68
60
68
dB
NOTES
1
See Standard Military Drawing 5962-9313001MPA for specifications.
2
Clipping level function on X channel only.
Specifications subject to change without notice.
AD830
REV. A
4
ABSOLUTE MAXIMUM RATINGS
1
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18 V
Internal Power Dissipation
2
. . . . . . . Observe Derating Curves
Output Short Circuit Duration . . . . Observe Derating Curves
Common-Mode Input Voltage . . . . . . . . . . . . . . . . . . . . . .
V
S
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . .
V
S
Storage Temperature Range (Q) . . . . . . . . . 65
C to +150
C
Storage Temperature Range (N) . . . . . . . . . 65
C to +125
C
Storage Temperature Range (R) . . . . . . . . . 65
C to +125
C
Operating Temperature Range
AD830J . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0
C to +70
C
AD830A . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
C to +85
C
AD830S . . . . . . . . . . . . . . . . . . . . . . . . . . 55
C to +125
C
Lead Temperature Range (Soldering 60 seconds) . . . +300
C
NOTES
1
Stresses above those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2
8-Pin Plastic Package:
JA
= 90
C/Watt
8-Pin SOIC Package:
JA
= 155
C/Watt
8-Pin Cerdip Package:
JA
= 110
C/Watt
MAXIMUM POWER DISSIPATION
The maximum power that can be safely dissipated by the
AD830 is limited by the associated rise in junction temperature.
For the plastic packages, the maximum safe junction tempera-
ture is 145
C. For the cerdip, the maximum junction tempera-
ture is 175
C. If these maximums are exceeded momentarily,
proper circuit operation will be restored as soon as the die tem-
perature is reduced. Leaving the AD830 in the "overheated"
condition for an extended period can result in permanent dam-
age to the device. To ensure proper operation, it is important to
observe the recommended derating curves.
While the AD830 output is internally short circuit protected,
this may not be sufficient to guarantee that the maximum junc-
tion temperature is not exceeded under all conditions. If the
output is shorted to a supply rail for an extended period, then
the amplifier may be permanently destroyed.
ESD SUSCEPTIBILITY
ESD (electrostatic discharge) sensitive device. Electrostatic
charges as high as 4000 volts, which readily accumulate on the
human body and on test equipment, can discharge without de-
tection. Although the AD830 features proprietary ESD protec-
tion circuitry, permanent damage may still occur on these
devices if they are subjected to high energy electrostatic dis-
charges. Therefore, proper ESD precautions are recommended
to avoid any performance degradation or loss of functionality.
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
AD830AN
40
C to +85
C
8-Pin Plastic Mini-DIP
N-8
AD830JR
0
C to +70
C
8-Pin SOIC
R-8
5962-9313001MPA*
55
C to +125
C
8-Pin Cerdip
Q-8
*See Standard Military Drawing for specifications.
2.5
0
90
1.5
0.5
30
1.0
50
2.0
70
50
30
10
10
AMBIENT TEMPERATURE
C
TOTAL POWER DISSIPATION Watts
T
J
MAX = 145
C
8-PIN MINI-DIP
8-PIN SOIC
Maximum Power Dissipation vs. Temperature,
Mini-DlP and SOIC Packages
3.0
0.2
140
0.8
0.4
40
0.6
60
1.4
1.0
1.2
1.6
2.0
2.2
2.8
2.4
1.8
100
120
80
60
40
20
0
20
AMBIENT TEMPERATURE
C
TOTAL POWER DISSIPATION Watts
T
J
MAX = 175
C
8-PIN CERDIP
Maximum Power Dissipation vs. Temperature,
Cerdip Package
AD830
REV. A
5
FREQUENCY Hz
CMRR dB
110
30
10M
50
40
1k
70
60
80
90
100
1M
100k
10k
V
S
=
15V
V
S
=
5V
Figure 1. Common-Mode Rejection Ratio vs. Frequency
FREQUENCY Hz
50
70
90
10k
10M
1M
100k
1k
80
60
HARMONIC DISTORTION dBc
V
OUT
= 2V p-p
R
L
= 150
GAIN = +1
5V SUPPLIES
2ND HARMONIC
3RD HARMONIC
15V SUPPLIES
2ND HARMONIC
3RD HARMONIC
Figure 2. Harmonic Distortion vs. Frequency
JUNCTION TEMPERATURE
C
INPUT CURRENT
A
9
3
140
6
4
40
5
60
8
7
120
80
60
40
100
20
0
20
Figure 3. Input Bias Current vs. Temperature
Typical Characteristics
FREQUENCY Hz
PSRR dB
100
10
10M
30
20
1k
40
50
60
70
80
90
1M
100k
10k
TO V
P
@
15V
TO V
P
@
5V
TO V
N
@
15V
TO V
N
@
5V
Figure 4. Power Supply Rejection Ratio vs. Frequency
FREQUENCY Hz
3
12
27
100k
100M
10M
1M
10k
9
6
3
0
24
21
18
15
GAIN dB
15V
5V
1G
10V
R
L
= 150
C
L
= 4.7pF
Figure 5. Closed-Loop Gain vs. Frequency G = +1
JUNCTION TEMPERATURE
C
INPUT OFFSET VOLTAGE mV
3
4
140
1
3
40
2
60
2
0
1
120
100
80
60
40
20
0
20
5V
S
15V
S
10V
S
Figure 6. Input Offset Voltage vs. Temperature
AD830
REV. A
6
0.10
0.03
0.01
0.02
0.06
0.04
0.05
0.07
0.08
0.09
15
6
5
0.10
0.03
0.01
0.02
0.06
0.04
0.05
0.07
0.08
0.09
14
13
12
11
10
9
8
7
SUPPLY VOLTAGE
Volts
DIFFERENTIAL GAIN %
DIFFERENTIAL PHASE D
egrees
PHASE
GAIN
GAIN = +2
R
L
= 500
FREQ = 4.5MHz
Figure 7. Differential Gain and Phase vs. Supply Voltage,
R
L
= 500
40
100
2.00
70
90
0.50
80
0.25
50
60
1.75
1.25
1.00
0.75
1.50
PEAK AMPLITUDE Volts
HARMONIC DISTORTION dB
HD3 (
15V)
100kHz
HD2 (
5V)
100kHz
HD2 (
15V)
100kHz
HD3 (
5V)
100kHz
Figure 8. Harmonic Distortion vs. Peak Amplitude,
Frequency = 100 kHz
50
10
100
10M
40
20
1k
30
100k
1M
10k
FREQUENCY Hz
INPUT VOLTAGE NOISE nV/
Hz
Figure 9. Noise Spectral Density
0.20
15
0.06
0.02
6
0.04
5
0.12
0.08
0.10
0.14
0.16
0.18
14
13
12
11
10
9
8
7
SUPPLY VOLTAGE
Volts
DIFFERENTIAL GAIN %
DIFFERENTIAL PHASE D
egrees
GAIN
PHASE
0.40
0.12
0.04
0.08
0.24
0.16
0.20
0.28
0.32
0.36
GAIN = +2
R
L
= 150
FREQ = 4.5MHz
Figure 10. Differential Gain and Phase vs. Supply Voltage,
R
L
= 150
40
100
2.00
70
90
0.50
80
0.25
50
60
1.75
1.25
1.00
0.75
1.50
PEAK AMPLITUDE Volts
HARMONIC DISTORTION dB
HD2 (
15V)
4MHz
HD3 (
15V)
4MHz
HD2 (
5V)
4MHz
HD3 (
5V)
4MHz
Figure 11. Harmonic Distortion vs. Peak Amplitude,
Frequency = 4 MHz
JUNCTION TEMPERATURE
C
QUIESCENT SUPPLY CURRENT mA
15.00
12.25
140
13.00
12.50
40
12.75
60
13.75
13.25
13.50
14.00
14.25
14.50
14.75
120
100
80
60
40
20
0
20
16.5V
S
5V
S
Figure 12. Supply Current vs. Junction Temperature
AD830
REV. A
7
Typical Characteristics
3
12
27
1M
1G
100M
10M
100k
9
6
3
0
24
21
18
15
FREQUENCY Hz
UNITY GAIN CONNECTION
GAIN OF 2 CONNECTION
9
6
21
3
0
3
6
18
15
12
9
15V
5V
R
L
= 150
C
L
= 0pF
Figure 13. Closed-Loop Gain vs. Frequency for the
Three Common Connections of Figure 16
10
90
100
0%
100mV
20
ns
V
S
=
15V
V
S
=
5V
Figure 14. Small Signal Pulse Response,
R
L
= 150
, C
L
= 4.7 pF, G = +1
9
6
21
100k
1G
10M
1M
10k
3
0
3
6
18
15
12
9
FREQUENCY Hz
GAIN dB
100M
V
S
=
5V
R
L
= 150
C
L
= 4.7pF
C
L
= 15pF
C
L
= 33pF
Figure 15. Closed-Loop Gain vs. Frequency vs.
C
L
, G = +1. V
S
=
5 V
V
1
V
P
OUT
V
N
V
OUT
= 2V
1
RESISTOR LESS GAIN OF 2
1
2
4
3
8
7
5
6
AD830
C
A=1
G
M
G
M
V
OUT
= V
1
GAIN OF 1
V
1
V
P
OUT
V
N
1
2
4
3
8
7
5
6
AD830
C
A=1
G
M
G
M
V
OUT
= V
1
OP-AMP CONNECTION
V
1
V
P
OUT
V
N
1
2
4
3
8
7
5
6
AD830
C
A=1
G
M
G
M
(a)
(b)
(c)
Figure 16. Connection Diagrams
10
90
100
0%
1V
20
ns
V
S
=
15V
V
S
=
5V
Figure 17. Large Signal Pulse Response,
R
L
= 150
, C
L
= 4.7 pF, G = +1
9
6
21
100k
100M
10M
1M
10k
3
0
3
6
18
15
12
9
FREQUENCY Hz
GAIN dB
V
S
= +15V
R
L
= 150
C
L
= 4.7pF
C
L
= 15pF
C
L
= 33pF
1G
Figure 18. Closed-Loop Gain vs. Frequency, vs.
C
L
, G = +1. V
S
=
15 V
AD830
REV. A
8
TRADITIONAL DIFFERENTIAL AMPLIFICATION
In the past, when differential amplification was needed to reject
common-mode signals superimposed with a desired signal; most
often the solution used was the classic op amp based difference
amplifier shown in Figure 19. The basic function V
O
= V
1
V
2
is
simply achieved, but the overall performance is poor and the cir-
cuit possesses many serious problems that make it difficult to re-
alize a robust design with moderate to high levels of
performance.
R
1
R
2
R
3
R
4
V
OUT
V
2
V
1
ONLY IF R
1
= R
2
= R
3
= R
4
DOES
V
OUT
= V
1
V
2
Figure 19. Op Amp Based Difference Amplifier
PROBLEMS WITH THE OP AMP BASED APPROACH
Low Common-Mode Rejection Ratio (CMRR)
Low Impedance Inputs
CMRR Highly Sensitive to the Value of Source R
Different Input Impedance for the + and Input
Poor High Frequency CMRR
Requires Very Highly Matched Resistors R
1
R
4
to Achieve
High CMRR
Halves the Bandwidth of the Op Amp
High Power Dissipation in the Resistors for Large Common-
Mode Voltage
AD830 FOR DIFFERENTIAL AMPLIFICATION
The AD830 amplifier was specifically developed to solve the
listed problems with the discrete difference amplifier approach.
Its topology, discussed in detail in a later section, by design acts
as a difference amplifier. The circuit of Figure 20 shows how
simply the AD830 is configured to produce the difference of two
signals V
1
and V
2
, in which the applied differential signal is
exactly reproduced at the output relative to a separate output
common. Any common-mode voltage present at the input is
removed by the AD830.
A=1
V
I
V
I
V
OUT
V
2
V
1
V
OUT
= V
1
V
2
I
Y
I
X
Figure 20. AD830 as a Difference Amplifier
ADVANTAGEOUS PROPERTIES OF THE AD830
High Common-Mode Rejection Ratio (CMRR)
High Impedance Inputs
Symmetrical Dynamic Response for +1 and 1 Gain
Low Sensitivity to the Value of Source R
Equal Input Impedance for the + and Input
Excellent High Frequency CMRR
No Halving of the Bandwidth
Constant Power Distortion vs. Common-Mode Voltage
Highly Matched Resistors Not Needed
AD830
REV. A
9
UNDERSTANDING THE AD830 TOPOLOGY
The AD830 represents Analog Devices' first amplifier product
to embody a powerful alternative amplifier topology. Referred to
as active feedback, the topology used in the AD830 provides in-
herent advantages in the handling of differential signals, differ-
ing system commons, level shifting and low distortion, high
frequency amplification. In addition, it makes possible the
implementation of many functions not realizable with single op
amp circuits or is superior to op amp based equivalent circuits.
With this in mind, it is important to understand the internal
structure of the AD830.
The topology, reduced to its elemental form, is shown below in
Figure 21. Nonideal effects such as nonlinearity, bias currents
and limited full scale are omitted from this model for simplicity,
but are discussed later. The key feature of this topology is the
use of two, identical voltage-to-current converters, G
M
, that
make up input and feedback signal interfaces. They are labeled
with inputs V
X
and V
Y
, respectively. These voltage to current
converters possess fully differential inputs, high linearity, high
input impedance and wide voltage range operation. This enables
the part to handle large amplitude differential signals; they also
provide high common-mode rejection, low distortion and negli-
gible loading on the source. The label, G
M
, is meant to convey
that the transconductance is a large signal quantity, unlike in the
front-end of most op amps. The two G
M
stage current outputs
I
X
and I
Y
, sum together at a high impedance node which is char-
acterized by an equivalent resistance and capacitance connected
to an "ac common." A unity voltage gain stage follows the high
impedance node to provide buffering from loads. Relative to
either input, the open loop gain, A
OL
, is set by the
transconductance, G
M
, working into the resistance, R
P
; A
OL
=
G
M
R
P
. The unity gain frequency
0
dB
for the open loop gain
is established by the transconductance, G
M
, working into the
capacitance, C
C
;
0
dB
= G
M
/C
C
. The open loop description of
the AD830 is shown below for completeness.
A=1
V
OUT
V
X2
V
X1
I
X
= (V
X1
V
X2
) G
M
I
Y
= (V
Y1
V
Y2
) G
M
I
Z
= I
X
+ I
Y
I
Y
I
X
V
Y2
V
Y1
G
M
G
M
I
Z
A
OLS
=
G
M
R
P
1 + S (C
C
R
P
)
C
C
R
P
Figure 21. Topology Diagram
A=1
V
OUT
V
X2
V
X1
V
X1
V
X2
= V
Y
2
V
Y1
FOR V
Y2
= V
OUT
V
OUT
= (V
X1
V
X2
+ V
Y1
)
I
Y
I
X
V
Y2
V
Y1
G
M
G
M
1
1 + S(C
C
/G
M
)
C
C
Figure 22. Closed-Loop Connection
Precise amplification is accomplished through closed-loop op-
eration of this topology. Voltage feedback is implemented via
the Y G
M
stage in which where the output is connected to the
Y input for negative feedback as shown in Figure 22. An input
signal is applied across the X G
M
stage, either fully differentially
or single-ended referred to common. It produces a current sig-
nal which is summed at the high impedance node with the out-
put current from the Y G
M
stage. Negative feedback nulls this
sum to a small error current necessary to develop the output
voltage at the high impedance node. The error current is usually
negligible, so the null condition essentially forces the Y G
M
output stage current to exactly equal the X G
M
output current.
Since the two transconductances are identical, the differential
voltage across the Y inputs equals the negative of the differential
voltage across the X input; V
Y
= V
X
or more precisely
V
Y2
V
Y1
= V
X1
V
X2
. This simple relation provides the basis to
easily analyze any function possible to synthesize with the
AD830, including any feedback situation.
The bandwidth of the circuit is defined by the G
M
and the
capacitor C
C
. The highly linear G
M
stages give the amplifier a
single pole response, excluding the output amplifier and loading
effects. It is important to note that the bandwidth and general dy-
namic behavior is symmetrical (identical) for the noninverting
and
the inverting connections of the AD830.
In addition, the input im-
pedance and CMRR are the same for either connections. This is
very advantageous and unlike in a voltage or current feedback
amplifier, where there is a distinct difference in performance be-
tween the inverting and noninverting gain. The practical impor-
tance of this cannot be overemphasized and is a key feature
offered by the AD830 amplifier topology.
AD830
REV. A
10
INTERFACING THE INPUT
Common-Mode Voltage Range
The common-mode range of the AD830 is defined by the am-
plitude of the differential input signal and the supply voltage.
The general definition of common-mode voltage, V
CM
, is usu-
ally applied to a symmetrical differential signal centered about a
particular voltage as illustrated by the diagram in Figure 23.
This is the meaning implied here for common-mode voltage.
The internal circuitry establishes the maximum allowable volt-
age on the input or feedback pins for a given supply voltage.
This constraint and the differential input voltage sets the
common-mode voltage limit. Figure 24 shows a curve of the
common-mode voltage range vs. differential voltage for three
supply voltage settings.
V
MAX
V
PEAK
V
CM
Figure 23. Common-Mode Definition
15
0
2.0
3
0
6
9
12
1.6
1.2
0.8
0.4
+V
CM
15V = V
S
10V = V
S
5V = V
S
+V
CM
+V
CM
V
CM
V
CM
V
CM
DIFFERENTIAL INPUT VOLTAGE V
PEAK
COMMON-MODE VOLTAGE
Volts
Figure 24. Input Common-Mode Voltage Range vs.
Differential Input Voltage
Differential Voltage Range
The maximum applied differential voltage is limited by the clip-
ping range of the input stages. This is nominally set at 2.4 volts
magnitude and depicted in the crossplot (X-Y) photo of Figure
25. The useful linear range of the input stages is set at 2 volts,
but is actually a function of the distortion required for a particu-
lar application. The distortion increases for larger differential
input voltages. A plot of relative distortion versus input differen-
tial voltage is shown in Figures 8 and 11 in the Typical Charac-
teristics section. The distortion characteristics could impose a
secondary limit to the differential input voltage for high accu-
racy applications.
10
90
100
0%
1V
1V
Figure 25. Clipping Behavior
15
0
20
3
0
6
9
12
16
12
8
4
SUPPLY VOLTAGE Volts
MAXIMUM OUTPUT SWING
Volts
V
P
V
N
Figure 26. Maximum Output Swing vs. Supply
AD830
REV. A
11
Choice of Polarity
The sign of the gain is easily selected by choosing the polarity of
the connections to the + and inputs of the X G
M
stage. Swap-
ping between inverting and noninverting gain is possible simply
by reversing the input connections. The response of the ampli-
fier is identical in either connection, except for the sign change.
The bandwidth, high impedance, transient behavior, etc., of the
AD830, is symmetrical for both polarities of gain. This is very
advantageous and unlike an op amp.
Input Impedance
The relatively high input impedance of the AD830, for a differ-
ential receiver amplifier, permits connections to modest imped-
ance sources without much loading or loss of common-mode
rejection. The nominal input resistance is 300 k
. The real limit
to the upper value of the source resistance is in its effect on
common-mode rejection and bandwidth. If the source resistance
is in only one input, then the low frequency common-mode re-
jection will be lowered to
R
IN
/R
S
. The source resistance/input
capacitance pole
f
=
1
2
R
S
C
IN


limits the bandwidth.
Furthermore, the high frequency common-mode rejection will
be additionally lowered by the difference in the frequency re-
sponse caused by the R
S
C
IN
pole. Therefore, to maintain
good low and high frequency common-mode rejection, it is rec-
ommended that the source resistances of the + and inputs be
matched and of modest value (
10 k
).
Handling Bias Currents
The bias currents are typically 4
A flowing into each pin of the
G
M
stages of the AD830. Since all applications possess some fi-
nite source resistance, the bias current through this resistor will
create a voltage drop (I
BIAS
R
S
). The relatively high input im-
pedance of the AD830 permits modest values of R
S
, typically
10 k
. If the source resistance is in only one terminal, then an
objectional offset voltage may result (e.g., 4
A 5 k
=
20 mV). Placement of an equal value resistor in series with the
other input will cancel the offset to first order. However, due to
mismatches in the resistances, a residual offset will remain and
likely be greater than bias current (offset current) mismatches.
Applying Feedback
The AD830 is intended for use with gain from 1 to 100. Gains
greater than one are simply set by a pair of resistors connected
as shown in the difference amplifier (Figure 35) with gain >1.
The value of the bottom resistor R
2
, should be kept less than
1 k
to insure that the pole formed by C
IN
and the parallel con-
nection of R
1
and R
2
is sufficiently high in frequency so that it
does not introduce excessive phase shift around the loop and de-
stabilizes the amplifier. A compensating resistor, equal to the
parallel combination of R
1
and R
2
, should be placed in series
with the other Y G
M
stage input to preserve the high frequency
common-mode rejection and to lower the offset voltage induced
by the input bias current.
Output Common Mode
The output swing of the AD830 is defined by the differential in-
put voltage, the gain and the output common. Depending on
the anticipated signal span, the output common (or ground)
may be set anywhere between the allowable peak output voltage
in a manner similar to that described for input voltage common
mode. A plot of the peak output voltage versus supply is shown
in Figure 26. A prediction of the common-mode range versus
the peak output differential voltage can be easily derived from
the maximum output swing as V
OCM
= V
MAX
V
PEAK
.
Output Current
The absolute peak output current is set by the short circuit cur-
rent limiting, typically greater that 60 mA. The maximum drive
capability is rated at 50 mA, but without a guarantee of distor-
tion performance. Best distortion performance is obtained by
keeping the output current
20 mA. Attempting to drive large
voltages into low valued resistances (e.g., 10 V into 150
) will
cause an apparent lowering of the limit for output signal swing,
but is just the current limiting behavior.
Driving Cap Loads
The AD830 is capable of driving modest sized capacitive loads
while maintaining its rated performance. Several curves of band-
width versus capacitive load are given in Figures 15 and 18. The
AD830 was designed primarily as a low distortion video speed
amplifier, but with a tradeoff, giving up very large capacitive
load driving capability. If very large capacitive loads must be
driven, then the network shown in Figure 27 should be used to
insure stable operation. If the loss of gain caused by the resistor
R
S
in series with the load is objectionable, then the optional
feedback network shown may be added to restore the lost gain.
5
8
4
1
2
3
7
6
A=1
AD830
G
M
C
G
M
+
INPUT
SIGNAL
+V
S
0.1
F
R
S
36.5
V
OUT
R
S
C
1
100pF
R
1
1k
R
1
0.1
F
V
S
* OPTIONAL
FEEDBACK
NETWORK
Z
CM
V
CM
Figure 27. Circuit for Driving Large Capacitive Loads
3
12
27
100k
100M
10M
1M
10k
9
6
3
0
24
21
18
15
CLOSED-LOOP AMPLITUDE RESPONSE dB
FREQUENCY Hz
15V
5V
Figure 28. Closed-Loop Response vs. Frequency with
100 pF Load and Series Resistor Compensation
AD830
REV. A
12
SUPPLIES, BYPASSING AND GROUNDING (FIGURE 29)
The AD830 is capable of operating over a wide range of supply
voltages, both single and dual supplies. The coupling may be dc
or ac provided the input and output voltages stay within the
specified common-mode voltage limits. For dual supplies, the
device works from
4 V to
16.5 V. Single supply operation is
possible over +8 V to +33 V. It is also possible to operate the
part with split supply voltages (e.g., +24 V, 5 V) for special
applications such as level shifting. The primary constraint is that
the total potential between the two supplies does not exceed
33 V.
Inclusion of power supply bypassing capacitors is necessary to
achieve stable behavior and the specified performance. It is es-
pecially important when driving low resistance loads. At a mini-
mum, connect a 0.1
F ceramic capacitor at the supply lead of
the AD830 package. In addition, for the best by passing, we rec-
ommend connecting a 0.01
F ceramic capacitor and 4.7
F
tantalum capacitor to the supply lead going to the AD830.
0.1
F
LOAD
GND
LEAD
V
P
AND
V
N
0.01
F
4.7
F
V
P
AND
V
N
LOAD
GND
LEAD
(a) (b)
Figure 29. Supply Decoupling Options
The AD830 is designed by its functionality to be capable of
rejecting noise and dissimilar potentials in the ground lines.
Therefore, proper care is necessary to realize the benefits of the
differential amplification of the part. Separation of the input and
output grounds is crucial in rejection of the common mode
noise at the inputs and eliminating any ground drops on the in-
put signal line. For example, connecting the ground of a coaxial
cable to the AD830 output common (board ground) could de-
grade the CMR and also introduce power-down loading on
cable grounds. However, it is also necessary as in any electronic
system, to provide a return path for bias currents back to their
original power supply. This is accomplished by providing a con-
nection between the differing grounds through a modest imped-
ance labeled Z
CM
(e.g., 100
).
Single Supply Operation
The AD830 is capable of operating in single power supply appli-
cations down to a voltage of +8 V, with the generalized connec-
tion shown in Figure 30. There is a constraint on the
common-mode voltage at the input and output which estab-
lishes the range for these voltages. Direct coupling may be used
for input and output voltages which lie in these ranges. Any gain
network applied needs to be referred to the output common
connection or have an appropriate offset voltage. In situations
where the signal lies at a common voltage outside the common
mode range of the AD830 direct coupling will not work, so ac
coupling should be used. A tested application included later in
this data sheet (Figure 42), shows how to easily accomplish cou-
pling to the AD830. For single supply operation where direct
coupling is desired the input and output common-mode curves
(Figures 31 and 32) should be used.
5
8
4
1
2
3
7
6
A=1
AD830
G
M
C
+
V
P
+
+
V
OUT
V
OCM
V
ICM
V
IN
V
OUT
= (V
IN
V
ICM
) + V
OCM
G
M
Figure 30. General Single Supply Connection
30
0
2.0
4
0
12
16
24
1.6
1.2
0.8
0.4
DIFFERENTIAL INPUT VOLTAGE V
PEAK
COMMON MODE VOLTAGE LIMITS
Volts
8
28
20
V
P
= +30V
V
P
= +15V
V
P
= +10V
TO GND
Figure 31. Input Common-Mode Range for Single Supply
0
30
4
10
12
16
24
26
22
18
14
SUPPLY VOLTAGE Volts
MAXIMUM OUTPUT SWING
Volts
8
28
20
TO V
P
TO GND
Figure 32. Output Swing Limit for Single Supply
AD830
REV. A
13
Differential Line Receiver
The AD830 was specifically designed to perform as a differen-
tial line receiver. The circuit in Figure 33 shows how simple it is
to configure the AD830 for this function. The signal from sys-
tem "A" is received differentially relative to A's common, and
that voltage is exactly reproduced relative to the common in sys-
tem B. The common-mode rejection versus frequency, shown in
Figure 1, is excellent, typically 100 dB at low frequencies. The
high input impedance permits the AD830 to operate as a bridg-
ing amplifier across low impedance terminations with negligible
loading. The differential gain and phase specifications are very
good as shown in Figure 7 for 500
and Figure 10 for 150
.
The input and output common should be separated to achieve
the full CMR performance of the AD830 as a differential ampli-
fier. However, a common return path is necessary between sys-
tems A and B.
4
5
3
6
AD830
1
2
8
7
A=1
COMMON IN
SYSTEM B
V
OUT
= V
1
V
2
COMMON IN
SYSTEM A
V
1
V
2
INPUT
SIGNAL
V
CM
Z
CM
V
P
0.1F
V
OUT
V
N
0.1F
G
M
G
M
C
Figure 33. Differential Line Receiver
Wide Range Level Shifter
The wide common-mode range and accuracy of the AD830 al-
lows easy level shifting of differential signals referred to an input
common-mode voltage to any new voltage defined at the out-
put. The inputs may be referenced to levels as high as 10 V at
the inputs with a
2 V swing about 10 V. In the circuit of Fig-
ure 34, the output voltage, V
OUT
, is defined by the simple equa-
tion shown below. The excellent linearity and low distortion are
preserved over the full input and output common-mode range.
The voltage sources need not be of low impedance, since the
high input resistance and modest input bias current of the
AD830 V-to-I converters permit the use of resistive voltage di-
viders as reference voltages.
4
5
3
6
AD830
1
2
8
7
A=1
OUTPUT
COMMON
V
OUT
= V
1
V
2
+ V
3
V
P
0.1F
V
OUT
V
N
0.1F
G
M
G
M
INPUT
COMMON
V
3
C
V
1
V
2
INPUT
SIGNAL
Figure 34. Differential Amplification with Level Shifting
Difference Amplifier with Gain > 1
The AD830 can provide instrumentation amplifier style differ-
ential amplification at gains greater than 1. The input signal is
connected differentially and the gain is set via feedback resistors
as shown in Figure 35. The gain, G = (R
2
+ R
1
)/R
2
. The AD830
can provide either inverting or noninverting differential amplifi-
cation. The polarity of the gain is established by the polarity of
the connection at the input. Feedback resistors R
2
should gener-
ally be R
2
1 k
to maintain closed-loop stability and also keep
bias current induced offsets low. Highest CMRR and lowest dc
offsets are preserved by including a compensating resistor in
series with Pin 3. The gain may be as high as 100.
4
5
3
6
AD830
1
2
8
7
A=1
V
OUT
= (V
1
V
2
) (1+R
1
/R
2
)
V
P
0.1F
V
OUT
V
N
0.1F
G
M
G
M
R1
R2
Z
CM
R
1
R
2
V
1
V
2
INPUT
SIGNAL
C
V
CM
Figure 35. Gain of G Differential Amplifier, G > 1
Offsetting the Output with Gain
Some applications, such as A/D drivers, require that the signal
be amplified and also offset, typically to accommodate the input
range of the device. The AD830 can offset the output signal
very simply through Pin 3 even with gain > 1. The voltage ap-
plied to Pin 3 must be attenuated by an appropriate factor so
that V
3
G = desired offset. In Figure 36, a resistive divider
from a voltage reference is used to produce the attenuated offset
voltage.
4
5
3
6
AD830
1
2
8
7
A=1
V
OUT
= (V
1
V
2
) (1+R
1
/R
2
)
V
1
V
2
INPUT
SIGNAL
V
P
0.1F
V
OUT
V
N
0.1F
G
M
G
M
R
3
R
4
Z
CM
R
2
R
1
R
1
R
2
V
3
V
REF
C
V
CM
Figure 36. Offsetting the Output with Differential Gain > 1
AD830
REV. A
14
Loop Through or Line Bridging Amplifier (Figure 37)
The AD830 is ideally suited for use as a video line bridging am-
plifier. The video signal is tapped from the conductor of the
cable relative to its shield. The high input impedance of the
AD830 provides negligible loading on the cable. More signifi-
cantly, the benign loading is maintained while the AD830 is
powered-down. Coupled with its good video load driving per-
formance, the AD830 is well suited to video cable monitoring
applications.
4
5
3
6
AD830
1
2
8
7
A=1
V
P
0.1F
V
OUT
V
N
0.1F
G
M
G
M
R
G
75
75
499
499
OPTIONAL C
C
249
C
Figure 37. Cable Tap Amplifier
Resistorless Summing
Direct, two input, resistorless summing is easily realized from
the general unity gain mode. By grounding V
X2
and applying the
two inputs to V
X1
and V
Y1
, the output is the exact sum of the
applied voltages V
1
and V
3
, relative to common; V
OUT
= V
1
+
V
3
. A diagram of this simple, but potent application is shown
below in Figure 38. The AD830 summing circuit possesses sev-
eral virtues not present in the classic op amp based summing
circuits. It has high impedance inputs, no resistors, very precise
summing, high reverse isolation and noninverting gain. Achiev-
ing this function and performance with op amps requires signifi-
cantly more components.
4
5
3
6
AD830
1
2
8
7
A=1
V
OUT
= V
1
+ V
3
V
P
OUT
V
N
G
M
G
M
V
1
V
3
C
Figure 38. Resistorless Summing Amplifier
2 Gain Bandwidth Line Driver
A gain of two, without the use of resistors, is possible with the
AD830. This is accomplished by grounding V
X2
, tying the two
inputs V
X1
and V
Y1
together and applying the input, V
IN
, to this
wired connection. The output is exactly twice the applied volt-
age, V
IN
; V
OUT
= 2 V
IN
. Figure 39 below shows the connec-
tions for this highly useful application. The most notable
characteristic of this alternative gain of two is that there is no
loss of bandwidth as in a voltage feedback op amp based gain of
+2 where the bandwidth is halved, therefore, the gain band-
width is doubled. Also, this circuit is accurate without the need
for any precise valued resistors, as in the op amp equivalents,
and it possess excellent differential gain and phase performance
as shown in Figures 40 and 41.
4
5
3
6
AD830
1
2
8
7
A=1
V
P
0.1F
V
OUT
V
N
0.1F
G
M
G
M
75
75
V
IN
C
Figure 39. Full Bandwidth Line Driver (G = +2)
SUPPLY VOLTAGE
Volts
.10
15
.03
.01
6
.02
5
.06
.04
.05
.07
.08
.09
14
13
12
11
10
9
8
7
DIFFERENTIAL GAIN %
DIFFERENTIAL PHASE Degrees
.20
.06
.02
.04
.12
.08
.10
.14
.16
.18
PHASE
GAIN
GAIN = +2
R
L
= 150
FREQ = 3.58MHz
0 TO 0.7V
Figure 40. Differential Gain and Phase for the Circuit of
Figure 39
0.2
0.3
0.8
100k
100M
10M
1M
10k
0.2
0.1
0
0.1
0.7
0.6
0.5
0.4
FREQUENCY Hz
AMPLITUDE RESPONSE dB
V
S
=
15V
V
S
=
10V
V
S
=
5V
R
L
= 150
GAIN = +2
Figure 41. 0.1 dB Gain Flatness for the Circuit of Figure 39
AD830
REV. A
15
AC COUPLED LINE RECEIVER
The AD830 is configurable as an ac coupled differential ampli-
fier on a single or bipolar supply voltages. All that is needed is
inclusion of a few noncritical passive components as illustrated
below in Figure 42. A simple resistive network at the X G
M
input establishes a common-mode bias. Here, the common
mode is centered at 6 volts, but in principle can be any voltage
within the common-mode limits of the AD830. The 10 k
re-
sistors to each input bias the X G
M
stage with sufficiently high
impedance to keep the input coupling corner frequency low, but
not too large so that residual bias current induced offset voltage
becomes troublesome. For dual supply operation, the 10 k
resistors may go directly to ground. The output common is con-
veniently set by a Zener diode for a low impedance reference to
preserve the high frequency CMR. However, a simple resistive
divider will work fine and good high frequency CMR can be
maintained by placing a compensating resistor in series with the
+Y input. The excellent CMRR response of the circuit is shown
in Figure 43. A plot of the 0.1 dB flatness from 10 Hz is also
shown. With the use of 10
F capacitors, the CMR is >90 dB
down to a few tens of hertz. This level of performance is almost
impossible to achieve with discrete solutions.
4
5
3
6
AD830
1
2
8
7
A=1
Z
CM
+12V
0.1F
V
OUT
G
M
G
M
75
75
1000F
75
COAX
CABLE
+12V
4.7k
6.8V
1N4736
+V
S
10k
10k
10F
10F
R
T
10k
10k
2k
*
*OPTIONAL TUNING FOR
IMPROVING VERY LOW
FREQUENCY CMR.
C
INPUT
SIGNAL
Figure 42. AC Coupled Line Receiver
120
100
20
10
100
100M
10M
1M
100k
10k
1k
80
60
40
FREQUENCY Hz
COMMON-MODE REJECTION dB
WITH CIRCUIT TRIMMED
USING EXTERNAL 2k
POTENTIOMETER
WITHOUT EXTERNAL
2k
POTENTIOMETER
Figure 43. Common-Mode Rejection vs. Frequency for
Line Receiver
1
0.4
0.9
10
100
10M
1M
100k
10k
1k
0.3
0.2
0.1
0
0.8
0.7
0.6
0.5
AMPLITUDE
RESPONSE
d
B
FREQUENCY Hz
Figure 44. Amplitude Response vs. Frequency for Line
Receiver
AD830
REV. A
16
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
Cerdip (Q) Package
0.320 (8.13)
0.290 (7.37)
0.015 (0.38)
0.008 (0.20)
15
0
0.005 (0.13) MIN
0.055 (1.4) MAX
1
PIN 1
4
5
8
0.310 (7.87)
0.220 (5.59)
0.405 (10.29) MAX
0.200
(5.08)
MAX
SEATING
PLANE
0.023 (0.58)
0.014 (0.36)
0.070 (1.78)
0.030 (0.76)
0.060 (1.52)
0.015 (0.38)
0.150
(3.81)
MIN
0.200 (5.08)
0.125 (3.18)
0.100
(2.54)
BSC
Plastic Mini-DIP (N) Package
PIN 1
0.280 (7.11)
0.240 (6.10)
4
5
8
1
SEATING
PLANE
0.060 (1.52)
0.015 (0.38)
0.130
(3.30)
MIN
0.210
(5.33)
MAX
0.160 (4.06)
0.115 (2.93)
0.430 (10.92)
0.348 (8.84)
0.022 (0.558)
0.014 (0.356)
0.070 (1.77)
0.045 (1.15)
0.100
(2.54)
BSC
0.325 (8.25)
0.300 (7.62)
0.015 (0.381)
0.008 (0.204)
0.195 (4.95)
0.115 (2.93)
8-Pin SOIC (R) Package
1
4
5
8
0.050
(1.27)
TYP
0.188 (4.75)
0.198 (5.00)
0.150 (3.80)
0.158 (4.00)
0.228 (5.80)
0.244 (6.200)
0.014 (0.36)
0.018 (0.46)
0.181 (4.60)
0.205 (5.20)
0.102 (2.59)
0.094 (2.39)
0.020 (0.50)
0.045 (1.15)
0.007 (0.18)
0.015 (0.38)
0.004 (0.10)
0.010 (0.25)
C17352410/92
PRINTED IN U.S.A.
All brand or product names mentioned are trademarks or registered trademarks of their respective holders.