REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
a
AD10226
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
Analog Devices, Inc., 2002
Dual-Channel, 12-Bit 125 MSPS
IF Sampling A/D Converter
FUNCTIONAL BLOCK DIAGRAM
D0B
(LSB)
D1B
D2B
D3B
D4B
D5B
D6B
D7B
D8B
D9B
D10B
D11B
(MSB)
D0A
(LSB)
D1A
D2A
D3A
D4A
D5A
D6A
D7A
D8A
D9A
D10A
D11A
(MSB)
ADC
50
A
IN
A2
T1A
ADC
50
A
IN
B2
T1B
AD10226
12
TIMING
ENCODEA
ENCODEA
REF
REF_A_OUT
TIMING
ENCODEB
ENCODEB
REF
REF_B_OUT
OUTPUT
RESISTORS
T/H
T/H
A
IN
A1
A
IN
B1
12
OUTPUT
RESISTORS
12
12
DFS_A
SFDR_A
DFS_B
SFDR_B
FEATURES
Two Independent 12-Bit, 125 MSPS ADCs
Channel-to-Channel Isolation, > 80 dB
AC-Coupled Signal Conditioning Included
Gain Flatness up to Nyquist, < 0.1 dB
Input VSWR 1.1:1 to Nyquist
80 dB Spurious-Free Dynamic Range
Two's Complement Output Format
3.3 V or 5 V CMOS-Compatible Output Levels
1.5 W Per Channel
Single-Ended or Differential Input
350 MHz Input Bandwidth
APPLICATIONS
Wireless and Wired Broadband Communications
Base Stations and "Zero-IF" or Direct IF Sampling
Subsystems
Wireless Local Loop (WLL)
Local Multipoint Distribution Service (LMDS)
Radar and Satellite Subsystems
PRODUCT DESCRIPTION
The AD10226 offers two complete ADC channels with on-module
signal conditioning for improved dynamic performance. Each wide
dynamic range ADC has a transformer coupled front end
optimized for direct-IF sampling. The AD10226 has on-chip
track-and-hold circuitry and utilizes an innovative architecture to
achieve 12-bit, 125 MSPS performance. The AD10226 uses
innovative high density circuit design to achieve exceptional
performance, while still maintaining excellent isolation and pro-
viding for board area savings.
The AD10226 operates with 5.0 V analog supply and 3.3 V digital
supply. Each channel is completely independent, allowing opera-
tion with independent ENCODE and analog inputs. The AD10226
is available in a 35 mm square 385-lead BGA package.
PRODUCT HIGHLIGHTS
1. Guaranteed sample rate of 125 MSPS
2. Input signal conditioning included with full-power bandwidth
to 350 MHz
3. Industry-leading IF sampling performance
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2
AD10226SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
1
Test
Parameter
Temp
Level
Min
Typ
Max
Unit
RESOLUTION
12
Bits
DC ACCURACY
Differential Nonlinearity
2
Full
IV
0.99
0.3
+0.99
LSB
Integral Nonlinearity
2
Full
IV
1.3
0.75
+1.3
LSB
No Missing Codes
Full
IV
Guaranteed
Gain Error
3
25
C
I
9
1
+9
% FS
Output Offset
25
C
I
12
+2
+12
LSB
Gain Tempco
Full
V
100
ppm/
C
Offset Tempco
Full
V
50
ppm/
C
ANALOG INPUT
Input Voltage Range
25
C
V
1.84
V p-p
Input Impedance
25
C
V
50
Input VSWR
4
Full
V
1.1:1
1.25:1
Ratio
Analog Input Bandwidth, High
Full
IV
300
350
MHz
Analog Input Bandwidth, Low
Full
IV
1
MHz
ANALOG REFERENCE
Output Voltage
25
C
V
2.5
V
Load Current
25
C
V
5
mA
Tempco
Full
V
80
ppm/
C
SWITCHING PERFORMANCE
5
Maximum Conversion Rate
Full
VI
125
MSPS
Minimum Conversion Rate
Full
IV
10
MSPS
Duty Cycle
Full
IV
45
50
55
%
Aperture Delay (t
A
)
25
C
V
2.1
ns
Aperture Uncertainty (Jitter)
25
C
V
0.25
ps rms
Output Valid Time (t
V
)
6
Full
IV
3.0
4.5
ns
Output Propagation Delay (t
PD
)
6
Full
IV
4.5
6.0
ns
Output Rise Time (t
R
)
25
C
V
3.5
ns
Output Fall Time (t
F
)
25
C
V
3.3
ns
DIGITAL INPUTS
ENCODE Input Common-Mode
Full
IV
3.75
V
Differential Input (ENC,
ENC)
Full
IV
500
mV
Logic "1" Voltage
Full
IV
2.0
V
Logic "0" Voltage
Full
IV
0.8
V
Input Resistance
Full
IV
3
6
k
Input Capacitance
25
C
V
3
pF
DIGITAL OUTPUTS
Logic "1" Voltage
6
Full
IV
3.1
3.3
V
Logic "0" Voltage
6
Full
IV
0
0.2
V
Output Coding
Two's Complement
POWER SUPPLY
7
Power Dissipation
8
Full
VI
3040
3300
mW
Power Supply Rejection Ratio
Full
IV
0.5
5.0
mV/V
Total I (DV
DD
) Current
Full
VI
40
60
mA
Total I (AV
CC
) Current
Full
VI
540
650
mA
(V
DD
= 3.3 V, V
CC
= 5.0 V; ENCODE = 125 MSPS, unless otherwise noted.)
REV. 0
3
AD10226
Test
Parameter
Temp
Level
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
Signal-to-Noise Ratio (SNR)
9
(Without Harmonics)
f
IN
= 10.3 MHz
25
C
I
66.5
68.5
dBFS
f
IN
= 49 MHz
25
C
V
67
dBFS
f
IN
= 71 MHz
25
C
I
63
66
dBFS
f
IN
= 121 MHz
25
C
V
64
dBFS
f
IN
= 250 MHz
25
C
V
60
dBFS
Signal-to-Noise Ratio (SINAD)
10
(With Harmonics)
f
IN
= 10.3 MHz
25
C
I
65.5
68
dBFS
f
IN
= 49 MHz
25
C
V
66.5
dBFS
f
IN
= 71 MHz
25
C
I
62.5
65
dBFS
f
IN
= 121 MHz
25
C
V
62.5
dBFS
f
IN
= 250 MHz
25
C
V
59.5
dBFS
Spurious-Free Dynamic Range
11
f
IN
= 10 MHz
25
C
I
76.5
82
dBFS
f
IN
= 41 MHz
25
C
V
77
dBFS
f
IN
= 71 MHz
25
C
I
66
72
dBFS
f
IN
= 121 MHz
25
C
V
71
dBFS
f
IN
= 250 MHz
25
C
V
70
dBFS
Two-Tone Intermodulation
Distortion
12
(IMD)
f
IN
= 29.3 MHz; f
IN
= 30.3 MHz
25
C
V
78
dBc
f
IN
= 150 MHz; f
IN
= 151 MHz
25
C
V
70
dBc
Channel-to-Channel Isolation
13
f
IN
= 121 MHz
Full
IV
85
dB
NOTES
1
All ac specifications tested by driving ENCODE and
ENCODE differentially, with the analog input applied to A
IN
X1 and A
IN
X2 tied to ground.
2
SFDR enabled (SFDR = 1) for DNL and INL specifications.
3
Gain error measured at 10.3 MHz.
4
Input VSWR, see TPC 14.
5
See Figure 1, Timing Diagram.
6
t
V
and t
PD
are measured from the transition points of the ENCODE input to the 50%/50% levels of the digital outputs swing. The digital output load during
test is not to exceed an ac load of 10 pF or a dc current of
40 A.
7
Supply voltages should remain stable within
5% for normal operation.
8
Power dissipation measures with encode at rated speed.
9
Analog input signal power at 1 dBFS; signal-to-noise (SNR) is the ratio of signal level to total noise (first six harmonics removed). ENCODE = 125 MSPS,
SFDR mode = 1. SNR is reported in dBFS, related back to converter full-scale.
10
Analog input signal power at 1 dBFS; signal-to-noise and distortion (SINAD) is the ratio of signal level to total noise + harmonics. ENCODE = 125 MSPS.
SINAD is reported in dBFS, related back to converter full-scale.
11
Analog input signal equals 1 dBFS; SFDR is ratio of converter full-scale to worst spur.
12
Both input tones at 7 dBFS; two-tone intermodulation distortion (IMD) rejection is the ratio of either tone to the worst third order intermod product.
13
Channel-to-channel isolation tested with A channel/50
terminated (A
IN
A2) grounded and a full-scale signal applied to B channel (A
IN
B2).
Specifications subject to change without notice.
REV. 0
AD10226
4
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD10226 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ABSOLUTE MAXIMUM RATINGS
*
V
DD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V
V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V
Analog Inputs . . . . . . . . . . . . . . . . . . . . . . 5 V p-p (18 dBm)
Digital Inputs . . . . . . . . . . . . . . . . . . . 0.5 V to V
DD
+ 0.5 V
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Operating Temperature (Ambient) . . . . . . . 55
C to +125C
Storage Temperature (Ambient) . . . . . . . . . 65
C to +150C
Maximum Junction Temperature . . . . . . . . . . . . . . . . . 150
C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only; functional operation of the device
at these or any other conditions outside of those indicated in the operation sections
of this specification is not implied. Exposure to absolute maximum ratings for
extended periods may affect device reliability.
THERMAL CHARACTERISTICS
385-Lead BGA Package:
The typical
JA
of the module as determined by an IR scan is
26.25
C/W.
t
PD
AIN
ENCODE
ENCODE
D11 D0
SAMPLE N 1
SAMPLE N
SAMPLE N 10
SAMPLE N 11
SAMPLE N 9
SAMPLE N 1
1/f
S
DATA N 11
DATA N 10
N 9
DATA N 1
DATA N
DATA N 1
t
V
N 2
Figure 1. Timing Diagram
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
AD10226AB
25
C to +85C (Ambient)
385-Lead BGA (35 mm 35 mm)
B-385
AD10226/PCB
25
C
Evaluation Board with AD10226AB
EXPLANATION OF TEST LEVELS
Test Level
I
100% production tested
II
100% production tested at 25
C and sample tested at specific
temperatures
III Sample tested only
IV Parameter is guaranteed by design and characterization
testing
V
Parameter is a typical value only
VI 100% production tested at 25
C; guaranteed by design and
characterization testing for industrial temperature range
Table I. Output Coding (V
REF
= 2.5 V) (Two's Complement)
Code
A
IN
(V)
Digital Output
+2047
+0.875
0111 1111 1111
0
0
0000 0000 0000
1
0.000427
1111 1111 1111
2048
0.875
1000 0000 0000
REV. 0
AD10226
5
PIN CONFIGURATION
35mm SQUARE
BOTTOM VIEW
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
24
22
20
18
16
14
12
10
8
6
4
2
25
23
21
19
17
15
13
11
9
7
5
3
1
PIN FUNCTION DESCRIPTIONS
Mnemonic
Function
AGNDA
A Channel Analog Ground. A and B grounds should be connected as close to the device as possible.
REF_A_OUT
A Channel Internal Voltage Reference
NC
No connection
A
IN
A1
Analog Input for A side ADC ( input)
A
IN
A2
Analog Input for A side ADC (+ input)
AV
CC
A
Analog Positive Supply Voltage (nominally 5.0 V)
DGNDA
A Channel Digital Ground
D11AD0A
Digital Outputs for ADC A. D0 (LSB)
ENCODEA
Complement of ENCODE
ENCODEA
Data conversion initiated on the rising edge of ENCODE input.
DV
CC
A
Digital Positive Supply Voltage (nominally 3.3 V)
DGNDB
B Channel Digital Ground
D11BD0B
Digital Outputs for ADC B. D0 (LSB)
AGNDB
B Channel Analog Ground. A and B grounds should be connected as close to the device as possible.
DV
CC
B
Digital Positive Supply Voltage (nominally 3.3 V)
ENCODEB
Complement of ENCODE
ENCODEB
Data conversion initiated on rising edge of ENCODE input.
REF_B_OUT
B Channel Internal Voltage Reference
A
IN
B1
Analog Input for B side ADC ( input)
A
IN
B2
Analog Input for B side ADC (+ input)
AV
CC
B
Analog Positive Supply Voltage (nominally 5.0 V)
DFS
Data format select. Low = Two's Complement, High = Binary.
SFDR Mode
CMOS control pin that enables (SFDR MODE = 1) a proprietary circuit that may improve the spurious free dynamic
range (SFDR) performance. It is useful in applications where the dynamic range of the system is limited by discrete spurious
frequency content caused by nonlinearities in the ADC transfer function. SFDR Mode = 0 for normal operation.
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