ChipFind - документация

Электронный компонент: AD14160LBB-4

Скачать:  PDF   ZIP
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
AD14160/AD14160L
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
Analog Devices, Inc., 1998
Quad-SHARC
DSP Multiprocessor Family
FUNCTIONAL BLOCK DIAGRAM
PERFORMANCE FEATURES
ADSP-21060 Core Processor (
. . .
4)
480 MFLOPS Peak, 320 MFLOPS Sustained
25 ns Instruction Rate, Single-Cycle
Instruction ExecutionEach of Four Processors
16 Mbit Shared SRAM (Internal to SHARCs)
4 Gigawords Addressable Off-Module Memory
Sixteen 40 Mbyte/s Link Ports (Four per SHARC)
Eight 40 Mbit/s Independent Serial Ports (Two
from Each SHARC)
5 V and 3.3 V Operation
32-Bit Single Precision and 40-Bit Extended
Precision IEEE Floating Point Data Formats, or
32-Bit Fixed Point Data Format
IEEE JTAG Standard 1149.1 Test Access Port and
On-Chip Emulation
PACKAGING FEATURES
452-Lead Ceramic Ball Grid Array (CBGA)
1.85" (47 mm) Body Size
0.200" Max Height
0.050" Ball Pitch
29 Grams (typical)
JC
= 0.36 C/W
GENERAL DESCRIPTION
The AD14160/AD14160L Quad-SHARC Ceramic Ball Grid
Array (CBGA) puts the power of the first generation AD14060
(CQFP) DSP multiprocessor into a very high density ball grid
array package; now with additional link and serial I/O pinned
out, beyond that from the CQFP package. The core of the multi-
processor is the ADSP-21060 DSP microcomputer. The AD14x60
modules have the highest performance--density and lowest
cost-- performance ratios of any in their class. They are ideal
for applications requiring higher levels of performance and/or
functionality per unit area.
The AD14160/AD14160L takes advantage of the built-in
multiprocessing features of the ADSP-21060 to achieve 480 peak
MFLOPS with a single chip type, in a single package. The on-
chip SRAM of the DSPs provides 16 Mbits of on-module
shared SRAM. The complete shared bus (48 data, 32 address)
is also brought off-module for interfacing with expansion
memory or other peripherals.
SHARC is a registered trademark of Analog Devices, Inc.
The ADSP-21060 link ports are interconnected to provide
direct communication among the four SHARCs as well as high
speed off-module access. Internally, links connect the SHARC
in a ring. Externally, each SHARC has a total of 160 Mbytes/s
link port bandwidth.
Multiprocessor performance is enhanced with embedded power
and ground planes, matched impedance interconnect, and opti-
mized signal routing lengths and separation. The fully tested
and ready-to-insert multiprocessor also significantly reduces
board space.
ID
2-0
CPA
SPORT 1
SPORT 0
TDI
EBOOT,
LBOOT,
BMS
CS
TIMEXP
LINK 1
LINK 2
LINK 3
LINK 4
IRQ
2-0
FLAG
3-0
CS
TIMEXP
LINK 1
LINK 2
LINK 3
LINK 4
IRQ
2-0
FLAG
3-0
EMU
CLKIN
RESET
EMU
CLKIN
RESET
CS
TIMEXP
LINK 1
LINK 2
LINK 3
LINK 4
IRQ
2-0
FLAG
3-0
TCK, TMS, TRST
EBOOT,
LBOOT, BMS
ID
2-0
CPA
SPORT 1
SPORT 0
TDO
ID
2-0
CPA
SPORT 1
SPORT 0
TCK, TMS, TRST
TCK, TMS, TRST
CS
TIMEXP
LINK 1
LINK 2
LINK 3
LINK 4
IRQ
2-0
FLAG
3-0
LINK 0
LINK 5
TDO
TDO
LINK 0
LINK 5
TDI
TCK, TMS, TRST
TDI
SHARC_D
SHARC_A
SHARC_C
AD14160/
AD14160L
ID
2-0
CPA
SPORT 1
SPORT 0
EBOOT,
LBOOT, BMS
SHARC_B
LINK 0
LINK 5
TDI
LINK 0
LINK 5
TDO
EMU
CLKIN
RESET
EMU
CLKIN
RESET
EBOOT,
LBOOT,
BMS
SHARC BUS (
ADDR
31-0
,
DATA
47-0
,
MS
3-0
,
RD, WR, PAGE, ADRCLK, SW, ACK,
SBTS, HBR, HBG, REDY, BR
6-1
, RPBA, DMAR
1.2
, DMAG
1.2
)
s
s
s
s
AD14160/AD14160L
2
REV. A
DETAILED DESCRIPTION
Architectural Features
ADSP-21060 Core
The AD14160/AD14160L is based on the powerful ADSP-21060
(SHARC) DSP chip. The ADSP-21060 SHARC combines a
high performance floating-point DSP core with integrated, on-
chip system features including a 4 Mbit SRAM memory, host
processor interface, DMA controller, serial ports, and both link
port and parallel bus connectivity for glueless DSP multiprocess-
ing, (see Figure 1). It is fabricated in a high speed, low power
CMOS process, and has a 25 ns instruction cycle time. The arith-
metic/ logic unit (ALU), multiplier and shifter all perform single-
cycle instructions, and the three units are arranged in parallel,
maximizing computational throughput.
The SHARC features an enhanced Harvard architecture in
which the data memory (DM) bus transfers data, and the pro-
gram memory (PM) bus transfers both instructions and data.
There is also an on-chip instruction cache which selectively
caches only those instructions whose fetches conflict with the
PM bus data accesses. This combines with the separate program
and data memory buses to enable three-bus operation for fetch-
ing an instruction and two operands, all in a single cycle. The
SHARC also contains a general purpose data register file, which
is a 10-port, 32-register (16 primary, 16 secondary) file. Each
SHARC's core also implements two data address generators
(DAGs), implementing circular data buffers in hardware. The
DAGs contain sufficient registers to allow the creation of up to
32 circular buffers. The 48-bit instruction word accommodates a
variety of parallel operations, for concise programming. For ex-
ample, the ADSP-21060 can conditionally execute a multiply, an
add, a subtract, and a branch, all in a single instruction.
The SHARCs contain 4 Mbits of on-chip SRAM each, orga-
nized as two blocks of 2 Mbits, which can be configured for
different combinations of code and data storage. The memory
can be configured as a maximum of 128K words of 32-bit data,
256K words of 16-bit data, 80K words of 48-bit instructions (or
40-bit data), or combinations of different word sizes up to
4 megabits. A 16-bit floating-point storage format is supported
which effectively doubles the amount of data that may be stored
on chip. Conversion between the 32-bit floating point and 16-
bit floating point formats is done in a single instruction. Each
memory block is dual-ported for single-cycle, independent
accesses by the core processor and I/O processor or DMA con-
troller. The dual-ported memory and separate on-chip buses
allow two data transfers from the core and one from I/O, all in a
single cycle.
SERIAL PORTS
(2)
LINK PORTS
(6)
4
6
6
36
IOP
REGISTERS
(
MEMORY MAPPED)
CONTROL,
STATUS, AND
DATA BUFFERS
I/O PROCESSOR
TIMER
INSTRUCTION
CACHE
32 x 48-BIT
ADDR
DATA
DATA
DATA
ADDR
ADDR
DATA
ADDR
TWO INDEPENDENT
DUAL-PORTED BLOCKS
PROCESSOR PORT
I/O PORT
BLOCK 0
BLOCK 1
JTAG
TEST AND
EMULATION
7
HOST PORT
ADDR BUS
MUX
IOA
17
IOD
48
MULTIPROCESSOR
INTERFACE
DUAL-PORTED SRAM
EXTERNAL
PORT
DATA BUS
MUX
48
32
24
PM ADDRESS BUS
DM ADDRESS BUS
PM DATA BUS
DM DATA BUS
BUS
CONNECT
(PX)
DATA
REGISTER
FILE
16 x 40-BIT
BARREL
SHIFTER
ALU
MULTIPLIER
DAG1
8 x 4 x 32
32
48
40/32
CORE PROCESSOR
DMA
CONTROLLER
PROGRAM
SEQUENCER
DAG2
8 x 4 x 24
Figure 1. ADSP-21060 Processor Block Diagram (Core of the AD14160/AD14160L)
AD14160/AD14160L
3
REV. A
IOP REGISTERS
NORMAL WORD ADDRESSING
0x0000 0000
0x0002 0000
0x0004 0000
0x0008 0000
0x0010 0000
0x0018 0000
0x0020 0000
0x0028 0000
0x0030 0000
0x0038 0000
0x003F FFFF
SHORT WORD ADDRESSING
INTERNAL MEMORY SPACE
OF SHARC_B
ID=010
INTERNAL MEMORY SPACE
OF SHARC_A
ID=001
INTERNAL MEMORY SPACE
OF SHARC_C
ID=011
INTERNAL MEMORY SPACE
OF SHARC_D
ID=100
INTERNAL MEMORY SPACE
OF ADSP-2106x
WITH ID=101
INTERNAL MEMORY SPACE
OF ADSP-2106x
WITH ID=110
BROADCAST WRITE
TO ALL
ADSP-2106xs
NORMAL WORD ADDRESSING: 32-BIT DATA WORDS
48-BIT INSTRUCTION WORDS
SHORT WORD ADDRESSING: 16-BIT DATA WORDS
MS
0
BANK 0
0x0040 0000
0xFFFF FFFF
MULTIPROCESSOR
MEMORY SPACE
BANK 1
BANK 2
DRAM
(OPTIONAL)
BANK 3
NONBANKED
MS
1
MS
2
MS
3
BANK SIZE IS
SELECTED BY
MSIZE BIT FIELD OF
SYSCON
REGISTER.
EXTERNAL
MEMORY
SPACE
INTERNAL
MEMORY
SPACE
(INDIVIDUAL
SHARCs)
INTERNAL
TO AD14160x
EXTERNAL
TO AD14160x
Figure 2. AD14160/AD14160L Memory Map
CLKIN
RESET
BOOTSELECT A
BOOTSELECT BCD
SPORT0
JTAG
1X CLOCK
LINKS 1, 2, 3, & 4;
IRQ
2-0
;
FLAG
3-0
;
TIMEXP,
SPORT1
CPA
ID
2-0
SHARC_D
LINKS 1, 2, 3, & 4;
IRQ
2-0
;
FLAG
3-0
;
TIMEXP,
SPORT1
CPA
ID
2-0
SHARC_C
RD
WR
ACK
MS
3-0
PAGE
SBTS
SW
ADRCLK
CS
HBR
HBG
REDY
BR
1-6
DATA
47-0
ADDR
31-0
SHARC_A
LINKS 1, 2, 3, & 4;
IRQ
2-0
;
FLAG
3-0
;
TIMEXP,
SPORT1
CPA
ID
2-0
SHARC_B
LINKS 1, 2, 3, & 4;
IRQ
2-0
;
FLAG
3-0
;
TIMEXP,
SPORT1
CPA
ID
2-0
AD14160/
AD14160L
(QUAD PROCESSOR
CLUSTER)
SYSTEM EXPANSION
SPORT1
RPBA
DMAR1,2
DMAG1,2
Figure 3. Complete Shared Memory Multiprocessing System
AD14160/AD14160L
4
REV. A
Shared Memory Multiprocessing
The AD14160/AD14160L takes advantage of the powerful
multiprocessing features built into the SHARC. The SHARCs are
connected to maximize the performance of this cluster-of-four
architecture, and still allow for off-module expansion. The
AD14160/AD14160L in itself is a complete shared memory
multiprocessing system, as shown in Figure 3. The unified ad-
dress space of the SHARCs allows direct interprocessor ac-
cesses of each SHARCs' internal memory. In other words, each
SHARC can directly access the internal memory and IOP registers
of each of the other SHARCs by simply reading or writing to the
appropriate address in multi-processor memory space (see Fig-
ure 2)--this is called a direct read or direct write.
Bus arbitration is accomplished with the on-SHARC arbitration
logic. Each SHARC has a unique ID, and drives the Bus-Request
(BR) line corresponding to its ID, while monitoring all others.
BR1BR4 are used within the AD14160/AD14160L, while BR5
and
BR6 can be used for expansion. All bus requests (BR1BR6)
are included in the module I/O.
Two different priority schemes, fixed and rotating, are available
to resolve competing bus requests. The RPBA pin selects which
scheme is used: when RPBA is high, rotating priority bus arbitra-
tion is selected, and when RPBA is low, fixed priority is selected.
Table I. Rotating Priority Arbitration Example
Hardware Processor IDs
Cycle
ID1
ID2
ID3
ID4
ID5 ID6
1
M
1
2 BR
3
4
5
Initial Priority Assignments
2
4
5 BR
M-BR
1
2
3
3
4
5 BR
M
1
2
3
4
5 BR M
1
2
3
4 BR
5
1 BR 2
3
4
5
M
Final Priority Assignments
NOTES
15 = Assigned Priority.
M = Bus Mastership (in that cycle).
BR = Requesting Bus Mastership with BRx.
Bus mastership is passed from one SHARC to another during a
bus transition cycle. A bus transition cycle only occurs when the
current bus master deasserts its BR line and one of the slave
SHARCs asserts its BR line. The bus master can therefore re-
tain bus mastership by keeping its BR line asserted. When the
bus master deasserts its BR line, and no other BR line is as-
serted, then the master will not lose any bus cycles. When more
than one SHARC asserts its BR line, the SHARC with the
highest priority request becomes bus master on the following
cycle. Each SHARC observes all of the BR lines, and therefore
tracks when a bus transition cycle has occurred, and which
processor has become the new bus master. Master processor
changeover incurs only one cycle of overhead. An example bus
transition sequence is shown in Table I.
Bus locking is possible, allowing indivisible read-modify-write
sequences for semaphores. In either the fixed or rotating priority
scheme, it is also possible to limit the number of cycles the
master can control the bus. The AD14160/AD14160L also
provides the option of using the Core Priority Access (CPA)
mode of the SHARC. Using the CPA signal allows external bus
accesses by the core processor of a slave SHARC to take priority
over ongoing DMA transfers. Also, each SHARC can broadcast
write to all other SHARCs simultaneously, allowing the implemen-
tation of reflective semaphores.
The bus master can communicate with slave SHARCs by writ-
ing messages to their internal IOP registers. The MSRG0
MSRG7 registers are general-purpose registers that can be used
for convenient message passing, semaphores and resource shar-
ing between the SHARCs. For message passing, the master
communicates with a slave by writing and/or reading any of the
eight message registers on the slave. For vector interrupts, the
master can issue a vector interrupt to a slave by writing the
address of an interrupt service routine to the slave's VIRPT
register. This causes an immediate high priority interrupt on the
slave which, when serviced, will cause it to branch to the speci-
fied service routine.
Off-Module Memory and Peripherals Interface
The AD14160/AD14160L's external port provides the interface to
off-module memory and peripherals (see Figure 5). This port
consists of the complete external port bus of the SHARC, bused
together in common among the four SHARCs.
The 4-gigaword off-module address space is included in the
AD14160/AD14160L's unified address space. Addressing of
external memory devices is facilitated by each SHARC inter-
nally decoding the high order address lines to generate memory
bank select signals. Separate control lines are also generated for
simplified addressing of page-mode DRAM. The AD14160/
AD14160L also supports programmable memory wait states and
external memory acknowledge controls to allow interfacing to
DRAM and peripherals with variable access, hold and disable
time requirements.
Link Port I/O
Each individual SHARC features six 4-bit link ports that facili-
tate SHARC-to-SHARC communication and external I/O inter-
facing. Each link port can be configured for either 1
or 2
operation, allowing each to transfer either 4 or 8 bits per cycle.
The link ports can operate independently and simultaneously,
with a maximum bandwidth of 40 MBytes/s each, or a total of
240 MBytes/s per SHARC.
The AD14160/AD14160L provides additional link port I/O
beyond that of the AD14060. Internally, two links from each
SHARC form a ring connection among the four. The remaining
four link ports from each SHARC are brought out indepen-
dently from each SHARC. A maximum of 640 MBytes/s link
port bandwidth is then available off of the AD14160/AD14160L.
The link port connections are detailed in Figure 4.
SHARC_A
SHARC_B
SHARC_D
SHARC_C
1
2
4
3
1
2
4
3
5
5
5
5
0
0
0
0
1
2
4
3
1
2
4
3
Figure 4. Link Port Connections
AD14160/AD14160L
5
REV. A
ADDR
310
DATA
470
CPA
BR
26
BR
1
BMS
CONTROL
AD14160/
AD14160L
5
1x
CLOCK
RESET
ADDR
DATA
HOST
PROCESSOR
INTERFACE
(OPTIONAL)
ACK
CS
GLOBAL
MEMORY
AND
PERIPHERALS
(OPTIONAL)
OE
WE
ADDR
DATA
CS
ADDR
DATA
BOOT
EPROM
(OPTIONAL)
RD
WR
MS
30
SBTS
SW
ADRCLK
CS
HBR
HBG
REDY
ACK
RESET
RPBA
CLKIN
PAGE
CPA
BR
15
BR
6
CONTROL
ADSP-2106x #6
(OPTIONAL)
ADDR
310
DATA
470
5
RESET
RPBA
CLKIN
ADDR
310
DATA
470
CPA
BR
1, 2, 3, 4, 6
BR
5
CONTROL
ADSP-2106x #5
(OPTIONAL)
5
3
ID
3
ID
RESET
RPBA
CLKIN
SERIALS
LINKS
DISCRETES
3
ID
Figure 5. Optional System Interconnections