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Электронный компонент: AD1674BD

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FUNCTIONAL BLOCK DIAGRAM
REF OUT
SHA
COMP
20k
10k
5k
2.5k
2.5k
5k
12
12
AD1674
AGND
BIP OFF
REF IN
20V
IN
10V
IN
IDAC
12
CONTROL
CE
12/8
CS
R/C
A
0
5k
10k
SAR
CLOCK
10V
REF
REGISTERS / 3-STATE OUTPUT BUFFERS
DAC
STS
DB11 (MSB)
DB0 (LSB)
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
12-Bit 100 kSPS
A/D Converter
AD1674*
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
FEATURES
Complete Monolithic 12-Bit 10 s Sampling ADC
On-Board Sample-and-Hold Amplifier
Industry Standard Pinout
8- and 16-Bit Microprocessor Interface
AC and DC Specified and Tested
Unipolar and Bipolar Inputs
5 V, 10 V, 0 V10 V, 0 V20 V Input Ranges
Commercial, Industrial and Military Temperature
Range Grades
MIL-STD-883 and SMD Compliant Versions Available
PRODUCT DESCRIPTION
The AD1674 is a complete, multipurpose, 12-bit analog-to-
digital converter, consisting of a user-transparent onboard
sample-and-hold amplifier (SHA), 10 volt reference, clock and
three-state output buffers for microprocessor interface.
The AD1674 is pin compatible with the industry standard
AD574A and AD674A, but includes a sampling function while
delivering a faster conversion rate. The on-chip SHA has a wide
input bandwidth supporting 12-bit accuracy over the full
Nyquist bandwidth of the converter.
The AD1674 is fully specified for ac parameters (such as S/(N+D)
ratio, THD, and IMD) and dc parameters (offset, full-scale
error, etc.). With both ac and dc specifications, the AD1674 is
ideal for use in signal processing and traditional dc measure-
ment applications.
The AD1674 design is implemented using Analog Devices'
BiMOS II process allowing high performance bipolar analog cir-
cuitry to be combined on the same die with digital CMOS logic.
Five different temperature grades are available. The AD1674J
and K grades are specified for operation over the 0
C to +70
C
temperature range. The A and B grades are specified from
40
C to +85
C; the AD1674T grade is specified from 55
C
to +125
C. The J and K grades are available in both 28-lead
plastic DIP and SOIC. The A and B grade devices are available
in 28-lead hermetically sealed ceramic DIP and 28-lead SOIC.
The T grade is available in 28-lead hermetically sealed ceramic
DIP.
*Protected by U. S. Patent Nos. 4,962,325; 4,250,445; 4,808,908; RE30586 .
PRODUCT HIGHLIGHTS
1. Industry Standard Pinout: The AD1674 utilizes the pinout
established by the industry standard AD574A and AD674A.
2. Integrated SHA: The AD1674 has an integrated SHA which
supports the full Nyquist bandwidth of the converter. The
SHA function is transparent to the user; no wait-states are
needed for SHA acquisition.
3. DC and AC Specified: In addition to traditional dc specifica-
tions, the AD1674 is also fully specified for frequency do-
main ac parameters such as total harmonic distortion,
signal-to-noise ratio and input bandwidth. These parameters
can be tested and guaranteed as a result of the onboard
SHA.
4. Analog Operation: The precision, laser-trimmed scaling and
bipolar offset resistors provide four calibrated ranges:
0 V to +10 V and 0 V to +20 V unipolar, 5 V to +5 V and
10 V to +10 V bipolar. The AD1674 operates on +5 V and
12 V or
15 V power supplies.
5. Flexible Digital Interface: On-chip multiple-mode
three-state output buffers and interface logic allow direct
connection to most microprocessors.
AD1674SPECIFICATIONS
DC SPECIFICATIONS
AD1674J
AD1674K
Parameter
Min
Typ
Max
Min
Typ
Max
Unit
RESOLUTION
12
12
Bits
INTEGRAL NONLINEARITY (INL)
1
1/2
LSB
DIFFERENTIAL NONLINEARITY (DNL)
(No Missing Codes)
12
12
Bits
UNIPOLAR OFFSET
1
@ +25
C
3
2
LSB
BIPOLAR OFFSET
1
@ +25
C
6
4
LSB
FULL-SCALE ERROR
1, 2
@ +25
C
(with Fixed 50
Resistor from REF OUT to REF IN)
0.1
0.25
0.1
0.25
% of FSR
TEMPERATURE RANGE
0
+70
0
+70
C
TEMPERATURE DRIFT
3
Unipolar Offset
2
2
1
LSB
Bipolar Offset
2
2
1
LSB
Full-Scale Error
2
6
3
LSB
POWER SUPPLY REJECTION
V
CC
= 15 V
1.5 V or 12 V
0.6 V
2
1
LSB
V
LOGIC
= 5 V
0.5 V
1/2
1/2
LSB
V
EE
= 15 V
1.5 V or 12 V
0.6 V
2
1
LSB
ANALOG INPUT
Input Ranges
Bipolar
5
+5
5
+5
Volts
10
+10
10
+10
Volts
Unipolar
0
+10
0
+10
Volts
0
+20
0
+20
Volts
Input Impedance
10 Volt Span
3
5
7
3
5
7
k
20 Volt Span
6
10
14
6
10
14
k
POWER SUPPLIES
Operating Voltages
V
LOGIC
+4.5
+5.5
+4.5
+5.5
Volts
V
CC
+11.4
+16.5
+11.4
+16.5
Volts
V
EE
16.5
11.4
16.5
11.4
Volts
Operating Current
I
LOGIC
5
8
5
8
mA
I
CC
10
14
10
14
mA
I
EE
14
18
14
18
mA
POWER DISSIPATION
385
575
385
575
mW
INTERNAL REFERENCE VOLTAGE
9.9
10.0
10.1
9.9
10.0
10.1
Volts
Output Current (Available for External Loads)
4
2.0
2.0
mA
(External Load Should Not Change During Conversion
NOTES
1
Adjustable to zero.
2
Includes internal voltage reference error.
3
Maximum change from 25
C value to the value at T
MIN
or T
MAX
.
4
Reference should be buffered for
12 V operation.
All min and max specifications are guaranteed.
Specifications subject to change without notice.
REV. C
2
(T
MIN
to T
MAX
, V
CC
= +15 V 10% or +12 V 5%, V
LOGIC
= +5 V 10%, V
EE
= 15 V 10% or
12 V 5% unless otherwise noted)
REV. C
3
AD1674
AD1674A
AD1674B
AD1674T
Parameter
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
RESOLUTION
12
12
12
Bits
INTEGRAL NONLINEARITY (INL)
1
1/2
1/2
LSB
1
1/2
1
LSB
DIFFERENTIAL NONLINEARITY (DNL)
(No Missing Codes)
12
12
12
Bits
UNIPOLAR OFFSET
1
@ +25
C
2
2
2
LSB
BIPOLAR OFFSET
1
@ +25
C
6
3
3
LSB
FULL-SCALE ERROR
1, 2
@ +25
C
(with Fixed 50
Resistor from REF OUT to REF IN)
0.1
0.25
0.1
0.125
0.1
0.125
% of FSR
TEMPERATURE RANGE
40
+85
40
+85
55
+125
C
TEMPERATURE DRIFT
3
Unipolar Offset
2
2
1
1
LSB
Bipolar Offset
2
2
1
2
LSB
Full-Scale Error
2
8
5
7
LSB
POWER SUPPLY REJECTION
V
CC
= 15 V
1.5 V or 12 V
0.6 V
2
1
1
LSB
V
LOGIC
= 5 V
0.5 V
1/2
1/2
1/2
LSB
V
EE
= 15 V
1.5 V or 12 V
0.6 V
2
1
1
LSB
ANALOG INPUT
Input Ranges
Bipolar
5
+5
5
+5
5
+5
Volts
10
+10
10
+10
10
+10
Volts
Unipolar
0
+10
0
+10
0
+10
Volts
0
+20
0
+20
0
+20
Volts
Input Impedance
10 Volt Span
3
5
7
3
5
7
3
5
7
k
20 Volt Span
6
10
14
6
10
14
6
10
14
k
POWER SUPPLIES
Operating Voltages
V
LOGIC
+4.5
+5.5
+4.5
+5.5
+4.5
+5.5
Volts
V
CC
+11.4
+16.5 +11.4
+16.5 +11.4
+16.5
Volts
V
EE
16.5
11.4 16.5
11.4 16.5
11.4
Volts
Operating Current
I
LOGIC
5
8
5
8
5
8
mA
I
CC
10
14
10
14
10
14
mA
I
EE
14
18
14
18
14
18
mA
POWER DISSIPATION
385
575
385
575
385
575
mW
INTERNAL REFERENCE VOLTAGE
9.9
10.0
10.1
9.9
10.0
10.1
9.9
10.0
10.1
Volts
Output Current (Available for External Loads)
4
2.0
2.0
2.0
mA
(External Load Should Not Change During Conversion
AD1674SPECIFICATIONS
AC SPECIFICATIONS
AD1674J/A
AD1674K/B/T
Parameter
Min
Typ
Max
Min
Typ
Max
Units
Signal to Noise and Distortion (S/N+D) Ratio
2, 3
69
70
70
71
dB
Total Harmonic Distortion (THD)
4
90
82
90
82
dB
0.008
0.008
%
Peak Spurious or Peak Harmonic Component
92
82
92
82
dB
Full Power Bandwidth
1
1
MHz
Full Linear Bandwidth
500
500
kHz
Intermodulation Distortion (IMD)
5
Second Order Products
90
80
90
80
dB
Third Order Products
90
80
90
80
dB
SHA (Specifications are Included in Overall Timing Specifications)
Aperture Delay
50
50
ns
Aperture Jitter
250
250
ps
Acquisition Time
1
1
s
DIGITAL SPECIFICATIONS
Parameter
Test Conditions
Min
Max
Units
LOGIC INPUTS
V
IH
High Level Input Voltage
+2.0
V
LOGIC
+0.5 V
V
V
IL
Low Level Input Voltage
0.5
+0.8
V
I
IH
High Level Input Current (V
IN
= 5 V)
V
IN
= V
LOGIC
10
+10
A
I
IL
Low Level Input Current (V
IN
= 0 V)
V
IN
= 0 V
10
+10
A
C
IN
Input Capacitance
10
pF
LOGIC OUTPUTS
V
OH
High Level Output Voltage
I
OH
= 0.5 mA
+2.4
V
V
OL
Low Level Output Voltage
I
OL
= 1.6 mA
+0.4
V
I
OZ
High-Z Leakage Current
V
IN
= 0 to V
LOGIC
10
+10
A
C
OZ
High-Z Output Capacitance
10
pF
NOTES
1
f
IN
amplitude = 0.5 dB (9.44 V p-p) 10 V bipolar mode unless otherwise noted. All measurements referred to 0 dB (9.997 V p-p) input signal unless
otherwise noted.
2
Specified at worst case temperatures and supplies after one minute warm-up.
3
See Figures 12 and 13 for other input frequencies and amplitudes.
4
See Figure 11.
5
fa = 9.08 kHz, fb = 9.58 kHz with f
SAMPLE
= 100 kHz. See Definition of Specifications section and Figure 15.
All min and max specifications are guaranteed.
Specifications subject to change without notice.
4
REV. C
(T
MIN
to T
MAX
, with V
CC
= +15 V 10% or +12 V 5%, V
LOGIC
= +5 V 10%, V
EE
= 15 V 10% or
12 V 5%, f
SAMPLE
= 100 kSPS, f
IN
= 10 kHz, stand-alone mode unless otherwise noted)
1
(for all grades T
MIN
to T
MAX
, with V
CC
= +15 V 10% or +12 V 5%, V
LOGIC
= +5 V 10%,
V
EE
= 15 V 10% or 12 V 5%)
AD1674
REV. C
5
(for all grades T
MIN
to T
MAX
with V
CC
= +15 V 10% or +12 V 5%,
V
LOGIC
= +5 V 10%, V
EE
= 15 V 10% or 12 V 5%; V
IL
= 0.4 V,
V
IH
= 2.4 V unless otherwise noted)
SWITCHING SPECIFICATIONS
CONVERTER START TIMING (Figure 1)
J, K, A, B, Grades
T Grade
Parameter
Symbol Min Typ
Max
Min Typ Max Units
Conversion Time
8-Bit Cycle
t
C
7
8
7
8
s
12-Bit Cycle
t
C
9
10
9
10
s
STS Delay from CE
t
DSC
200
225 ns
CE Pulse Width
t
HEC
50
50
ns
CS
to CE Setup
t
SSC
50
50
ns
CS
Low During CE High t
HSC
50
50
ns
R/C to CE Setup
t
SRC
50
50
ns
R/C Low During CE High t
HRC
50
50
ns
A
0
to CE Setup
t
SAC
0
0
ns
A
0
Valid During CE High t
HAC
50
50
ns
READ TIMING--FULL CONTROL MODE (Figure 2)
J, K, A, B, Grades
T Grade
Parameter
Symbol Min
Typ
Max
Min Typ Max Units
Access Time
t
DD
1
75
150
75
150 ns
Data Valid After CE Low
t
HD
25
2
25
2
ns
20
3
15
4
ns
Output Float Delay
t
HL
5
150
150 ns
CS
to CE Setup
t
SSR
50
50
ns
R/C to CE Setup
t
SRR
0
0
ns
A
0
to CE Setup
t
SAR
50
50
ns
CS
Valid After CE Low
t
HSR
0
0
ns
R/C High After CE Low
t
HRR
0
0
ns
A
0
Valid After CE Low
t
HAR
50
50
ns
NOTES
1
t
DD
is measured with the load circuit of Figure 3 and is defined as the time
required for an output to cross 0.4 V or 2.4 V.
2
0
C to T
MAX
.
3
At 40
C.
4
At 55
C.
5
t
HL
is defined as the time required for the data lines to change 0.5 V when
loaded with the circuit of Figure 3.
All min and max specifications are guaranteed.
Specifications subject to change without notice.
Test
V
CP
C
OUT
Access Time High Z to Logic Low
5 V
100 pF
Float Time Logic High to High Z
0 V
10 pF
Access Time High Z to Logic High
0 V
100 pF
Float Time Logic Low to High Z
5 V
10 pF
t
HEC
CE
STS
DB11 DB0
A
0
CS
__
R/C
_
t
SSC
t
HSC
t
SRC
t
HRC
t
SAC
t
HAC
t
C
t
DSC
HIGH IMPEDANCE
Figure 1. Converter Start Timing
HIGH
IMPEDANCE
CE
STS
DB11 DB0
A
0
CS
__
R/C
_
t
HSR
t
SSR
t
HRR
t
SAR
t
HAR
t
DD
t
HL
HIGH
IMP.
DATA
VALID
t
HD
t
HS
t
SSR
Figure 2. Read Timing
V
CP
D
OUT
C
OUT
I
OH
I
OL
Figure 3. Load Circuit for Bus Timing Specifications