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Электронный компонент: AD1833ACST

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REV. 0
AD1833A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
2003 Analog Devices, Inc. All rights reserved.
Multichannel,
24-Bit, 192 kHz, - DAC
FEATURES
5 V Stereo Audio System with 3.3 V Tolerant Digital
Interface
Supports 96 kHz Sample Rates on 6 Channels and
192 kHz on 2 Channels
Supports 16-/20-/24-Bit Word Lengths
Multibit - Modulators with
Perfect Differential Linearity Restoration for
Reduced Idle Tones and Noise Floor
Data Directed Scrambling DACs--Least Sensitive to
Jitter
Differential Output for Optimum Performance
DACs Signal-to-Noise and Dynamic Range: 110 dB
94 dB THD + N--6-Channel Mode
95 dB THD + N--2-Channel Mode
On-Chip Volume Control per Channel with 1024-Step
Linear Scale
Software Controllable Clickless Mute
Digital De-emphasis Processing
Supports 256
f
S
, 512
f
S
, and 768
f
S
Master
Clock Modes
Power-Down Mode Plus Soft Power-Down Mode
Flexible Serial Data Port with Right-Justified,
Left-Justified, I
2
S Compatible, and DSP Serial Port Modes
Supports Packed Data Mode and TDM Mode
48-Lead LQFP Plastic Package
APPLICATIONS
DVD Video and Audio Players
Home Theater Systems
Automotive Audio Systems
Set-Top Boxes
Digital Audio Effects Processors
FUNCTIONAL BLOCK DIAGRAM
AGND
DGND
FILTR FILTD
MCLK
CDATA
CLATCH
CCLK
OUTLP1
OUTLN1
OUTLP2
OUTLN2
OUTLP3
OUTLN3
OUTRP3
OUTRN3
OUTRP2
OUTRN2
OUTRP1
OUTRN1
ZERO FLAGS
DV
D D 1
DV
D D 2
AV
D D
RESET
SOUT
AD1833A
SPI
PORT
DATA
PORT
L/RCLK
BCLK
SDIN1
SDIN2
SDIN3
INTERPOLATOR
DAC
INTERPOLATOR
DAC
INTERPOLATOR
DAC
INTERPOLATOR
DAC
INTERPOLATOR
DAC
FILTER
ENGINE
INTERPOLATOR
DAC
GENERAL DESCRIPTION
The AD1833A is a complete, high performance, single-chip,
multichannel, digital audio playback system. It features six audio
playback channels, each comprising a high performance digital
interpolation filter, a multibit
S-D modulator featuring Analog
Devices' patented technology, and a continuous-time voltage-out
analog DAC section. Other features include an on-chip clickless
attenuator and mute capability for each channel, programmed
through an SPI compatible serial control port.
The AD1833A is fully compatible with all known DVD formats,
accommodating word lengths of up to 24 bits at sample rates of
48 kHz and 96 kHz on all six channels while supporting a 192 kHz
sample rate on two channels. It also provides the Redbook stan-
dard 50
ms/15 ms digital de-emphasis filters at sample rates of
32 kHz, 44.1 kHz, and 48 kHz.
The AD1833A has a very flexible serial data input port that
allows glueless interconnection to a variety of ADCs, DSP chips,
AES/EBU receivers, and sample rate converters. It can be con-
figured in right-justified, left-justified, I
2
S, or DSP serial port
compatible modes. The AD1833A accepts serial audio data in MSB
first, twos complement format. The AD1833A can be operated
from a single 5 V power supply; it also features a separate supply
pin for its digital interface that allows it to be interfaced to devices
using 3.3 V power supplies.
The AD1833A is fabricated on a single monolithic integrated
circuit and is housed in a 48-lead LQFP package for operation
from 40
C to +85C.
REV. 0
2
AD1833ASPECIFICATIONS
Parameter
Min
Typ
Max
Unit
Test Conditions
ANALOG PERFORMANCE
DIGITAL-TO-ANALOG CONVERTERS
Dynamic Range (20 Hz to 20 kHz, 60 dBFS Input)
with A-Weighted Filter
AD1833AA
106.5
110.0
dB
AD1833AA
110.5
dB
f
S
= 96 kHz
AD1833AC
107.0
dB
Total Harmonic Distortion + Noise
95
89
dB
Two channels active
94
dB
Six channels active
95
dB
96 kHz, two channels active
94
dB
96 kHz, six channels active
SNR
110
dB
Interchannel Isolation
108
dB
DC Accuracy
Gain Error
3
%
Interchannel Gain Mismatch
0.2
%
Gain Drift
80
ppm/
C
Interchannel Crosstalk (EIAJ Method)
120
dB
Interchannel Phase Deviation
0.1
Degrees
Volume Control Step Size (1023 Linear Steps)
0.098
%
Volume Control Range (Max Attenuation)
+63.5 (0.098)
dB (%)
Mute Attenuation
63.5 (0.098)
dB (%)
De-emphasis Gain Error
0.1
dB
Full-Scale Output Voltage at Each Pin (Single-Ended)
1 (2.8)
V rms (V p-p)
Output Resistance Measured Differentially
150
W
Common-Mode Output Volts
2.2
V
DAC INTERPOLATION FILTER--8 Mode (48 kHz)
Pass Band
21.768
kHz
Pass-Band Ripple
0.01
dB
Stop Band
24
kHz
Stop-Band Attenuation
70
dB
Group Delay
510
ms
DAC INTERPOLATION FILTER--4 Mode (96 kHz)
Pass Band
37.7
kHz
Pass-Band Ripple
0.03
dB
Stop Band
55.034
kHz
Stop-Band Attenuation
70
dB
Group Delay
160
ms
DAC INTERPOLATION FILTER--2 Mode (192 kHz)
Pass Band
89.954
kHz
Pass-Band Ripple
1
dB
Stop Band
104.85
kHz
Stop-Band Attenuation
70
dB
Group Delay
140
ms
TEST CONDITIONS, UNLESS OTHERWISE NOTED
*
Supply Voltages (AV
DD
, DV
DDX
)
5 V
Ambient Temperature
25
C
Input Clock
12.288 MHz, (8 Mode)
Input Signal
Nominally 1 kHz, 0 dBFS
(Full-Scale)
Input Sample Rate
48 kHz
Measurement Bandwidth
20 Hz to 20 kHz
Word Width
24 Bits
Load Capacitance
100 pF
Load Impedance
10 k
W
*Performance is identical for all channels (except for the Interchannel Gain
Mismatch and Interchannel Phase Deviation specifications).
REV. 0
3
AD1833A
Parameter
Min
Typ
Max
Unit
Test Conditions
DIGITAL I/O
Input Voltage HI
2.4
V
Input Voltage LO
0.8
V
Output Voltage HI
DV
DD2
0.4
V
Output Voltage LO
0.4
V
POWER SUPPLIES
Supply Voltage (AV
DD
and DV
DD1
)
4.5
5
5.5
V
Supply Voltage (DV
DD2
)
3.3
DV
DD1
V
Supply Current I
ANALOG
38.5
42
mA
Supply Current I
DIGITAL
42
48
mA
Active
2
mA
Power-Down
Power Supply Rejection Ratio
1 kHz 300 mV p-p Signal at Analog Supply Pins
60
dB
20 kHz 300 mV p-p Signal at Analog Supply Pins
50
dB
Specifications subject to change without notice.
DIGITAL TIMING
Parameter
Min
Max
Unit
Comments
MASTER CLOCK AND RESET
t
ML
MCLK LO (All Modes)
*
15
ns
24 MHz clock, clock doubler bypassed
t
MH
MCLK HI (All Modes)
*
15
ns
24 MHz clock, clock doubler bypassed
t
PDR
PD/RST LO
20
ns
SPI PORT
t
CCH
CCLK HI Pulsewidth
20
ns
t
CCL
CCLK LO Pulsewidth
20
ns
t
CCP
CCLK Period
80
ns
t
CDS
CDATA Setup Time
10
ns
To CCLK rising
t
CDH
CDATA Hold Time
10
ns
From CCLK rising
t
CLS
CLATCH Setup
10
ns
To CCLK rising
t
CLH
CLATCH Hold
10
ns
From CCLK rising
DAC SERIAL PORT
t
DBH
BCLK HI
15
ns
t
DBL
BCLK LO
15
ns
t
DLS
L/RCLK Setup
10
ns
To BCLK rising
t
DLH
L/RCLK Hold
10
ns
From BCLK rising
t
DDS
SDATA Setup
10
ns
To BCLK rising
t
DDH
SDATA Hold
15
ns
From BCLK rising
TDM MODE MASTER
t
TMBD
BCLKTDM Delay
20
ns
From MCLK rising
t
TMFSD
FSTDM Delay
10
ns
From BCLKTDM rising
t
TMDDS
SDIN1 Setup
15
ns
To BCLKTDM falling
t
TMDDH
SDIN1 Hold
15
ns
From BCLKTDM falling
TDM MODE SLAVE
f
TSB
BCLKTDM Frequency
256 f
S
t
TSBCH
BCLKTDM High
20
ns
t
TSBCL
BCLKTDM Low
20
ns
t
TSFS
FSTDM Setup
10
ns
To BCLKTDM falling
t
TSFH
FSTDM Hold
10
ns
From BCLKTDM falling
t
TSDDS
SDIN1 Setup
15
ns
To BCLKTDM falling
t
TSDDH
SDIN1 Hold
15
ns
From BCLKTDM falling
AUXILIARY INTERFACE
t
AXLRD
L/RCLK Delay
10
ns
From BCLK falling
t
AXDD
Data Delay
10
ns
From BCLK falling
t
AXBD
AUXBCLK Delay
20
ns
From MCLK rising
*MCLK symmetry must be better than 60:40 or 40:60.
Specifications subject to change without notice.
(Guaranteed over 40 C to +85 C, AV
DD
= DV
DD
= 5 V
10%)
REV. 0
4
AD1833A
MCLK
t
MH
PD/RST
t
ML
t
PDR
Figure 1. MCLK and
RESET Timing
CLATCH
CCLK
CIN
D0
D15
D14
D8
t
CCH
t
CCL
D9
t
CDS
t
CDH
t
CLS
t
CLH
t
CCP
Figure 2. SPI Port Timing
BCLK
L/RCLK
SDATA
LEFT-JUSTIFIED
MODE
SDATA
RIGHT-JUSTIFIED
MODE
LSB
SDATA
I
2
S MODE
MSB
MSB-1
MSB
MSB
t
DBH
t
DBL
t
DLS
t
DDS
t
DDH
t
DDS
t
DLH
t
DDH
t
DDS
t
DDS
t
DDH
t
DDH
Figure 3. Serial Port Timing
MSB
t
TMBD
t
TMFSD
t
TMDDS
t
TMDDH
MCLK
BCLKTDM
FSTDM
SDIN1
t
TSBCL
t
TSBCH
t
TSDDH
t
TSDDS
t
TSFS
t
TSFH
Figure 4. TDM Master and Slave Mode Timing
REV. 0
AD1833A
5
ABSOLUTE MAXIMUM RATINGS
*
(T
A
= 25
C, unless otherwise noted.)
AV
DD
, DV
DDX
to AGND, DGND . . . . . . . . 0.3 V to +6.5 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . 0.3 V to +0.3 V
Digital I/O Voltage to DGND . . . . . 0.3 V to DV
DD2
+ 0.3 V
Analog I/O Voltage to AGND . . . . . . 0.3 V to AV
DD
+ 0.3 V
Operating Temperature Range
Industrial (A Version) . . . . . . . . . . . . . . . 40
C to +85C
Storage Temperature Range . . . . . . . . . . . . 65
C to +150C
Maximum Junction Temperature . . . . . . . . . . . . . . . . 150
C
LQFP,
q
JA
Thermal Impedance . . . . . . . . . . . . . . . . . 91
C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215
C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.
MSB
MCLK
AUXBCLK
AUXL/
RCLK
AUX DATA
t
AXDD
t
AXLRD
t
AXBD
Figure 5. Auxiliary Interface Timing
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
AD1833AAST
40
C to +85C
Low Profile Quad Flat Package
ST-48
AD1833ACST
40
C to +85C
Low Profile Quad Flat Package
ST-48
EVAL-AD1833AEB
Evaluation Board
AD1833AAST-REEL
40
C to +85C
Low Profile Quad Flat Package
ST-48
AD1833ACST-REEL
40
C to +85C
Low Profile Quad Flat Package
ST-48
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate
on the human body and test equipment and can discharge without detection. Although the AD1833A
features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to
high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid
performance degradation or loss of functionality.