ChipFind - документация

Электронный компонент: AD1835AS

Скачать:  PDF   ZIP

Document Outline

REV. PrA
Preliminary Technical Data
PRELIMINARY TECHNICAL DATA
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
a
AD1835
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
Analog Devices, Inc., 2002
2 ADC, 8 DAC,
96 kHz, 24-Bit -
Codec
FEATURES
5 V Stereo Audio System with 3.3 V Tolerant Digital
Interface
Supports up to 96 kHz Sample Rates
192 kHz Sample Rate Available on One DAC
Supports 16-/20-/24-Bit Word Lengths
Multibit Sigma-Delta Modulators with
"Perfect Differential Linearity Restoration" for
Reduced Idle Tones and Noise Floor
Data Directed Scrambling DACs--Least
Sensitive to Jitter
Differential Output for Optimum Performance
ADCs: 92 dB THD + N, 100 dB SNR,
and Dynamic Range
DACs: 95 dB THD + N, 110 dB SNR,
and Dynamic Range
On-Chip Volume Controls per Channel with
1024-Step Linear Scale
DAC and ADC Software Controllable Clickless Mutes
Digital De-Emphasis Processing
Supports 256 f
S
, 512 f
S,
and 768 f
S
Master
Mode Clocks
Power-Down Mode Plus Soft Power-Down Mode
Flexible Serial Data Port with Right-Justified, Left-
Justified, I
2
S-Compatible, and DSP Serial Port Modes
TDM Interface Mode Supports 8 In/8 Out Using a
Single SHARC
SPORT
52-Lead MQFP Plastic Package
APPLICATIONS
DVD Video and Audio Players
Home Theater Systems
Automotive Audio Systems
Audio/Visual Receivers
Digital Audio Effects Processors
FUNCTIONAL BLOCK DIAGRAM
OUTLP1
OUTLN1
CONTROL PORT
CLOCK
FILTD
FILTR
ADCLP
ADCLN
ADCRP
ADCRN
DLRCLK
DBCLK
DSDATA1
DSDATA2
DSDATA3
DSDATA4
MCLK
ASDATA
ABCLK
ALRCLK
ODVDD
DVDD
AVDD
AVDD
DVDD
AGND
AGND
AGND
AGND
DGND
DGND
CIN
CLATCH
CCLK
COUT
DIGITAL
FILTER
PD/RST M/S
-
ADC
V
REF
VOLUME
SERIAL DATA
I/O PORT
DIGITAL
FILTER
OUTRP1
OUTRN1
VOLUME
OUTLP2
OUTLN2
VOLUME
DIGITAL
FILTER
OUTRP2
OUTRN2
VOLUME
OUTLP3
OUTLN3
VOLUME
DIGITAL
FILTER
OUTRP3
OUTRN3
VOLUME
OUTLP4
OUTLN4
VOLUME
DIGITAL
FILTER
OUTRP4
OUTRN4
VOLUME
DIGITAL
FILTER
-
ADC
-
DAC
-
DAC
-
DAC
-
DAC
PRODUCT OVERVIEW
The AD1835 is a high-performance, single-chip codec featuring
four stereo DACs and one stereo ADC. Each DAC comprises a
high-performance digital interpolation filter, a multibit sigma-
delta modulator featuring Analog Devices' patented technology,
(Continued on Page 11 )
SHARC is a registered trademark of Analog Devices, Inc.
REV. PrA
PRELIMINARY TECHNICAL DATA
2
AD1835SPECIFICATIONS
TEST CONDITIONS
Supply Voltages (AV
DD
, DV
DD
) . . . . . . . . . . . . . . . . . . . . . . . . 5.0 V
Ambient Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
C
Input Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.288 MHz, (256
f
S
Mode)
ADC Input Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0078125 kHz, 1 dBFS (Full Scale)
DAC Input Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0078125 kHz, 0 dBFS (Full Scale)
Input Sample Rate (f
S
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 kHz
Measurement Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Hz to 20 kHz
Word Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Bits
Load Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 pF
Load Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 k
Performance of all channels is identical (exclusive of the Interchannel Gain Mismatch and Interchannel Phase Deviation
specifications).
Parameter
Min
Typ
Max
Unit
ANALOG-TO-DIGITAL CONVERTERS
ADC Resolution
24
Bits
Dynamic Range (20 Hz to 20 kHz, 60 dB Input)
No Filter
100
103
dB
A-Weighted
101
105
dB
Total Harmonic Distortion + Noise (THD + N)
93
88.5
dB
Interchannel Isolation
100
dB
Interchannel Gain Mismatch
0.01
dB
Analog Inputs
Differential Input Range (
Full Scale)
2.828
+2.828
V
Common-Mode Input Volts
2.25
V
Input Impedance
4
k
Input Capacitance
15
pF
V
REF
2.25
V
DC Accuracy
Gain Error
+5
%
Gain Drift
TBD
ppm/C
Crosstalk (EIAJ Method)
TBD
dB
DIGITAL-TO-ANALOG CONVERTERS
DAC Resolution
Dynamic Range (20 Hz to 20 kHz, 60 dBFS Input)
No Filter
103
105
With A-Weighted Filter
105
108
dB
Total Harmonic Distortion + Noise
95
90
dB
Interchannel Isolation
100
dB
DC Accuracy
Gain Error
4.0
%
Interchannel Gain Mismatch
0.01
%
Gain Drift
150
ppm/
C
Interchannel Crosstalk (EIAJ method)
120
dB
Interchannel Phase Deviation
0.1
Degrees
Volume Control Step Size (1023 Linear Steps)
0.098
%
Volume Control Range (Max Attenuation)
60
dB
Mute Attenuation
100
dB
De-Emphasis Gain Error
0.1
dB
Full-Scale Output Voltage at Each Pin (Single-Ended)
1.0 (2.8)
Vrms (V p-p)
Output Resistance at Each Pin
115
Common-Mode Output Volts
2.25
V
ADC DECIMATION FILTER, 48 kHz
*
Pass Band
20
kHz
Pass-Band Ripple
0.01
dB
Stop Band
24
kHz
Stop-Band Attenuation
120
dB
Group Delay
910
s
REV. PrA
PRELIMINARY TECHNICAL DATA
3
AD1835
Parameter
Min
Typ
Max
Unit
ADC DECIMATION FILTER, 96 kHz
*
Pass Band
40
kHz
Pass-Band Ripple
0.01
dB
Stop Band
48
kHz
Stop-Band Attenuation
120
dB
Group Delay
460
s
DAC INTERPOLATION FILTER, 48 kHz
*
Pass Band
20
kHz
Pass-Band Ripple
0.01
dB
Stop Band
24
kHz
Stop-Band Attenuation
55
dB
Group Delay
340
s
DAC INTERPOLATION FILTER, 96 kHz
*
Pass Band
37.5
kHz
Pass-Band Ripple
0.01
dB
Stop Band
55.034
kHz
Stop-Band Attenuation
55
dB
Group Delay
160
s
DAC INTERPOLATION FILTER, 192 kHz
*
Pass Band
89.954
kHz
Pass-Band Ripple
0.01
dB
Stop Band
104.85
kHz
Stop-Band Attenuation
80
dB
Group Delay
110
s
DIGITAL I/O
Input Voltage High
2.4
V
Input Voltage Low
0.8
V
Output Voltage High
ODV
DD
0.4
V
Output Voltage Low
0.4
V
Leakage Current
10
A
POWER SUPPLIES
Supply Voltage (AV
DD
and DV
DD
)
4.5
5.0
5.5
V
Supply Voltage (OV
DD
)
3.0
DV
DD
V
Supply Current I
ANALOG
84
95
mA
Supply Current I
ANALOG,
Power-Down
55
67
mA
Supply Current I
DIGITAL
64
72
mA
Supply Current I
DIGITAL,
Power-Down
1
4
mA
Dissipation
Operation, Both Supplies
740
mW
Operation, Analog Supply
420
mW
Operation, Digital Supply
320
mW
Power-Down, Both Supplies
280
mW
Power Supply Rejection Ratio
1 kHz, 300 mV p-p Signal at Analog Supply Pins
60
dB
20 kHz, 300 mV p-p Signal at Analog Supply Pins
50
dB
*Guaranteed by design.
Specifications subject to change without notice.
REV. PrA
PRELIMINARY TECHNICAL DATA
4
AD1835SPECIFICATIONS
TIMING
Parameter
Min
Max
Unit
Comments
MASTER CLOCK AND RESET
t
MH
MCLK High
15
ns
t
ML
MCLK Low
15
ns
t
PDR
PD/RST Low
20
ns
SPI PORT
t
CCH
CCLK High
40
ns
t
CCL
CCLK Low
40
ns
t
CCP
CCLK Period
80
ns
t
CDS
CDATA Setup
10
ns
To CCLK Rising
t
CDH
CDATA Hold
10
ns
From CCLK Rising
t
CLS
CLATCH Setup
10
ns
To CCLK Rising
t
CLH
CLATCH Hold
10
ns
From CCLK Rising
t
COE
COUT Enable
15
ns
From CLATCH Falling
t
COD
COUT Delay
20
ns
From CCLK Falling
t
COTS
COUT Three-State
25
ns
From CLATCH Rising
DAC SERIAL PORT
Normal Mode (Slave)
t
DBH
DBCLK High
60
ns
t
DBL
DBCLK Low
60
ns
f
DB
DBCLK Frequency
64 f
S
t
DLS
DLRCLK Setup
10
ns
To DBCLK Rising
t
DLH
DLRCLK Hold
10
ns
From DBCLK Rising
t
DDS
DSDATA Setup
10
ns
To DBCLK Rising
t
DDH
DSDATA Hold
10
ns
From DBCLK Rising
Packed 256 Modes (Slave)
t
DBH
DBCLK High
15
ns
t
DBL
DBCLK Low
15
ns
f
DB
DBCLK Frequency
256 f
S
t
DLS
DLRCLK Setup
10
ns
To DBCLK Rising
t
DLH
DLRCLK Hold
5
ns
From DBCLK Rising
t
DDS
DSDATA Setup
10
ns
To DBCLK Rising
t
DDH
DSDATA Hold
10
ns
From DBCLK Rising
ADC SERIAL PORT
Normal Mode (Master)
t
ABD
ABCLK Delay
25
ns
From MCLK Rising Edge
t
ALD
ALRCLK Delay Low
5
ns
From ABCLK Falling Edge
t
ABDD
ASDATA Delay
10
ns
From ABCLK Falling Edge
Normal Mode (Slave)
t
ABH
ABCLK High
60
ns
t
ABL
ABCLK Low
60
ns
f
AB
ABCLK Frequency
64 f
S
t
ALS
ALRCLK Setup
5
ns
To ABCLK Rising
t
ALH
ALRCLK Hold
15
ns
From ABCLK Rising
Packed 256 Mode (Master)
t
PABD
ABCLK Delay
20
ns
From MCLK Rising Edge
t
PALD
LRCLK Delay
5
ns
From ABCLK Falling Edge
t
PABDD
ASDATA Delay
10
ns
From ABCLK Falling Edge
REV. PrA
PRELIMINARY TECHNICAL DATA
5
AD1835
Parameter
Min
Max
Unit
Comments
TDM256 MODE (Master)
t
TBD
BCLK Delay
20
ns
From MCLK Rising
t
FSD
FSTDM Delay
5
ns
From BCLK Rising
t
TABDD
ASDATA Delay
10
ns
From BCLK Rising
t
TDDS
DSDATA1 Setup
15
ns
To BCLK Falling
t
TDDH
DSDATA1 Hold
15
ns
From BCLK Falling
TDM256 MODE (Slave)
f
AB
BCLK Frequency
256
f
S
ns
t
TBCH
BCLK High
min
ns
t
TBCL
BCLK Low
min
ns
t
TFS
FSTDM Setup
min
ns
To BCLK Falling
t
TFH
FSTDM Hold
min
ns
From BCLK Falling
t
ABDD
ASDATA Delay
max
ns
From BCLK Rising
t
TDDS
DSDATA1 Setup
min
ns
To BCLK Falling
t
TDDH
DSDATA1 Hold
min
ns
From BCLK Falling
TDM512 MODE (Master)
t
ABDH
BCLK Delay
40
ns
From MCLK Rising
t
FSD
FSTDM Delay
5
ns
From BCLK Rising
t
TABDD
ASDATA Delay
10
ns
From BCLK Rising
t
TDDS
DSDATA1 Setup
15
ns
To BCLK Falling
t
TDDH
DSDATA1 Hold
15
ns
From BCLK Falling
TDM512 MODE (Slave)
f
AB
BCLK Frequency
512
f
S
t
TBCH
BCLK High
20
ns
t
TBCL
BCLK Low
20
ns
t
TFS
FSTDM Setup
5
ns
To BCLK Rising
t
TFH
FSTDM Hold
10
ns
From BCLK Rising
t
TABDD
ASDATA Delay
20
ns
From BCLK Rising
t
TDDS
DSDATA1 Setup
5
ns
To BCLK Rising
t
TDDH
DSDATA1 Hold
10
ns
From BCLK Rising
AUXILIARY INTERFACE
t
AXDS
AAUXDATA Setup
10
ns
To AUXBCLK Rising
t
AXDH
AAUXDATA Hold
10
ns
From AUXBCLK Rising
f
ABP
AUXBCLK Frequency
64 f
S
Slave Mode
t
AXBH
AUXBCLK High
15
ns
t
AXBL
AUXBCLK Low
15
ns
t
AXLS
AUXLRCLK Setup
10
ns
To AUXBCLK Rising
t
AXLH
AUXLRCLK Hold
10
ns
From AUXBCLK Rising
Master Mode
t
AUXLRCLK
AUXLRCLK Delay
5
ns
From AUXBCLK Falling
t
AUXBCLK
AUXBCLK Delay
15
ns
From MCLK Rising Edge
Specifications subject to change without notice.