AD1855*

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700

World Wide Web Site: http://www.analog.com

Fax: 781/326-8703

© Analog Devices, Inc., 2000

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

REV. B

Stereo, 96 kHz, Multibit

DAC

FUNCTIONAL BLOCK DIAGRAM

ATTEN/

MUTE

ATTEN/

MUTE

SERIAL

DATA

INTERFACE

INTERPOLATOR

MULTIBIT SIGMA-

DELTA MODULATOR

SERIAL CONTROL

INTERFACE

CLOCK

CIRCUIT

OUTPUT
BUFFER

DAC

MULTIBIT SIGMA-

DELTA MODULATOR

VOLTAGE

REFERENCE

VOLUME

MUTE

CONTROL DATA

INPUT

DIGITAL
SUPPLY

CLOCK

96/

48F

CLOCK

ANALOG
OUTPUTS

ZERO
FLAG

ANALOG

SUPPLY

DE-EMPHASIS

MUTE

PD/RST

SERIAL

MODE

16-/18-/20-/24-BIT

DIGITAL

DATA INPUT

AD1855

INTERPOLATOR

384/

256

X2MCLK

FEATURES
5 V Stereo Audio DAC System
Accepts 16-/18-/20-/24-Bit Data
Supports 24 Bits and 96 kHz Sample Rate
Multibit Sigma-Delta Modulator with "Perfect Differen-

tial Linearity Restoration" for Reduced Idle Tones
and Noise Floor

Data Directed Scrambling DAC--Least Sensitive to

Jitter

Differential Output for Optimum Performance
113 dB Signal-to-Noise and Dynamic

Range at 48 kHz

Sample Rate

110 dB Signal-to-Noise and Dynamic Range at 96 kHz

Sample Rate

97 dB THD+N
On-Chip Volume Control with 1024 Steps
Hardware and Software Controllable Clickless Mute
Zero Input Flag Outputs for Left and Right Channels
Digital De-Emphasis Processing
Supports 128, 256, 384, and 512 F

Master Mode

Clock

Switchable Clock Doubler
Power-Down Mode Plus Soft Power-Down Mode
Flexible Serial Data Port with Right-Justified, Left-

Justified, I

S-Compatible and DSP Serial Port Modes

28-Lead SSOP Plastic Package

APPLICATIONS
DVD, CD, Set-Top Boxes, Home Theater Systems, Auto-

motive Audio Systems, Computer Multimedia Prod-
ucts, Sampling Musical Keyboards, Digital Mixing
Consoles, Digital Audio Effects Processors

*Patents Pending.

PRODUCT OVERVIEW

The AD1855 is a high performance, single-chip stereo, audio
DAC delivering 113 dB Dynamic Range and SNR (A-weighted--
not muted) at 48 kHz sample rate. It is comprised of a multibit
sigma-delta modulator with dither, continuous time analog
filters and analog output drive circuitry. Other features include
an on-chip stereo attenuator and mute, programmed through an
SPI-compatible serial control port. The AD1855 is fully com-
patible with current DVD formats, including 96 kHz sample
frequency and 24 bits. It is also backwards compatible by sup-
porting 50

µs/15 µs digital de-emphasis intended for "redbook"

44.1 kHz sample frequency playback from compact discs.

The AD1855 has a very simple but very flexible serial data input
port that allows for glueless interconnection to a variety of ADCs,
DSP chips, AES/EBU receivers and sample rate converters.
The AD1855 can be configured in left-justified, I

S, right-

justified, or DSP serial port compatible modes. The AD1855
accepts 16-/18-/20-/24-bit serial audio data in MSB first, twos-
complement format. A power-down mode is offered to mini-
mize power consumption when the device is inactive. The
AD1855 operates from a single +5 V power supply. It is fabri-
cated on a single monolithic integrated circuit and housed in a
28-lead SSOP package for operation over the temperature range
0

°C to +70°C.

REV. B

AD1855SPECIFICATIONS

TEST CONDITIONS UNLESS OTHERWISE NOTED

Supply Voltages (AV

, DV

)

+5.0 V

Ambient Temperature

+25

°C

Input Clock

24.576 MHz (512

× F

Mode)

Input Signal

1.0013 kHz
0.5 dB Full Scale

Input Sample Rate

48 kHz

Measurement Bandwidth

20 Hz to 20 kHz

Word Width

20 Bits

Load Impedance

6 k

Input Voltage HI

4.0 V

Input Voltage LO

0.8 V

Performance of right and left channels are identical (exclusive of the Interchannel Gain Mismatch and Interchannel Phase Deviation specifications).

ANALOG PERFORMANCE

Min

Typ

Max

Units

Resolution

Bits

Dynamic Range (20 Hz to 20 kHz, 60 dB Input)

No Filter

110

With A-Weighted Filter

108

113

Total Harmonic Distortion + Noise

0.0014

Analog Outputs

Differential Output Range (

±Full Scale)

5.6

V p-p

Output Impedance at Each Output Pin

200

Output Capacitance at Each Output Pin

CMOUT

2.5

Gain Error

5.0

±3.0

+5.0

Interchannel Gain Mismatch

0.15

+0.15

Gain Drift

150

300

ppm/

°C

Interchannel Crosstalk (EIAJ Method)

120

Interchannel Phase Deviation

±0.1

Degrees

Mute Attenuation

120

De-Emphasis Gain Error

±0.1

DIGITAL TIMING (Guaranteed over 0 C to +70 C, AV

= DV

= +5.0 V 10%)

Min

Max

Units

DMP

MCLK Period (512

Mode)

DMP

MCLK Period (384 F

Mode)

DMP

MCLK Period (256 F

Mode)

DML

MCLK LO Pulsewidth (All Mode)

0.4

× t

DMP

DMH

MCLK HI Pulsewidth (All Mode)

0.4

× t

DMP

DBH

BCLK HI Pulsewidth

DBL

BCLK LO Pulsewidth

DBP

BCLK Period

140

DLS

RCLK Setup

DLH

RCLK Hold (DSP Serial Port Mode Only)

DDS

SDATA Setup

DDH

SDATA Hold

PDRP

PD/RST LO Pulsewidth

4 MCLK Periods

REV. B

AD1855

DIGITAL I/O (0 C to +70 C)

Min

Typ

Max

Units

Input Voltage HI (V

)

2.4

Input Voltage LO (V

)

1.0

High Level Output Voltage (V

) I

= 1 mA

2.0

Low Level Output Voltage (V

) I

= 1 mA

0.4

Input Leakage (I

@ V

= 5 V)

µA

Input Leakage (I

@ V

= 0 V)

µA

Input Capacitance

POWER

Min

Typ

Max

Units

Supplies

Voltage, Analog and Digital

4.5

5.50

Analog Current

Analog Current--Power-Down

Digital Current

Digital Current--Power-Down

2.5

Dissipation

Operation--Both Supplies

250

Operation--Analog Supply

150

Operation--Digital Supply

100

Power-Down--Both Supplies

190

Power Supply Rejection Ratio

1 kHz 300 mV p-p Signal at Analog Supply Pins

20 kHz 300 mV p-p Signal at Analog Supply Pins

TEMPERATURE RANGE

Min

Typ

Max

Units

Specifications Guaranteed

°C

Functionality Guaranteed

°C

Storage

+125

°C

DIGITAL FILTER CHARACTERISTICS

Min

Typ

Max

Units

Passband Ripple

±0.04

Stopband Attenuation

Passband

0.448

Stopband

0.552

Group Delay

32, 44.1, 48 kHz (8

× Interpolation Mode)

106/F

sec

96 kHz (4

× Interpolation Mode)

53/F

sec

Group Delay Variation

µs

Specifications subject to change without notice.

AD1855

REV. B

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD1855 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS*

Min

Max

Units

to DGND

0.3

to AGND

0.3

Digital Inputs

DGND 0.3

+ 0.3

Analog Outputs

AGND 0.3

+ 0.3

AGND to DGND

0.3

Reference Voltage

(AV

+ 0.3)/2

Soldering

+300

°C

sec

*Stresses greater than those listed under Absolute Maximum Ratings may cause

permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

PACKAGE CHARACTERISTICS

Min

Typ

Max

Units

(Thermal Resistance

[Junction-to-Ambient])

109

°C/W

(Thermal Resistance

[Junction-to-Case])

°C/W

ORDERING GUIDE

Model

Temperature

Package Description

Package Options

AD1855JRS

°C to +70°C

28-Lead Shrink Small Outline

RS-28

AD1855JRSRL

°C to +70°C

28-Lead Shrink Small Outline

RS-28 on 13

Reels

PIN CONFIGURATION

TOP VIEW

(Not to Scale)

AD1855

FILTR

OUTR

OUTR+

AGND

96/

DEEMP

ZEROR

DGND

MCLK

CLATCH

CCLK

X2MCLK

384/

256

CDATA

AGND

OUTL

OUTL+

AVDD

FILTB

IDPM1

IDPM0

DVDD

SDATA

BCLK

RCLK

ZEROL

MUTE

PD/RST

AD1855

REV. B

PIN FUNCTION DESCRIPTIONS

Pin

Input/Output

Pin Name

Description

DGND

Digital Ground.

MCLK

Master Clock Input. Connect to an external clock source at either 128, 256,
384 or 512 F

, based on sample rate and clock doubler mode.

CLATCH

Latch input for control data. This input is rising-edge sensitive.

CCLK

Control clock input for control data. Control input data must be valid on the
rising edge of CCLK. CCLK may be continuous or gated.

CDATA

Serial control input, MSB first, containing 16 bits of unsigned data per
channel. Used for specifying channel specific attenuation and mute.

384/

256

Selects the master clock mode as either 384 times the intended sample fre-
quency (HI) or 256 times the intended sample frequency (LO). The state of
this input should be hardwired to logic HI or logic LO, or may be changed
while the AD1855 is in power-down/reset. It must not be changed while the
AD1855 is operational.

X2MCLK

Selects internal clock doubler (LO) or internal clock = MCLK (HI).

ZEROR

Right Channel Zero Flag Output. This pin goes HI when Right Channel has
no signal input for more than 1024 LR Clock Cycles.

DEEMP

De-Emphasis. Digital de-emphasis is enabled when this input signal is HI.
This is used to impose a 50

µs/15 µs response characteristic on the output

audio spectrum at an assumed 44.1 kHz sample rate.

96/

Selects 48 kHz (LO) or 96 kHz Sample Frequency Control.

11, 15

AGND

Analog Ground.

OUTR+

Right Channel Positive line level analog output.

OUTR

Right Channel Negative line level analog output.

FILTR

Voltage Reference Filter Capacitor Connection. Bypass and decouple the
voltage reference with parallel 10

µF and 0.1 µF capacitors to the AGND.

OUTL

Left Channel Negative line level analog output.

OUTL+

Left Channel Positive line level analog output.

AVDD

Analog Power Supply. Connect to analog +5 V supply.

FILTB

Filter Capacitor connection, connect 10

µF capacitor to AGND.

IDPM1

Input serial data port mode control one. With IDPM0, defines one of four
serial modes.

IDPM0

Input serial data port mode control zero. With IDPM1, defines one of four
serial modes.

ZEROL

Left Channel Zero Flag output. This pin goes HI when Left Channel has no
signal input for more than 1024 LR Clock Cycles.

MUTE

Mute. Assert HI to mute both stereo analog outputs. Deassert LO for nor-
mal operation.

PD/RST

Power-Down/Reset. The AD1855 is placed in a low power consumption
mode when this pin is held LO. The AD1855 is reset on the rising edge of
this signal. The serial control port registers are reset to the default values.
Connect HI for normal operation. A reset should always be performed at
power-on.

RCLK

Left/

Right clock input for input data. Must run continuously.

BCLK

Bit clock input for input data. Need not run continuously; may be gated or
used in a burst fashion.

SDATA

Serial input, MSB first, containing two channels of 16, 18, 20, and 24 bits of
twos complement data per channel.

DVDD

Digital Power Supply Connect to digital +5 V supply.

AD1855

REV. B

OPERATING FEATURES
Serial Data Input Port

The AD1855's flexible serial data input port accepts data in
twos-complement, MSB-first format. The left channel data field
always precedes the right channel data field. The input data
consists of either 16, 18, 20 or 24 bits, as established by the
mode select pins (IDPM0 Pin 21 and IDPM1 Pin 20) or the
mode select bits (Data 15 and 14) in the control register
through the SPI (Serial Peripheral Interface) control port. Nei-
ther the pins nor the SPI controls has preference; to ensure
proper control the selection not being used should be tied LO.
Therefore, when the SPI bits are used to control Serial Data
Input Format, Pins 20 and 21 should be tied LO. Similarly,
when the Pins are to be used to select the Data Format, the SPI
bits should be set to Zeros. When the SPI Control Port is not
being used, the SPI Pins (3, 4 and 5) should be tied LO.

Serial Data Input Mode

The AD1855 uses two multiplexed input pins to control the
mode configuration of the input data port mode as follows:

Table I. Serial Data Input Modes

IDPM1

IDPM0

(Pin 20)

(Pin 21)

Serial Data Input Format

Right Justified (16 Bits Only)

S-Compatible

Left Justified

DSP

Figure 1 shows the right-justified mode. L/

RCLK is HI for the

left channel, LO for the right channel. Data is valid on the
rising edge of BCLK. The MSB is delayed 16 bit clock periods
from an L/

RCLK transition, so that when there are 64 BCLK

periods per L/

RCLK period, the LSB of the data will be right

justified to the next L/

RCLK transition. The right-justified

mode can only be used with 16-bit inputs.

Figure 2 shows the I

S-justified mode. L/

RCLK is LO for the

left channel and HI for the right channel. Data is valid on the
rising edge of BCLK. The MSB is left justified to an L/

RCLK

transition but with a single BCLK period delay. The I

S-justified

mode can be used with 16-/18-/20- or 24-bit inputs.

Figure 3 shows the left-justified mode. L/

RCLK is HI for the

left channel, and LO for the right channel. Data is valid on the
rising edge of BLCK. The MSB is left justified to an L/

RCLK

transition, with no MSB delay. The left-justified mode can be
used with 16-/18-/20- or 24-bit inputs.

Figure 4 shows the left-justified DSP serial port style mode.
L/

RCLK must pulse HI for at least one bit clock period before

the MSB of the left channel is valid, and L/

RCLK must pulse

HI again for at least one bit clock period before the MSB of the
right channel is valid. Data is valid on the falling edge of BCLK.
The left-justified DSP serial port style mode can be used with
16-/18-/20- or 24-bit inputs.

Note that in this mode, it is the responsibility of the DSP to
ensure that the left data is transmitted with the first L/

RCLK

pulse, and that synchronism is maintained from that point
forward.

The AD1855 is capable of a 32

× F

BCLK frequency "packed

mode" where the MSB is left justified to an L/

RCLK transition,

and the LSB is right justified to an L/

RCLK transition. L/RCLK

is HI for the left channel and LO for the right channel. Data is
valid on the rising edge of BLCK. Packed mode can be used
when the AD1855 is programmed in right- or left-justified
mode. Packed mode is shown is Figure 5.

Table II. Frequency Mode Settings

96/

MCLK

X2MCLK

384/

256

Note

× Interpolation Mode

Normal, 32 kHz48 kHz

256

× F

384

× F

512

× F

Not Allowed

× Interpolation Mode

Double F

(96 kHz)

128

× F

(384/2)

× F

256

× F

Not Allowed

AD1855

REV. B

SDATA

INPUT

LSB

MSB2

MSB1

LSB+2 LSB+1

MSB2

MSB1

MSB

LSB+2

LSB+1

LSB

BCLK

INPUT

RCLK

INPUT

LEFT CHANNEL

RIGHT CHANNEL

MSB

Figure 1. Right-Justified Mode

LEFT CHANNEL

RIGHT CHANNEL

MSB2

MSB1

LSB+2

LSB+1

LSB

MSB2

MSB1

MSB

LSB+2

LSB+1

LSB

MSB

RCLK

INPUT

BCLK

INPUT

SDATA

INPUT

MSB

Figure 2. I

S-Justified Mode

MSB2

MSB1

LSB+2

LSB+1

LSB

MSB2

MSB1

MSB

LSB+2

LSB+1

LSB

MSB1

MSB

RCLK

INPUT

BCLK

INPUT

SDATA

INPUT

LEFT CHANNEL

RIGHT CHANNEL

MSB

Figure 3. Left-Justified Mode

SDATA

INPUT

MSB1

LSB+2

LSB+1

LSB

MSB1

LSB+2

LSB+1

LSB

MSB

MSB1

MSB

RCLK

INPUT

LEFT CHANNEL

RIGHT CHANNEL

BCLK

INPUT

MSB

Figure 4. Left-Justified DSP Mode

RCLK

INPUT

LEFT CHANNEL

RIGHT CHANNEL

BCLK

INPUT

SDATA

INPUT

LSB

MSB1

MSB2

LSB+2

LSB+1

LSB

MSB

MSB1

MSB2

LSB+2

LSB+1

LSB

MSB

MSB1

MSB

Figure 5. 32

× F

Packed Mode

AD1855

REV. B

Serial Control Port

The AD1855 serial control port is SPI compatible. SPI (Serial
Peripheral Interface) is an industry standard serial port protocol.
The write-only serial control port gives the user access to: select
input mode, soft power-down control, soft de-emphasis, channel-
specific attenuation and mute (both channels at once). The
AD1855 serial control port consists of three signals, control
clock CCLK (Pin 4), control data CDATA (Pin 5), and control
latch CLATCH (Pin 3). The control data input must be valid
on the control clock rising edge, and the control clock must
make a LO to HI transition when there is valid data. The con-
trol latch must make a LO to HI transition after the LSB has
been clocked into the AD1855, while the control clock is inac-
tive. The timing relation between these signals is shown in Fig-
ure 6. The control bits are assigned as in Table III.

Digital Timing

Min

Unit

CCH

CCLK HI Pulsewidth

40 (Burst Mode)

CCLK LO Pulsewidth

40 (Burst Mode)

CCP

CCLK Period

80 (Burst Mode)

CCSU

CCLK Setup Time

100

CSU

CDATA Setup Time

CHD

CDATA Hold Time

CLL

CLATCH LO Pulsewidth

CLH

CLATCH HI Pulsewidth

130

CLSU

CLATCH HI Setup

130

Table III. Serial Control Bit Definitions

MSB

LSB

Data 15 Data 14

Data 13 Data 12

Data 11

Data 10 Data 9

Data 8

Data 7

Data 6

Data 5

Data 4

Data 3

Data 2

Data 1

Data 0

IDPM1

IDPM0

Soft

1/Mute

1/Right

Volume Volume

Volume

Volume Volume

Input

Power-

De-

0/Normal

0/Left

Control Control

Control

Control Control

Mode1

Mode0

Down

Emphasis (Nonmute)

Data

Select

CLL

CLSU

CCH

CSU

CCL

CHD

D15

D14

CDATA

CCLK

CLATCH

CLH

CCSU

CCP

Figure 6. Serial Control Port Timing

The serial control port is byte oriented. The data is MSB first,
and is unsigned. There is one control register for the left chan-
nel or the right channel, as distinguished by bit Data 10. For
power-up and reset, the default settings are: Data 11 the Mute
control bit, reset default state is LO, which is the normal
(nonmuted) setting. Data 10 is LO, the Volume 9 through Vol-
ume 0 control bits have a reset default value of 11 1111 1111,
which is an attenuation of 0.0 dB (i.e., full scale, no attenua-
tion). The intent with these reset defaults is to enable AD1855
applications without requiring the use of the serial control port.
For those users who do not use the serial control port, it is still
possible to mute the AD1855 output by using the MUTE (Pin
23) signal.

Note that the serial control port timing is asynchronous to the
serial data port timing. Changes made to the attenuator level
will be updated on the next edge of the L/

RCLK after the

CLATCH write pulse as shown in Figure 7.

Mute

The AD1855 offers two methods of muting the analog output.
By asserting the MUTE (Pin 23) signal HI, both the left and
right channel are muted. As an alternative, the user can assert
the mute bit in the serial control register (Data 11) HI. The
AD1855 has been designed to minimize pops and clicks when
muting and unmuting the device.

AD1855

REV. B

CLATCH

CCLK

100

120

140

160

180

CDATA

>130ns

TIME ns

Figure 7. SPI Port Continuous CCLK Mode

CLATCH

CCLK

CDATA

TIME ns

200

400

600

800

1000

1200

1400

1600

1800

Figure 8. SPI Port Burst Mode

SPI Port Modes

The SPI port can be used in either of two modes, Burst Mode,
or Continuous CCLK Mode, as described below:

Continuous CCLK Mode

In this mode, the maximum CCLK frequency is 3 MHz. The
CCLK can run continuously between transactions. Please note
that the Low-to-Hi transition of the CLATCH with respect to
the rising edge of CCLK must be at least 130 ns, as shown in
Figure 7.

Burst Mode

To operate with SPI CCLK frequencies up to 12.288 MHz, the
SPI port can be operated in Burst Mode. This means that when
CLATCH is high, CCLK cannot be HI, as shown in Figure 8.

AD1855

REV. B

DLS

BCLK

RCLK

SDATA

LEFT-JUSTIFIED

MODE

SDATA

RIGHT-JUSTIFIED

MODE

LSB

SDATA

S-JUSTIFIED

MODE

DBH

DBP

DBL

DDS

MSB

MSB-1

DDH

DDS

MSB

DDH

DDS

DDH

MSB

Figure 9. Serial Data Port Timing

BCLK

RCLK

SDATA

LEFT-JUSTIFIED

DSP SERIAL

PORT STYLE MODE

MSB-1

DBH

DBP

DBL

DLS

DLH

DDS

DDH

MSB

Figure 10. Serial Data Port TimingDSP Serial Port Style Mode

PD/RST

MCLK

PDRP

DMP

DMH

DML

Figure 11.

Power-Down/Reset Timing

Timing Diagrams

The serial data port timing is shown in Figures 9 and 10. The
minimum bit clock HI pulsewidth is t

DBH

and the minimum bit

clock LO pulsewidth is t

DBL

. The minimum bit clock period is

DBP

. The left/right clock minimum setup time is t

DLS

and the

left/right clock minimum hold time is t

DLH

. The serial data

minimum setup time is t

DDS

and the minimum serial data hold

time is t

DDH

The power-down/reset timing is shown in Figure 11. The mini-
mum reset LO pulse width is t

PDRP

(four MCLK periods) to

accomplish a successful AD1855 reset operation.

AD1855

REV. B

TYPICAL PERFORMANCE

Figures 12 through 15 illustrate the typical analog performance
of the AD1855, at F

= 48 kHz, as measured by an Audio Preci-

sion System Two. Signal-to-Noise and THD+N performance

are shown under a range of conditions. Figure 16 shows the
power supply rejection performance of the AD1855. Figure 17
shows the noise floor of the AD1855. The digital filter transfer
function is shown in Figure 18. The two-tone test in Figure 19
is per the SMPTE Standard for Measuring Intermodulation
Distortion.

10

90

50

60

70

80

30

40

20

100

110

120

130

140

FREQUENCY kHz

150

160

Figure 12. 1 kHz Tone at 0.5 dBFS (8K-Point FFT)

40

45

85

65

70

75

80

55

60

50

100

105

dBr

FREQUENCY kHz

110

90

95

40

45

50

55

60

65

70

75

80

85

90

95

100

105

110

dBr

Figure 13. THD+N vs. Frequency at 0.5 dBFS

10

90

50

60

70

80

30

40

20

100

110

120

130

140

FREQUENCY kHz

150

160

10

90

50

60

70

80

30

40

20

100

110

120

130

140

150

160

Figure 14. Dynamic Range: 1 kHz at 60 dB

120

110 100 90 80 70 60 50 40 30

60

80

40

20

100

120

dBr

AMPLITUDE dBFS

20 10

20

40

60

80

100

120

dBr

Figure 15. THD+N vs. Amplitude at 1 kHz

AD1855

REV. B

100

200

500

dBr

10k

20k

25

30

35

40

15
20

10

FREQUENCY Hz

45

50

70

75

80

60
65

55

25

30

35

40

15
20

10

45

50

70

75

80

60
65

55

dBr

Figure 16. Power Supply Rejection to 300 mV p-p on AV

10

90

50

60

70

80

30

40

20

100

110

120

130

140

dBr

FREQUENCY kHz

150

10

20

30

40

50

60

70

80

90

100

110

120

130

140

150

dBr

Figure 17. Noise Floor

FREQUENCY kHz

100

160

MAGNITUDE RESPONSE

100

120

140

10

40

60

80

90

20

30

50

70

Figure 18. Digital Filter Response

10

90

50

60

70

80

30

40

20

100

110

120

130

140

dBr

FREQUENCY kHz

150

10

20

30

40

50

60

70

80

90

100

110

120

130

140

150

dBr

Figure 19. Two-Tone Test

AD1855

REV. B

Smooth Volume Control with Auto Ramp Up/Down

The AD1855 incorporates ADI's 1024 step "Smooth Volume
Control" with auto ramp up/down. Once per L/

RCLK cycle,

the AD1855 compares current volume level register to the vol-
ume level request register Data 9 through Data 0. If different,
volume is adjusted 1 step/sample. Therefore a change from
max to min volume takes 1024 samples or about 20 ms as
shown in Figure 20.

20ms

TIME

60

LEVEL

VOLUME REQUEST REGISTER

ACTUAL VOLUME REGISTER

Figure 20. Smooth Volume Control

Output Drive, Buffering and Loading

The AD1855 analog output stage is able to drive a 1 k

(in

series with 2 nF) load.

Power-Down/Reset

The AD1855 offers two methods for power-down and reset.
When the

PD/RST input (Pin 24) is asserted LO, the AD1855

is reset. As an alternative, the user can assert the soft power-
down bit (Data 13) HI. All the registers in the AD1855 digital
engine (serial data port, interpolation filter and modulator) are
zeroed. The two 8-bit registers in the serial control port are
initialized back to their default values. The user should wait
100 ms after bringing

PD/RST HI before using the serial data

input port and the serial control input. The AD1855 is designed
to minimize pops and clicks when entering and exiting the power-
down state. A reset should always be performed at power-on.

De-Emphasis

The AD1855 offers digital de-emphasis, supporting 50

µs/

µs digital de-emphasis intended for "redbook" 44.1 kHz

sample frequency playback from Compact Discs. The AD1855
offers control of de-emphasis by asserting the DEEMP input
(Pin 9) HI or by asserting the de-emphasis register bit (Data 12)
HI. The AD1855's de-emphasis is optimized for 44.1 kHz but
will scale to the other sample frequencies.

Control Signals

The IDPM0, IDPM1, and DEEMP control inputs are normally
connected HI or LO to establish the operating state of the
AD1855. They can be changed dynamically (and asynchro-
nously to L/

RCLK and the master clock) as long as they are

stable before the first serial data input bit (i.e., MSB) is pre-
sented to the AD1855.

AD1855

REV. B

I/F MODE

IDPM1 IDPM0

RJ, 16-BIT

DSP WCLK 1

U3B

SSM2135

C9
390pF
NP0

953

R20

549

2.15k

C14

1nF, NP0

R17

1.96k

C13

1nF, NP0

R10

953

R16

1.96k

R11

2.15k

C10
390pF
NP0

C15
2.2nF
NP0

LEFT
OUT

C11
390pF
NP0

R12

953

R21

549

R13

2.15k

C17

1nF, NP0

C16

1nF, NP0

R14

953

R15

2.15k

C12
390pF
NP0

C18
2.2nF
NP0

RIGHT
OUT

100nF

AV

100nF

+AV

SSM2135

U3A

R18

1.96k

3RD ORDER LP BESSEL FILTER
CORNER FREQUENCY: 92kHz
GROUP DELAY:

2.8 s

96/

384/

256

X2MCLK

SDATA

RCLK

BCLK

MCLK

IDPM0

IDPM1

DEEMP

MUTE

CLATCH

CCLK

CDATA

ZEROR

ZEROL

PD/RST

DVDD

AVDD

OUTL+

OUTL

OUTR+

OUTR

FILTR

FITLB

DGND

AGND AGND

AD1855JRS

C8
10 F

100nF

C7
10 F

CLATCH

CCLK

CDATA

DE-EMPHASIS

MUTE

I/F

MODE

JP2

R5
10k

R4
10k

DVDD

RST

DGND

CDATA

CCLK

CLATCH

SDATA

LRCLK

SCLK

MCLK

JP1

MCLK/SR

SEL

R2
10k

R3
10k

DVDD

R1
10k

100nF

DVDD

100nF

AVDD

AD1855 STEREO DAC

OUTPUT BUFFERS AND LP FILTERS

MCLK/SR SELECT

SELECT RATE X2MCLK 384/

256 96/48

MCLK

SPDIF
DIRECT
DIRECT

44.1
48.0
96.0

0
0
0

0
0
1

11.2896
12.2880
12.2880

DVDD

U2A

HC04

U2B

HC04

R6
221

CR1
ZERO LEFT

100nF

R7
221

CR2
ZERO RIGHT

FB1

600Z

NOTE:

= DGND

= AGND

R19

1.96k

AUDIO

DATA

CONTROL

PORT

53.6k

OPT

53.6k

OPT

: OPTIONAL. TRIM FOR BEST THD.

IMPROVES THD UP TO 6dB OVER DATA
SHEET.

Figure 21. Evaluation Board Circuit

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