Document Outline
- FEATURES
- APPLICATIONS
- GENERAL DESCRIPTION
- FUNCTIONAL BLOCK DIAGRAM
-
-
-
-
-
-
-
-
-
Digital BTSC Encoder
with Integrated ADC and DAC
AD1970
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
2005 Analog Devices, Inc. All rights reserved.
FEATURES
Complete BTSC encoder
Pilot tone generator
Includes subcarrier modulation
Channel separation: 30 dB
Bandwidth up to 14 kHz
Stereo analog or digital input
Phat-StereoTM algorithm for stereo image enhancement
Dialog enhancement function for playing wide dynamic
range video sources over built-in TV speakers
Includes L - R dual-band compressor
I
2
C port for control of modes, effects, and parameters
Analog input performance
74 dB dynamic range
-72 dB THD + N
Digital input performance
87 dB dynamic range
-83 dB THD + N
Integrated op amps for analog inputs and outputs
Single-ended output reduces external part count
Integrated PLL generates all clocks from composite video,
48 kHz sample clock, or high speed master clock
Sync stripper to recover video clock from composite
video signal
Output level control for setting aural carrier deviation
Macrovision
TM
-compliant
Dolby
TM
RF mode-compatible
48-pin LQFP plastic package
APPLICATIONS
Digital set top box
DVD player
DVD recorder
GENERAL DESCRIPTION
The AD1970 is a complete analog or digital-in, analog-out
BTSC encoder which includes pilot-tone generation and sub-
carrier mixing functions. The stereo ADC provides the means
for digitization of the analog baseband audio signal. A built-in
high performance DAC is provided to output the BTSC base-
band composite signal. The output of the AD1970 can be
connected with minimal external circuitry to the input of a
4.5 MHz aural FM modulator.
In addition to the digital BTSC encoder, the AD1970 includes a
stereo image enhancement function, Phat Stereo, to increase the
sense of spaciousness available from closely spaced TV
loudspeakers. A dialog enhancement algorithm solves the
problem of playing wide dynamic range sources over limited-
performance TV speakers and amplifiers. An I
2
C port allows
control of the AD1970's registers and parameters.
The AD1970 utilizes ADI's patented multibit - architecture to
provide BTSC performance of up to 87 dB dynamic range and a
THD+N of -83 dB.
The AD1970 includes patented BTSC stereo TV technology
licensed from THAT Corporation.
FUNCTIONAL BLOCK DIAGRAM
ANALOG L/R
INPUTS
I
2
C I/O
GROUP
I
2
C PORT
CONTROL
REGISTERS
ADC
VOLUME
CONTROL
BTSC
ENCODER
CORE
BTSC
ENCODED
OUTPUT
ANALOG
BIAS
3
DAC
DECIMATION
FILTER
05500-001
PLL
SYNC
STRIPPER
ADC
ADC
4
DIGITAL AUDIO
INTERFACE
COMPOSITE
VIDEO
AD1970
Figure 1.
AD1970
Rev. 0 | Page 2 of 20
TABLE OF CONTENTS
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 6
Package Characteristics (48-Lead LQFP).................................. 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Theory of Operation ........................................................................ 9
Signal Processing ............................................................................ 10
Background of BTSC ................................................................. 10
Performance Factors .................................................................. 10
Separation Alignment ................................................................ 11
Phase Linearity of the External Analog Filter......................... 11
Input Levels ................................................................................. 11
Clocking and PLL....................................................................... 11
Crystal Oscillator........................................................................ 11
General Purpose Input/Output (GPIO) Pins ......................... 11
Power-Up Sequence ................................................................... 11
Control Port .................................................................................... 12
I
2
C Port Overview ...................................................................... 12
I
2
C Address Decoding................................................................ 12
Input Level Control.................................................................... 13
Output Level Control................................................................. 13
I
2
C Read/Write Data Formats................................................... 14
Analog Input/Output ..................................................................... 16
ADC Input................................................................................... 16
DAC Output................................................................................ 16
Serial Data Port........................................................................... 16
Serial Data Modes ...................................................................... 16
Typical Applications Circuit.......................................................... 18
Outline Dimensions ....................................................................... 19
Ordering Guide .......................................................................... 19
REVISION HISTORY
4/05--Revision 0: Initial Version
AD1970
Rev. 0 | Page 3 of 20
SPECIFICATIONS
Test conditions, unless otherwise noted
Table 1.
Parameters Conditions
Unit
Supply Voltages (AV
DD
, DV
DD
)
3.3
V
Ambient Temperature
25
C
Input Signal
1 kHz, 0.8 V
RMS
analog, 0 dBFS digital
Hz, V rms, dBFS
Input Sample Rate
48
kHz
Measurement Bandwidth
20 Hz to 14 kHz
kHz
Word Width
24
Bits
Load Capacitance
50
pF
Load Current
1
mA
Input Voltage High
2.0
V
Input Voltage Low
0.8
V
Table 2. Analog Input Performance
Parameter
Min
Typ
Max
Unit
Maximum Input Level
1.0 (2.8)
V rms (V p-p)
Output Level
250
mV
rms
Dynamic Range (20 Hz to 14 kHz, 60 dB Input) (Encoded Output, Left = Right)
68
74
dB
THD + Noise (Encoded Output, Left = Right, 20 Hz to 14 kHz)
V
IN
= 0 dBV rms
72
65
dB
Table 3. Digital Input Performance
Parameter
Min
Typ
Max
Unit
Resolution
24
Bits
Output Level
250
mV
rms
Dynamic Range (20 Hz to 14 kHz, 60 dB Input) (Encoded Output, Left = Right)
81
87
dB
THD + Noise (Encoded Output, Left = Right, 20 Hz to 14 kHz)
V
IN
= 0 dBFS
83
74
dB
Table 4. Video Input
Parameter
Min
Typ
Max
Unit
Input Signal Level
0.35
1.0
V
P-P
Input Impedance
2 k
Table 5. Crystal Oscillator
Parameter
Min
Typ
Max
Unit
Transconductance
7
10
13
mmhos
AD1970
Rev. 0 | Page 4 of 20
Table 6. BTSC Encoder Performance
Parameter
Min
Typ
Max
Unit
CHANNEL SEPARATION (25 dB INPUT)
30 Hz to 500 Hz
24
30
dB
500 Hz to 5 kHz
18
21
dB
5 kHz to 13.5 kHz
14
15
dB
CHANNEL SEPARATION AT 1 kHz
0 dB Input
25 27
2 dB Input
24 26
FREQUENCY RESPONSE
30 Hz to 10 kHz
1
+0.5
dB
30 Hz to 13.5 kHz
1.5
+0.5
dB
Table 7. Digital I/O
Parameter
Min
Typ
Max
Unit
Input Voltage High (V
IH
) 2.0
V
Input Voltage Low (V
IL
)
0.8
V
Input Leakage (I
IH
@ V
IH
= 2.4 V)
10
A
Input Leakage (I
IL
@ V
IL
= 0.4 V)
10
A
High Level Output Voltage (V
OH
) I
OH
= 2 mA (except VID_PRES)
DVDD - 0.6
V
Low Level Output Voltage (V
OL
) I
OL
= 2 mA
0.4
V
Table 8. Power
Parameter
Min
Typ
Max
Unit
SUPPLIES
Voltage, Analog, Digital, PLL
3.0
3.3
3.6
V
Analog Current
30
41
50
mA
Digital Current
30
38
48
mA
PLL Current
1
5
8
mA
DISSIPATION
All Supplies
277
mW
Analog Supply
135
mW
Digital Supply
125
mW
PLL Supply
17
mW
Table 9. Temperature Range
Parameter
Min
Typ
Max
Unit
Specifications Guaranteed
25
C
Functionality Guaranteed
0
70
C
Storage
55
+125
C
AD1970
Rev. 0 | Page 5 of 20
Table 10. Digital Timing
Parameter
Min
Typ
Max
Unit
t
DMD
MCLK Duty Cycle, External 512 f
S
Mode
40
50
60
%
t
DBL
MCLK Low Pulse Width, External 512 f
S
Mode
15
ns
t
DBH
MCLK High Pulse Width, External 512 f
S
Mode
15
ns
t
DBL
MCLK Low Pulse Width, PLL, 256 f
S
or f
S
Mode
15
ns
t
DBH
MCLK High Pulse Width, PLL, 256 f
S
or f
S
Mode
15
ns
t
DLS
LRCLK Setup
10
ns
t
DLH
LRCLK Hold
10
ns
t
DDS
SDATA Setup
10
ns
t
DDH
SDATA Hold
10
ns
t
IBC
I
2
C Bus Clock Frequency
400
kHz
t
ISST
I
2
C Setup Time for Start Condition
10
ns
t
IH
I
2
C Hold Time for Start Condition
30
ns
t
SDS
SDA Setup Time
50
ns
t
SDH
SDA Hold Time
25
ns
t
SDF
SDA Fall Time at 3 mA Sink and 400 pF Load
25
ns
t
SDR
SDA Rise Time
300
ns
t
PWS
Pulse Width of Spikes Supressed by the Input Filter
50
ns
t
PDRP
RESETB Low Pulse Width
15
ns
AD1970
Rev. 0 | Page 6 of 20
ABSOLUTE MAXIMUM RATINGS
Table 11.
Min
Max
Unit
DV
DD
to DGND
0.3
+3.95
V
ODV
DD
to DGND
0.3
+3.95
V
AV
DD
to AGND
0.3
+3.95
V
Digital Inputs
DGND 0.3
DV
DD
+ 0.3
V
Analog Inputs
AGND 0.3
AV
DD
+ 0.3
V
AGND to DGND
0.3
+0.3
V
Reference Voltage
(AV
DD
+ 0.3)/2
V
Maximum Junction
Temperature
+125
C
Storage Temperature
Range
65
+150
C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
PACKAGE CHARACTERISTICS (48-LEAD LQFP)
Table 12.
Min Typ
Max
Unit
JA
(Thermal Resistance
[Junction-to-Ambient])
72
C/W
JC
(Thermal Resistance
[Junction-to-Case])
19.5
C/W
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
AD1970
Rev. 0 | Page 7 of 20
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
NC = NO CONNECT
AD1970
TOP VIEW
(Not to Scale)
DVDD
1
RESETB
2
DGND
3
DVDD
4
RSVD
5
DGND
GPIO1
GPIO0
XIN
XOUT
36
35
34
33
32
VOUT_OAMP
6
VIN_OAMP
7
AVDD
8
BTSC_OUT
9
AGND
10
VREF
11
FILTCAP
12
VID_PRES
MCLK
PLL_MODE1
PLL_MODE0
NC
31
30
29
28
27
VID_IN
PGND
26
25
AV
DD
13
AGND
14
V
O
UT_
I
AMP
L
15
VIN
_
IA
M
P
L
16
V
O
UT_
I
AMP
R
17
VIN
_
IA
M
P
R
18
CAP
LP
19
CAP
LN
20
CAP
RP
21
CAP
RN
22
PVD
D
23
PLL_LF
24
DGND
ADR0
ADR1
SC
L
SD
A
48 47 46 45 44
DIG_
IN_
E
N
LRCLK
BCLK
S
DATA
GPIO3
43 42 41 40 39
GPIO2
DV
DD
38 37
05500-002
Figure 2. Pin Configuration
Table 13. Pin Function Descriptions
Pin No.
Pin Name
Input/Output
Description
1
DVDD
Digital Power.
2
RESETB
IN
Reset--Active Low. After RESETB transitions from low to high, the AD1970 BTSC encoder
core goes through an initialization sequence where all registers are set to 0. The
initialization is completed after 1024 MCLK cycles. New values should not be written to
the control port until the initialization is complete.
3
DGND
Digital Ground.
4
DVDD
Digital Power. 3.3 V nominal.
5
RSVD
Reserved--Connect to DGND.
6
VOUT_OAMP
OUT
Output voltage of internal op amp to be used for BTSC output low pass filter.
7
VIN_OAMP
IN
Negative input of internal op amp to be used for BTSC output low pass filter.
8
AVDD
Analog Power.
9
BTSC_OUT
OUT
Encoded BTSC Output. The nominal output voltage for a 300 Hz, 0 dB mono input signal is
250 mV rms.
10
AGND
Analog Ground.
11
VREF
OUT
Connection for voltage reference noise reduction capacitor. The nominal VREF voltage is
1.5 V; the analog gain scales directly with the voltage on this pin. Any ac signal on this pin
causes distortion and therefore a large decoupling capacitor should be used to ensure the
voltage on VREF is clean.
12
FILTCAP
OUT
Connection for DAC noise reduction capacitor. A 10 F capacitor should be connected to
this pin to reduce the noise on an internal DAC biasing point to provide the highest
performance. It may not be necessary to connect this pin, depending on the quality of the
layout and grounding used in the application circuit.
13
AVDD
Analog Power. 3.3 V nominal. Bypass capacitors should be placed close to the pins and
connected directly to the analog ground plane.
14
AGND
Analog Ground.
15
VOUT_IAMPL
OUT
Output of internal op amp for left channel input amplifier.
16
VIN_IAMPL
IN
Negative input of internal op amp for left channel input amplifier.
17
VOUT_IAMPR
OUT
Output of internal op amp for right channel input amplifier.
AD1970
Rev. 0 | Page 8 of 20
Pin No.
Pin Name
Input/Output
Description
18
VIN_IAMPR
IN
Negative input of internal op amp for right channel input amplifier.
19
CAPLP
I/O
ADC Filter Capacitor Connection (positive left-channel input to modulator). A 1 nF
capacitor should be placed between this pin and analog ground.
20
CAPLN
I/O
ADC Filter Capacitor Connection (negative left-channel input to modulator). A 1 nF
capacitor should be placed between this pin and analog ground.
21
CAPRP
I/O
ADC Filter Capacitor Connection (positive right-channel input to modulator). A 1 nF
capacitor should be placed between this pin and analog ground.
22
CAPRN
I/O
ADC Filter Capacitor Connection (negative right-channel input to modulator). A 1 nF
capacitor should be placed between this pin and analog ground.
23
PVDD
PLL Power. 3.3 V nominal. Bypass capacitors should be placed close to this pin and
connected directly to the PLL ground.
24
PLL_LF
PLL Loop Filter Connection.
25
PGND
PLL Ground. Connect to DGND.
26
VID_IN
IN
Composite Video Input. Composite video signal input to the sync separator. The sync
output is connected to a PLL that generates the clocks for the AD1970. This pin has an
input impedance of 2 k.
27
NC
No Connect.
28
PLL_MODE0
IN
PLL Mode Select Pin 0. The setting of these pins indicates the source and frequency of the
input clock to generate the internal MCLK for the AD1970.
29
PLL_MODE1
IN
PLL Mode Select Pin 1. The setting of these pins indicates the source and frequency of the
input clock to generate the internal MCLK for the AD1970.
30
MCLK
IN
Master Clock Input. This input is used to generate the internal master clock if it is not
derived from the composite video signal on VID_IN. The master clock frequency must be
either fs or 256 fs, where fs is the input sampling frequency. The PLL_CTRLx pins should
be set to accept the appropriate MCLK input frequency.
31
VID_PRES
OUT
Video Present Flag. A high logic level on this pin indicates that a valid composite video
signal is present on the VID_IN pin. Open-drain output.
32
XOUT
OUT
Crystal Oscillator Output. This pin is the output of the on-board oscillator and should be
connected to one side of a crystal.
33
XIN
IN
Crystal Oscillator Input. This pin is the input to the on-board oscillator and should be
connected to one side of a crystal.
34
GPIO0
IN/OUT
General Purpose I/O 0. This pin can be set to be either a static input or output, with levels
and direction controlled through the I
2
C port.
35
GPIO1
IN/OUT
General Purpose I/O 1. This pin can be set to be either a static input or output, with levels
and direction controlled through the I
2
C port.
36
DGND
Digital Ground.
37
DVDD
Digital Power.
38
GPIO2
IN/OUT
General Purpose I/O 2. This pin can be set to be either a static input or output, with levels
and direction controlled through the I
2
C port.
39
GPIO3
IN/OUT
General Purpose I/O 3. This pin can be set to be either a static input or output, with levels
and direction controlled through the I
2
C port.
40
SDATA
IN/OUT
Serial Data Input/Output (Before BTSC Encoding). Digital input to the BTSC encoder or
output of the ADC. The serial format is selected by writing to Bits 3:2 of Control Register 1.
41
BCLK
IN/OUT
Bit Clock Input/Output. Serial bit clock for clocking in the serial data. The interpretation of
BCLK changes according to the serial mode, which is set by writing to the control
registers.
42
LRCLK
IN/OUT
Left/Right Clock Input/Output. Left/right clock for framing the serial input data. The
interpretation of the LRCLK changes according to the serial mode, set by writing to the
control registers.
43
DIG_IN_EN
IN
Digital Input Enable (active high).
44
SDA
IN/OUT
I
2
C Serial Data Input/Output.
45
SCL
IN
I
2
C Serial Clock Input.
46
ADR1
IN
I
2
C Address 1. The address of the I
2
C port is set by these pins according to Table 16.
47
ADR0
IN
I
2
C Address 0. The address of the I
2
C port is set by these pins according to Table 16.
48
DGND
Digital Ground.
AD1970
Rev. 0 | Page 9 of 20
THEORY OF OPERATION
The AD1970 is comprised of a BTSC encoder with stereo
analog inputs and a sync separator to derive the pilot signal
from the composite video stream. Figure 1 shows the block
diagram of the device.
Signal processing parameters are stored in a parameter RAM,
which is initialized on power-up by an internal boot ROM. The
values stored in the parameter RAM control all the filter coef-
ficients, mixing, and dynamics-processing code used in the
BTSC algorithm.
The AD1970 has an I
2
C port that supports complete read/write
capability of the parameter RAM, as well as a control port and
several other registers that allow the various signal processing
parameters to be controlled. The AD1970 can run as a stand-
alone processor without external control.
The AD1970 has a very flexible serial data input port that allows
for glueless interconnection to a variety of digital signal sources.
The AD1970 can be configured in left-justified, I
2
S, right-
justified, or DSP serial port-compatible modes. It can support
16, 20, and 24 bits in all modes. The AD1970 accepts serial
audio data in MSB first, twos complement format.
The AD1970 operates from a single 3.3 V power supply. It is
fabricated on a single monolithic integrated circuit and is
housed in a 48-pin LQFP package for operation over the
temperature range of 0C to 70C.
AD1970
Rev. 0 | Page 10 of 20
SIGNAL PROCESSING
BACKGROUND OF BTSC
BTSC is the name of the standard for adding stereo audio capa-
bility to the US television system. It is in many ways similar to
the algorithm used for FM stereo broadcasts, with the addition
of a sophisticated compressor circuit to improve the signal-to-
noise ratio.
To maintain compatibility with non-BTSC TV receivers, the
processing of mono (L = R) signals is unchanged from the
original pre-BTSC system. The L + R signal is applied to a 75 s
pre-emphasis filter, and is then applied to a 4.5 MHz FM mod-
ulator, which is later added to the video signal to create a
composite video signal.
Stereo capability is added by taking the L - R signal, applying it
to a 2-band dynamic compressor, and then multiplying this
signal by a carrier signal at twice the horizontal scanning rate
(F
h
), or about 2 15.734 kHz. This multiplication is known as
double sideband, suppressed-carrier modulation, and it
effectively translates the compressed L - R spectrum up in
frequency so that it sits above the audio band (see Figure 3).
For the receiver to recover this L - R signal, a pilot tone at the
horizontal rate is added to the signal. The receiver has a PLL
that locks to this pilot and generates a signal at the carrier
frequency. This signal is then used to multiply the composite
BTSC-encoded signal, which translates this component back
down to baseband. Once the L + R and L - R signals are
recovered, a simple addition/subtraction circuit (sometimes
referred to as the matrix) can be used to recover the right signal.
Since the pilot tone is added at 15.734 kHz, it is necessary to
reduce the bandwidth of the signal so that audio signals cannot
interfere with the pilot tone. In the AD1970, the bandwidth is
limited to 14 kHz; above this frequency, the response decays
very rapidly.
PERFORMANCE FACTORS
To maintain good separation between the left and right
channels, it is necessary to closely match the filtering and
companding standards set forth in the standard (FCC OET60).
Even small errors can result in poor performance. The AD1970
has been programmed to match these standards as accurately as
possible. Typical separation numbers range from 30 dB at
frequencies below 500 Hz to 15 dB at 13.5 kHz. Measuring these
numbers can be difficult, since significant differences exist
between many units sold as reference decoders, which are all
implemented with analog components.
05500-003
MATRIX
COMPRESSOR
75
s
PRE-EMPH
FILTER
OSCILLATOR
RMS
DETECT
PRE-EMPH
SECOND
ORDER
LPF
EIGHT
ORDER
GAIN
BANDPASS
SECOND
ORDER
GAIN
BANDPASS
FOURTH
ORDER
1/X
RMS
DETECT
NONLINEAR
FORMULA
L-R IN
2
Fh CARRIER
Fh PILOT
LR
L+R
L
R
MAIN
ALGORITHM
FLOW
TO
DAC
SPECTRAL TILT
FILTER
Figure 3. Signal Processing Flow
AD1970
Rev. 0 | Page 11 of 20
SEPARATION ALIGNMENT
The BTSC encoder outputs are all specified in terms of the
deviation of the FM 4.5 MHz carrier. For the AD1970, a digital
input level of 0 dB (mono signal) should cause a carrier devia-
tion of 25 kHz without the 75 s pre-emphasis filter. In
practice, the pre-emphasis filter can be left in for this adjust-
ment, as long as the frequency is low enough to not be affected
by the filter. It is critical to maintain the proper gain relationship
between the BTSC encoder and the 4.5 MHz FM modulator. A
common mistake is to assume that changing the gain between
the BTSC encoder output and the FM modulator input has the
same effect as changing the audio input level going in to the
BTSC encoder. The presence of a complicated 2-band nonlinear
dynamics processor means that the encoder output must be
connected to the decoder input (through the FM modulation/
demodulation process) with a known gain. If this gain is
changed, then the separation significantly suffers.
When measuring the AD1970 on the bench, it is possible to use
a BTSC reference decoder box, so that the FM modulation/
demodulation process can be skipped. These units have a
method of adjusting the input voltage sensitivity to achieve best
separation. The output level of the AD1970 can also be adjusted
over a wide range using either the I
2
C control port or by
adjusting the values of the components used in the external
analog low-pass filter that is between the BTSC encoder output
and the input to the FM modulator.
PHASE LINEARITY OF THE EXTERNAL ANALOG
FILTER
If the time-alignment of the pilot to the carrier signal is not
close to 0, a loss of separation can occur. This means that the
external analog low-pass filter should be a linear-phase design
to provide constant group delay over the range from dc to
50 kHz. A Bessel filter is recommended for this application. The
typical applications circuit (see Figure 8) shows a recommended
design for this filter.
INPUT LEVELS
The maximum input level to the AD1970 changes across
frequency. Table 14 shows the maximum allowable input level
for different frequencies. These values are part of the BTSC
specification, not a function of this chip.
Table 14. Maximum Input Levels to the BTSC Encoder
across Frequency
Frequency (Hz)
Maximum Input Level (dBFS)
20 to 1000
0
1600
-1
2500
-3
3150
-5
5000
-8
8000
-11
12500
-15
CLOCKING AND PLL
The AD1970's master clock either can be directly fed to the
MCLK pin or generated by a PLL from a composite video signal
input on the VID_IN pin. If the clock input is on the MCLK pin,
the PLL can synthesize the internal clocks from either a clock at
the digital audio frame sync frequency (f
S
= 48 kHz) or 256 f
S
.
The PLL mode is controlled by Pins PLL_MODE0 and
PLL_MODE1. The settings are shown in Table 15.
Table 15. PLL Modes
PLL_MODE1
PLL_MODE0
Setting
0
0
Composite video input (on
VID_IN)
0
1
256 fs (on MCLK)
1
0
fs (on MCLK)
1
1
PLL bypass
CRYSTAL OSCILLATOR
The AD1970 has an on-board crystal oscillator to generate a
clock that can be used by an RF modulator or other application.
For example, a 4 MHz crystal can be connected as shown in the
application circuit (see Figure 8). The AD1970 does not use this
clock itself, so if it is not needed in an application the XIN pin
should be grounded and the XOUT pin left unconnected.
GENERAL PURPOSE INPUT/OUTPUT (GPIO) PINS
Pins GPIO0, GPIO1, GPIO2, and GPIO3 are set to be inputs or
outputs by Bits 19:16 of Control Register 2. All four default to
input state. These pins do not take an input to or send an output
from the main signal flow. When set as an output, the binary
value on the pins is set according to Bits 15:12 of Control
Register 2. These pins can be used to interface with I/O pins on
a microcontroller and allow hardware control via the I
2
C bus.
POWER-UP SEQUENCE
The AD1970 has a built-in power-up sequence that initializes
the contents of all internal RAMs. During this time, the
parameter RAM is filled with values from its associated boot
ROM. The data memories are also cleared during this time.
The boot sequence lasts for 1024 MCLK cycles and starts on the
rising edge of the RESETB pin. The user should avoid writing to
or reading from the I
2
C registers during this period of time.
AD1970
Rev. 0 | Page 12 of 20
CONTROL PORT
I
2
C PORT OVERVIEW
The AD1970 can be controlled using the I
2
C port. In general,
there are three parameters that can be controlled: the encoder
output level, the Phat Stereo image enhancement algorithm, and
the dialog enhancement algorithm. It is also possible to write
new data into the parameter RAM to alter the filter coefficients
used in the BTSC encoding process. Since this is a fairly
complex topic and is unnecessary for normal operation of the
chip, the details are not included in this data sheet; please
contact ADI sales if modifications to the BTSC filters are
required.
The I
2
C port uses a 2-wire interface consisting of SDA, the
bidirectional data line, and SCL, the clock.
The R/W bit is low for a write operation and high for a read
operation. The 10-bit address word is decoded into either a
location in the parameter RAM or one of the registers. The
number of data bytes varies according to the register or
memory being accessed. The detailed data format diagram for
continuous-mode operation is given in the section.
I
2
C ADDRESS DECODING
Table 16 shows the address decoding used in the I
2
C port. Four
different addresses are available to avoid conflicting addresses
on an I
2
C bus. The I
2
C address space encompasses a set a
registers and the parameter RAM. The parameter RAM is
loaded on power-up from an on-board boot ROM.
Table 16. I
2
C Address Settings
ADR1
ADR0
I
2
C Address
0
0
0x20
0
1
0x21
1
0
0x22
1
1
0x23
Table 17. I
2
C Port Address Decoding
Register Address
Register Name
Read/Write Word Length
0
Input Level Control
Write: 22 bits
Read: 22 bits
1 to 254
Parameter RAM
255
Output Level Control
256
Control Register 1
Write: 11 bits
Read: 6 bits
257
Control Register 2
Write: 22 bits
258
ADC Volume Control
259
Stereo Spreading Control
260
Dialog Enhancement Control
AD1970
Rev. 0 | Page 13 of 20
INPUT LEVEL CONTROL
This register location controls the input level of both the left
and right channels to the AD1970 BTSC encoding algorithm.
The register defaults to a value of 1.0 (0100000000000000000000
in binary 2.20 format) and allows a maximum of 12 dB of gain
at a full-scale value. This feature allows compatibility with the
Dolby digital specification for proper operation in both RF
mode and line mode. In RF mode, the dialog level is specified at
11 dB higher than the dialog level in line mode. A gain of 11 dB
can be achieved by writing 1.8836 to Address 0.
OUTPUT LEVEL CONTROL
The level control of the BTSC-encoded output is controlled
in this register location. The default value is 0.5 (6 dB,
0010000000000000000000 in binary 2.20 format), or 250 mV
on the DAC output. The output level should not be used as a
volume control. Its intended use, in conjunction with the output
filter, is to match the level with the expected input of the BTSC
decoder. Matching these allows maximum separation between
the left and right encoded channels.
Control Register 1
Control Register 1 is an 11-bit register that controls serial
modes, de-emphasis, mute, power-down, and I
2
C-to-memory
transfers. Table 18 documents the contents of this register.
Bits 5:4 and 10:8 are reserved and should be set to 0 at all times.
The audio signal is muted with Bit 7 of the control register.
The soft power-down bit (Bit 6) stops the internal clocks to the
DSP core, but does not reset the part. The digital power
consumption is reduced to a low level when this bit is asserted.
Reset can only be asserted using the external reset pin.
Bits 3:2 select the serial format from one of four modes. These
different formats are discussed in the section of this data sheet.
The word length bits (1:0) are used in right-justified serial
modes to determine where the MSB is located relative to the
start of the audio frame.
Table 18. Control Register 1 Write
Register Bits
Function
10:8
Reserved, set to 000
7
Soft mute (1 = start mute sequence)
6
Soft power-down (1 = power-down)
5:4
Reserved, set to 00
3:2
Serial-In mode
00 = I
2
S
01 = Right-justified
10 = DSP
11 = Left-justified
1:0
Word length
00 = 24 bits
01 = 20 bits
10 = 16 bits
11 = 16 bits
Table 19. Control Register 1 Read
Register Bits
Function
5:2
GPIO 3:0 read back
1:0
Reserved
Control Register 2
Control Register 2 is a 22-bit write-only register that controls
power down modes, PLL and sync separator controls, and
digital I/O pin functions.
Table 20. Control Register 2
Register Bits
Function
21
Enable ADC output on serial audio interface
20
Reserved
19:16
GPIO output enable 3:0
15:12
GPIO data
11:9
PLL shift, default 100
8:4
Sync separator slicer voltage; default 10111
3
ADC power-down
2
Reference power-down
1
DAC power-down
0
PLL power-down
ADC Volume Control Register
This controls the input level of both ADC channels. The default
value is 1.0 (0100000000000000000000 in binary 2.20 format).
Stereo Spreading Register
This register controls ADI's patented Phat Stereo spatial
enhancement algorithm. The default is all 0s, which
corresponds to no effect. The maximum setting is
0100000000000000000000 or a twos complement fractional
value of 1.0. Note that the bass energy in each channel is
increased using this algorithm, which may cause some digital
clipping on full-scale signal peaks, especially at low frequencies.
AD1970
Rev. 0 | Page 14 of 20
Dialog Enhancement Register
This controls the built-in dialog enhancement algorithm, and
defaults to 0. The maximum setting is 0100000000000000000000
or a twos complement fractional value of 1.0. This algorithm is
intended to solve the problem of playing back high dynamic
range digital audio signals over a television's built-in speakers. It
provides an amplitude boost to signals that are in the range
where dialog signals are usually found, while at the same time
preventing loud special effects passages from overloading the
speakers or amplifiers.
I
2
C READ/WRITE DATA FORMATS
The read/write formats of the I
2
C port are designed to be byte
oriented. This allows for easy programming of common micro-
controller chips. In order to fit into a byte oriented format, 0s
are appended to the data fields in order to extend the data word
to the next multiple of 8 bits. For example, 22-bit words written
to the parameter RAM are appended with two leading zeroes in
order to reach 24 bits (3 bytes). These zero-extended data fields
are appended to a 2-byte field consisting of a read/write bit and
a 10-bit address. The I
2
C port knows how many data bytes to
expect based on the address received in the first two bytes.
05500-009
R/W
0
SCL
SDA
0
1
0
0
AD1 AD0
0
0
0
1
0
0
ACK. BY
AD1970
START BY
MASTER
FRAME 1
CHIP ADDRESS BYTE
FRAME 2
REGISTER ADDRESS UPPER BYTE
ACK. BY
AD1970
0
0
0
1
0
0
0
0
ACK. BY
AD1970
FRAME 3
REGISTER ADDRESS LOWER BYTE
0
REGISTER
WRITE
I
2
C
WRITE
D15 D14 D13 D12 D11 D10
D9
D8
ACK. BY
AD1970
FRAME 4
REGISTER DATA UPPER BYTE
D7
D6
D5
D4
D3
D2
D1
D0
ACK. BY
AD1970
STOP BY
MASTER
FRAME 5
REGISTER DATA LOWER BYTE
SCL
(CONTINUED)
SDA
(CONTINUED)
R/W
Figure 4. Sample of I
2
C Write Format (Control Register 1 Write)
05500-008
D7
D6
D5
D4
D3
D2
D1
D0
ACK. BY
MASTER
FRAME 5
REGISTER DATA BYTE
R/W
0
SCL
(CONTINUED)
SDA
(CONTINUED)
0
1
0
0
AD1 AD0
REPEATED START
BY MASTER
FRAME 4
CHIP ADDRESS BYTE
ACK. BY
AD1970
STOP BY
MASTER
I
2
C
READ
R/W
0
SCL
SDA
0
1
0
0
AD1 AD0
0
0
0
1
0
0
ACK. BY
AD1970
START BY
MASTER
FRAME 1
CHIP ADDRESS BYTE
FRAME 2
REGISTER ADDRESS UPPER BYTE
ACK. BY
AD1970
0
0
0
1
0
0
0
0
ACK. BY
AD1970
FRAME 3
REGISTER ADDRESS LOWER BYTE
0
REGISTER
READ
I
2
C
WRITE
R/W
Figure 5. Sample of I
2
C Read Format (Control Register 1 Read)
AD1970
Rev. 0 | Page 15 of 20
Table 21. Control Register 1 Write Format
Byte 0
Byte1
Byte 2
Byte 3
00000, R/W = 0, Adr [9:8]
Adr [7:0]
00000, Bit [10:8]
Bit [7:0]
Table 22. Control Register 1 Read Format
Byte 0
Byte 1
Byte 2
00000, R/W = 1, Adr [9:8]
Adr [7:0]
00, Bit [5:0]
Table 23. Control Register 2 Write Format
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
00000, R/W = 0, Adr [9:8]
Adr [7:0]
00, Bit [21:16]
Bit [15:8]
Bit [7:0]
Table 24. Input/Output Level Control, ADC Volume Control, Stereo Spreading, and Dialog Enhancement Registers Write Format
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
00000, R/W = 0, Adr [9:8]
Adr [7:0]
00, Level [21:16]
Level [15:8]
Level [7:0]
AD1970
Rev. 0 | Page 16 of 20
ANALOG INPUT/OUTPUT
ADC INPUT
The AD1970 accepts an analog left-right signal on its input.
DAC OUTPUT
Figure 6 shows the block diagram of the analog output. A series
of current sources are controlled by a digital - modulator.
Depending on the digital code from the modulator, each cur-
rent source is connected to the summing junction of either a
positive I-to-V converter or a negative I-to-V converter. Two
extra current sources that push instead of pull are added to set
the midscale common-mode voltage.
All current sources are derived from the VREF input pin. The
gain of the AD1970 is directly proportional to the magnitude of
the current sources, and therefore the gain of the AD1970 is
proportional to the voltage generated on the VREF pin. The
nominal VREF voltage is 1.5 V.
I
REF
I
REF
I
REF
DIG_IN
I
REF
+ DIG_IN
SWITCHED CURRENT
SOURCES
V
REF
IN
OUT
OUT+
FROM DIGITAL
MODULATOR
(DIG_IN)
05500-005
BIAS
Figure 6. Internal DAC Analog Architecture
Since the VREF input effectively multiplies the signal, care must
be taken to insure that no ac signals appear on this pin. This can
be accomplished by using a large decoupling capacitor con-
nected to VREF.
The AD1970 should be used with an external third order filter
on each output channel, as shown in Figure 8. The values shown
are for a 100 kHz Bessel filter. The use of a Bessel filter is impor-
tant to maintain the time-alignment of the pilot to the carrier. If
these signals are not in phase, a loss of separation occurs.
For best performance, a large (>10 F) capacitor should be
connected between the FILTCAP pin and analog ground.
SERIAL DATA PORT
The AD1970's flexible serial audio interface accepts and sends
data in twos complement, MSB first format. The left channel
data field always precedes the right channel data field. The serial
mode is set by using mode select bits in the control register. In
all modes except for the right justified mode, the serial port
accepts an arbitrary number of bits up to a limit of 24 (extra bits
do not cause an error, but they are truncated internally). In the
right-justified mode, control register bits are used to set the
word length to 16, 20, or 24 bits. The default on power-up is 24-
bit mode. Proper operation of the right justified mode requires
that there be exactly 64 BCLKs per audio frame.
SERIAL DATA MODES
Figure 7 shows the left-justified mode. LRCLK is high for the
left channel, and low for the right channel. Data is sampled on
the rising edge of BCLK. The MSB is left-justified to a LRCLK
transition, with no MSB delay. The left-justified mode can
accept any word length up to 24 bits.
Figure 7 shows the I2S mode, which is the default setting.
LRCLK is low for the left channel and the MSB is delayed from
the edge of the LRCLK by a single BCLK period. The I2S mode
can be used to accept any number of bits up to 24.
Figure 7 shows the right-justified mode of the AD1970. LRCLK
is high for the left channel, low for the right channel. Data is
sampled on the rising edge of BCLK. The start of data is delayed
from the LRCLK edge by 16, 12, or 8 BCLK intervals, depending
on the selected word length. The default word length is 24 bits;
other word lengths are set by writing to Bits 1:0 of the control
register. In right-justified mode, it is assumed that there are 64
BCLKs per frame.
Figure 7 shows the DSP serial port mode. LRCLK must pulse
high for at least one bit clock period before the MSB of the left
channel is valid and LRCLK must pulse high again for at least
one bit clock period before the MSB of the right channel is
valid. Data is sampled on the falling edge of BCLK. The DSP
serial port mode can be used with any word length up to 24 bits.
In this mode, it is the responsibility of the DSP to ensure that
the left data is transmitted with the first LRCLK pulse and that
synchronism is maintained from that point forward.
AD1970
Rev. 0 | Page 17 of 20
LRCLK
BCLK
SDATA
LEFT CHANNEL
LSB
RIGHT CHANNEL
LSB
MSB
MSB
LRCLK
BCLK
SDATA
LEFT CHANNEL
LSB
RIGHT CHANNEL
LSB
MSB
MSB
LRCLK
BCLK
SDATA
LEFT CHANNEL
RIGHT CHANNEL
MSB
MSB
LSB
LSB
LRCLK
BCLK
SDATA
LSB
LSB
1/F
S
05500-006
MSB
MSB
LEFT JUSTIFIED MODE: 16 TO 24 BITS PER CHANNEL
I
2
S MODE: 16 TO 24 BITS PER CHANNEL
RIGHT JUSTIFIED MODE: SELECT NUMBER
OF BITS PER CHANNEL
DSP MODE: 16 TO 24 BITS PER CHANNEL
NOTES:
1. DSP MODE DOESN'T IDENTIFY CHANNEL.
2. LRCLK NORMALLY OPERATES AT Fs EXCEPT FOR DSP MODE WHICH IS 2xFs.
3. BCLK FREQUENCY IS NORMALLY 64xLRCLK BUT MAY BE OPERATED IN BURST MODE.
Figure 7. Serial Data Formats
AD1970
Rev. 0 | Page 18 of 20
TYPICAL APPLICATIONS CIRCUIT
19
20
21
22
15
16
17
18
R1
10k
R2
10k
C26
4.7
F
C25
4.7
F
R3
10k
C1
82pF
R4
10k
C2
82pF
C6
1nF
C5
1nF
C4
1nF
C3
1nF
PLL_MODE0
PLL_MODE1
28
29
VID_PRES
VIDEO_IN
R11
10k
R12
1k
C27
470pF
C7
1nF
31
26
30
R13
1k
C9
22pF
Y1
4MHz
C8
22pF
33
32
4MHz
OPTIONAL
AUXILIARY
OSCILLATOR
AUDIO_IN_LEFT
AUDIO_IN_RIGHT
XIN
XOUT
MCLK
3
36
48
25
10
14
DG
ND
DG
ND
DG
ND
PG
ND
AG
ND
AG
ND
RSVD
+
+
C10
10
F
C11
10
F
43
42
35
34
2
11
12
27
5
41
40
39
38
DIG_IN_EN
LRCLK_INTF
BCLK_INTF
SDATA_INTF
GPIO3
GPIO2
GPIO1
GPIO0
RESET
+
+
+
C24
0.1
F
C23
0.1
F
C22
0.1
F
C20
0.1
F
C21
0.1
F
C18
4.7
F
C19
0.1
F
R5
1.6k
C16
2.2
F
C17
0.1
F
L1
600Z
L2
600Z
3.3V
3.3V
3.3V
SCL
SDA
R15
2k
R14
2k
ADR0
ADR1
R6
11k
R8
3.01k
R7
11k
R9
604
R10
49.9k
C14
68pF
C12
2.2nF
C15
270pF
BTSC
C13
10
F
VOUT_IAMPL
VIN_IAMPL
VOUT_IAMPR
VIN_IAMPR
CAPLP
CAPLN
CAPRP
CAPRN
PLL_MODE0
PLL_MODE1
VID_PRES
VID_IN
NC
FILTCAP
VREF
RESET
GPIO0
GPIO1
GPIO2
GPIO3
SDATA
BCLK
LRCLK
DIG_IN_EN
7
6
44
9
45
46
47
VOUT_OAMP
VIN_OAMP
BTSC_OUT
SDA
24
SCL
ADR1
ADR0
PLL_LF
DVDD
DVDD
AVDD
AVDD
DVDD
PVDD
05500-007
1
4
37
8
13
23
+
+
AD1970
Figure 8. Typical Applications Circuit
AD1970
Rev. 0 | Page 19 of 20
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MS-026-BBC
TOP VIEW
(PINS DOWN)
1
12
13
25
24
36
37
48
0.27
0.22
0.17
0.50
BSC
LEAD PITCH
7.00
BSC SQ
1.60
MAX
0.75
0.60
0.45
VIEW A
9.00
BSC SQ
PIN 1
0.20
0.09
1.45
1.40
1.35
0.08 MAX
COPLANARITY
VIEW A
ROTATED 90 CCW
SEATING
PLANE
7
3.5
0
0.15
0.05
Figure 9. 48-Lead Low-Profile Quad Flat Package [LQFP]
(ST-48)
Dimensions are shown in millimeters
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
AD1970JSTZ
1
0C to 70C
48-Lead LQFP
ST-48
AD1970JSTZRL
1
0C to 70C
48-Lead LQFP on 13-inch Reel
ST-48
1
Z = Pb-free part.
AD1970
Rev. 0 | Page 20 of 20
NOTES
Purchase of licensed I
2
C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I
2
C
Patent Rights to use these components in an I
2
C system, provided that the system conforms to the I
2
C Standard Specification as defined by Philips
.
2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D0550004/05(0)
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