AD5061 Fully Accurate 16-Bit VOUT nanoDAC SPI Interface 2.7 V to 5.5 V, in an SOT-23 Data Sheet (Rev. 0)
Fully Accurate 16-Bit V
OUT
nanoDAC
TM
SPI Interface 2.7 V to 5.5 V, in an SOT-23
AD5061
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
2005 Analog Devices, Inc. All rights reserved.
FEATURES
Single 16-bit DAC, 4 LSB INL
Power-on reset to midscale or zero-scale
Guaranteed monotonic by design
3 power-down functions
Low power serial Interface with Schmitt-triggered inputs
Small, 8-lead SOT-23 package, low power
Fast settling time of 4 s typically
2.7 V to 5.5 V power supply
Low glitch on power-up
SYNC Interrupt facility
APPLICATIONS
Process control
Data acquisition systems
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
FUNCTIONAL BLOCK DIAGRAM
AD5061
V
DD
V
OUT
V
REF
POWER-ON
RESET
DAC
REGISTER
DAC
INPUT
CONTROL
LOGIC
POWER-DOWN
CONTROL LOGIC
RESISTOR
NETWORK
REF(+)
SCLK
DIN
04762-
001
SYNC
DACGND
BUF
AGND
OUTPUT
BUFFER
Figure 1.
Table 1. Related Devices
Part No.
Description
AD5062
2.7 V to 5.5 V, 16-bit nanoDAC D/A,
1 LSB INL, SOT-23
AD5063
2.7 V to 5.5 V, 16-bit nanoDAC D/A,
1 LSB INL, MSOP
AD5040/AD5060
2.7 V to 5.5 V, 14-/16-bit nanoDAC D/A,
1 LSB INL, SOT-23
GENERAL DESCRIPTION
The AD5061, a member of ADI's nanoDAC family, is a low
power, single, 16-bit, buffered voltage-out DAC that operates
from a single 2.7 V to 5.5 V supply. The part offers a relative
accuracy specification of 4 LSB and operation is guaranteed
monotonic with a 1 LSB DNL specification. The part uses a
versatile, 3-wire serial interface that operates at clock rates
up to 30 MHz, and is compatible with standard SPI, QSPITM,
MICROWIRETM, and DSP interface standards. The reference for
the AD5061 is supplied from an external V
REF
pin. A reference
buffer is also provided on-chip. The part incorporates a power-
on reset circuit that ensures the DAC output powers up to mid-
scale or zero scale and remains there until a valid write takes
place to the device. The part contains a power-down feature
that reduces the current consumption of the device to typically
300 nA at 5 V and provides software-selectable output loads
while in power-down mode. The part is put into power-down
mode over the serial interface. Total unadjusted error for the
part is <3 mV. This part exhibits very low glitch on power-up.
PRODUCT HIGHLIGHTS
1.
Available in a small 8-lead SOT-23 package.
2.
16-bit accurate, 4 LSB INL.
3.
Low glitch on power-up.
4.
High speed serial interface with clock speeds up to 30 MHz.
5.
Three power-down modes available to the user.
6.
Reset to known output voltage (midscale or zero scale).
AD5061
Rev. 0 | Page 2 of 20
TABLE OF CONTENTS
Specifications..................................................................................... 3
Timing Characteristics..................................................................... 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. 8
Terminology .................................................................................... 12
Theory of Operation ...................................................................... 13
DAC Architecture....................................................................... 13
Reference Buffer ......................................................................... 13
Power-On to Zero-Scale or Midscale ...................................... 14
Software Reset............................................................................. 14
Power-Down Modes .................................................................. 14
Microprocessor Interfacing....................................................... 14
Applications..................................................................................... 16
Choosing a Reference for the AD5061 .................................... 16
Bipolar Operation Using the AD5061 ..................................... 16
Using AD5061 with a Galvanically-Isolated
Interface Chip ............................................................................. 17
Power Supply Bypassing and Grounding................................ 17
Outline Dimensions ....................................................................... 18
Ordering Guide .......................................................................... 18
REVISION HISTORY
7/05--Revision 0: Initial Version
AD5061
Rev. 0 | Page 3 of 20
SPECIFICATIONS
V
DD
= 5.5 V, V
REF
= 4.096 V @ V
DD
= 5.0 V, R
L
= unloaded, C
L
= 22 pF to GND; T
MIN
to T
MAX
, unless otherwise specified.
Table 2.
A, B Grade
1
Parameter Min
Typ
Max
Unit
Test
Conditions/Comments
STATIC PERFORMANCE
Resolution 16
Bits
Relative Accuracy (INL)
0.5
4
LSB
-40C to +85C, B grade
0.5
4
-40C to +125C, Y grade
Total Unadjusted Error (TUE)
0.5
3.0
mV
-40C to +85C, B grade
0.5
3.0
-40C to +125C, Y grade
Differential Nonlinearity (DNL)
0.5
1
LSB
Guaranteed monotonic,
-40C to +85C, B grade
0.5
1
Guaranteed monotonic
-40C to +125C, Y grade
Gain Error
0.01
0.05
% of FSR
T
A
= -40C to +85C, , B grade
0.01
0.05
T
A
= -40C to +125C (Y grade)
Gain Error Temperature Coefficient
1
ppm of FSR/C
Offset Error
0.02
3.0
mV
T
A
= -40C to + 85C, B grade
0.02
3.0
T
A
= -40C to + 125C, Y grade
Offset Error Temperature Coefficient
0.5
V/C
Full-Scale Error
0.05
3.0
mV
All 1s loaded to DAC register, B grade
T
A
= -40C to +85C
0.05
3.0
All 1s loaded to DAC register, Y grade
T
A
= -40C to +125C
OUTPUT CHARACTERISTICS
2
Output Voltage Range
0
V
REF
V Unipolar
operation
Output Voltage Settling Time
4
s
scale to scale code transition to 1LSB.
Output Noise Spectral Density
64
nV/
Hz
DAC code = midscale, 1 kHz
Output Voltage Noise
6
V p-p
DAC code = midscale , 0.1 to 10 Hz bandwidth
Digital-to-Analog Glitch Impulse
2
nV-s
1 LSB change around major carry, R
L
= 5 K
Digital Feedthrough
0.003
nV-s
DAC code = Fullscale
DC Output Impedance (Normal)
8
k
Output impedance tolerance 10%
DC Output Impedance (Power-Down)
(Output Connected to 1 k Network)
1
k
Output impedance tolerance 20
(Output Connected to 100 k
Network)
100
k
Output impedance tolerance 400
REFERENCE INPUT/OUTPUT
V
REF
Input Range
3
2 V
DD
- 50
mV
Input Current (Power-Down)
0.1
A
Zero-scale
loaded
Input Current (Normal)
0.5
A
DC Input Impedance
1
M
LOGIC INPUTS
Input Current
4
1
5 A
V
IL
, Input Low Voltage
0.8
V
V
DD
= 4.5 V to 5.5 V
0.8
V
DD
= 2.7 V to 3.6 V
V
IH
, Input High Voltage
2.0
V
V
DD
= 2.7 V to 5.5 V
1.8
V
DD
= 2.7 V to 3.6 V
Pin Capacitance
4
pF
AD5061
Rev. 0 | Page 4 of 20
A, B Grade
1
Parameter Min
Typ
Max
Unit
Test
Conditions/Comments
POWER REQUIREMENTS
V
DD
2.7
5.5
V
All digital inputs at 0 V or V
DD
I
DD
(Normal Mode)
DAC active and excluding load current
V
DD
= 2.7 V to 5.5 V
1.0
0.89
1.2 mA
V
IN
= V
DD
and V
IL
= GND, V
DD
= 5.5 V,
V
REF
= 4.096 V, code = midscale
V
IN
= V
DD
and V
IL
= GND, V
DD
= 3.0 V,
V
REF
= 4.096 V, code = midscale
I
DD
(All Power-Down Modes)
V
DD
= 2.5 V to 5.5 V
0.265
1 A
V
IH
= V
DD
and V
IL
= GND, V
DD
= 5.5 V,
V
REF
= 4.096 V, code = midscale
V
IH
= V
DD
and V
IL
= GND, V
DD
= 3.0 V,
V
REF
= 4.096 V, code = midscale
1
Temperature range for the B grade: -40C to +85C, typical at 25C; temperature range for the Y grade: -40C to +125C.
2
Guaranteed by design and characterization, not production tested.
3
The typical output supply headroom performance for various reference voltages can be seen in Figure 27.
4
Total current flowing into all pins.
AD5061
Rev. 0 | Page 5 of 20
TIMING CHARACTERISTICS
V
DD
= 2.7 V to 5.5 V; all specifications T
MIN
to T
MAX
, unless otherwise specified.
Table 3.
Parameter Limit
1
Unit Test
Conditions/Comments
t
1
2
33
ns min
SCLK cycle time
t
2
5
ns min
SCLK high time
t
3
3
ns min
SCLK low time
t
4
10 ns
min
SYNC to SCLK falling edge set-up time
t
5
3
ns min
Data set-up time
t
6
2
ns min
Data hold time
t
7
0 ns
min
SCLK falling edge to SYNC rising edge
t
8
12 ns
min
Minimum SYNC high time
t
9
9 ns
min
SYNC rising edge to next SCLK fall ignore
1
All input signals are specified with tr = tf = 1 ns/V (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2.
2
Maximum SCLK frequency is 30 MHz.
t
4
t
3
t
2
t
5
t
7
t
6
D0
D1
D2
D22
D23
SYNC
SCLK
04762-002
t
9
t
1
t
8
D23
D22
DIN
Figure 2. Timing Diagram
AD5061
Rev. 0 | Page 6 of 20
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter Rating
V
DD
to GND
-0.3 V to +7.0 V
Digital Input Voltage to GND
-0.3 V to V
DD
+ 0.3 V
V
OUT
to GND
-0.3 V to V
DD
+ 0.3 V
V
REF
to GND
-0.3 V to V
DD
+ 0.3 V
Operating Temperature Range
Industrial (B grade)
-40C to + 85C
Extended Automotive Temperature
Range (Y Grade)
-40C to +125C
Storage Temperature Range
-65C to +150C
Maximum Junction Temperature
150C
SOT-23 Package
Power Dissipation
(T
J
max - T
A
)/
JA
JA
Thermal Impedance
206C/W
Jc
Thermal Impedance
44C/W
Reflow Soldering (Pb-Free)
Peak Temperature
260C
Time-at-Peak Temperature
10 sec to 40 sec
ESD 1.5
kV
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
This device is a high performance integrated circuit with an
ESD rating of <2 kV, and is ESD-sensitive. Proper precautions
should be taken for handling and assembly.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
AD5061
Rev. 0 | Page 7 of 20
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AD5061
TOP VIEW
(Not to Scale)
V
OUT
SYNC
1
8
AGND
SCLK
2
7
DIN
DACGND
3
6
04762-003
V
REF
4
5
V
DD
Figure 3. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
Description
1 DIN Serial Data Input. This device has a 24-bit shift register. Data is clocked into the register on the falling edge of the
serial clock input.
2
V
DD
Power Supply Input. These parts can be operated from 2.7 V to 5.5 V and V
DD
should be decoupled to GND.
3
VREF
Reference Voltage Input.
4 V
OUT
Analog Output Voltage from DAC.
5
AGND
Ground Reference Point for Analog Circuitry.
6
DACGND
Ground Input to the DAC.
7
SYNC
Level-Triggered Control Input (Active Low). This is the frame synchronization signal for the input data. When SYNC
goes low, it enables the input shift register, and data is transferred in on the falling edges of the following clocks.
The DAC is updated following the 24th clock cycle unless SYNC is taken high before this edge, in which case the
rising edge of SYNC acts as an interrupt, and the write sequence is ignored by the DAC.
8 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can
be transferred at rates up to 30 MHz.
AD5061
Rev. 0 | Page 8 of 20
TYPICAL PERFORMANCE CHARACTERISTICS
04762-004
160
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
60160
50160
40160
30160
20160
10160
INL E
R
ROR (LS
B
)
DAC CODE
T
A
= 25
C
V
DD
= 5V, V
REF
= 4.096V
Figure 4. Typical INL Plot
04762-005
160
0.16
0.14
0.12
0.10
0.08
0.06
0.04
0.02
0
0.02
0.04
0.06
0.08
0.10
0.12
0.14
0.16
60160
50160
40160
30160
20160
10160
TUE
E
RROR (mV
)
DAC CODE
T
A
= 25
C
V
DD
= 5V, V
REF
= 4.096V
Figure 5. Typical TUE Plot
04762-006
160
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
60160
50160
40160
30160
20160
10160
DNL E
R
ROR (LS
B
)
DAC CODE
T
A
= 25
C
V
DD
= 5V, V
REF
= 4.096V
Figure 6. Typical DNL Plot
04762-007
40
20
0
20
40
60
80
100
120
1.2
1.0
0.8
0.6
0.4
0.2
0
0.2
0.4
0.6
0.8
1.0
1.2
140
DNL E
RROR (LS
B
)
TEMPERATURE (
C)
V
DD
= 5.5V, V
REF
= 4.096V
V
DD
= 2.7V, V
REF
= 2.0V
MAX DNL ERROR @ V
DD
= 2.7V
MAX DNL ERROR @ V
DD
= 5.5V
MIN DNL ERROR @ V
DD
= 2.7V
MIN DNL ERROR @ V
DD
= 5.5V
Figure 7. DNL vs. Temperature
04762-008
40
20
0
20
40
60
80
100
120
1.2
1.0
0.8
0.6
0.4
0.2
0
0.2
0.4
0.6
0.8
1.0
1.2
140
TUE
E
RROR (mV
)
TEMPERATURE (
C)
V
DD
= 5.5V, V
REF
= 4.096V
V
DD
= 2.7V, V
REF
= 2.0V
MAX TUE ERROR @ V
DD
= 2.7V
MAX TUE ERROR @ V
DD
= 5.5V
MIN TUE ERROR @ V
DD
= 5.5V
MIN TUE ERROR @ V
DD
= 2.7V
Figure 8. TUE vs. Temperature
04762-090
40
20
0
20
40
60
80
100
120
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
140
INL E
RROR (LS
B
)
TEMPERATURE (
C)
V
DD
= 5.5V, V
REF
= 4.096V
V
DD
= 2.7V, V
REF
= 2.0V
MAX INL ERROR @ V
DD
= 2.7V
MAX INL ERROR @ V
DD
= 5.5V
MIN INL ERROR @ V
DD
= 5.5V
MIN INL ERROR @ V
DD
= 2.7V
Figure 9. INL vs. Temperature
AD5061
Rev. 0 | Page 9 of 20
04762-010
2.0
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
5.5
5.0
4.5
4.0
3.5
3.0
2.5
DNL E
RROR (LS
B
)
REFERENCE VOLTAGE (V)
MAX DNL ERROR @ V
DD
= 5.5V
MIN DNL ERROR @ V
DD
= 5.5V
T
A
= 25
C
Figure 10. DNL vs. Reference Input Voltage
04762-011
2.0
1.2
1.0
0.8
0.6
0.4
0.2
0
0.2
0.4
0.6
0.8
1.0
1.2
5.5
5.0
4.5
4.0
3.5
3.0
2.5
TUE
E
RROR (mV
)
REFERENCE VOLTAGE (V)
MAX INL ERROR @ V
DD
= 5.5V
MIN INL ERROR @ V
DD
= 5.5V
T
A
= 25
C
Figure 11. TUE vs. Reference Input Voltage
04762-009
2.0
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
5.5
5.0
4.5
4.0
3.5
3.0
2.5
INL E
RROR (LS
B
)
REFERENCE VOLTAGE (V)
MAX INL ERROR @ V
DD
= 5.5V
MIN INL ERROR @ V
DD
= 5.5V
T
A
= 25
C
Figure 12. INL vs. Reference Input Voltage
04762-013
40
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
140
120
100
80
60
40
20
0
20
S
U
P
P
L
Y
CURRE
NT (mA)
TEMPERATURE (
C)
V
DD
= 5.5V, V
REF
= 4.096V
V
DD
= 2.7V, V
REF
= 2.0V
CODE = FULL-SCALE
V
DD
= 5.5V
V
DD
= 2.7V
Figure 13. Supply Current vs. Temperature
04762-014
0
0
3.00
2.75
2.50
2.25
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
70000
60000
50000
40000
30000
20000
10000
I
DD
(mA)
DAC CODE
V
DD
= 3.0V, V
REF
= 2.5V
V
DD
= 5.5V, V
REF
= 4.096V
T
A
= 25
C
Figure 14. Supply Current vs. Digital Input Code
04762-015
2.5
0
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
6.0
5.5
5.0
4.5
4.0
3.5
3.0
S
U
P
P
LY
CURRE
NT (mA)
SUPPLY VOLTAGE (V)
V
REF
= 2.5V
T
A
= 25
C
CODE = MIDSCALE
Figure 15. Supply Current vs. Supply Voltage
AD5061
Rev. 0 | Page 10 of 20
04762-012
40
0.6
0.4
0.2
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
140
120
100
80
60
40
20
0
20
OFFS
E
T E
RROR (mV
)
TEMPERATURE (
C)
V
DD
= 5.5V, V
REF
= 4.096V
V
DD
= 2.7V, V
REF
= 2.0V
OFFSET ERROR @ V
DD
= 5.5V
OFFSET ERROR @ V
DD
= 2.7V
Figure 16. Offset vs. Temperature
04762-017
CH2 50mV/DIV
CH1 2V/DIV
TIME BASE 400ns/DIV
24TH CLOCK FALLING
CH1 = SCLK
CH2 = V
OUT
Figure 17. Digital-to-Analog Glitch Impulse; See Figure 21
0
50
100
150
200
250
300
1000
10000
100000
1000000
FREQUENCY (Hz)
N
OISE SPEC
TR
A
L
D
E
N
S
ITY (
n
v/ H
z
)
V
DD
= 5V
T
A
= 25C
V
REF
= 4.096V
FULL SCALE
MIDSCALE
ZERO SCALE
100
04762-018
Figure 18. Output Noise Spectral Density
04762-019
CH2 2V/DIV
CH1 2V/DIV
TIME BASE = 5.00
s
CH3 2V
CH2 = V
OUT
CH1 = TRIGGER
CH3 = SCLK
Figure 19. Exiting Power-Down
04762-020
V
DD
= 3V
DAC= FULL SCALE
V
REF
= 2.7V
T
A
= 25C
Y AXIS = 2
V/DIV
X AXIS = 4s/DIV
Figure 20. 0.1 Hz to 10 Hz Noise Plot
04762-021
50
100
150
200
250
300
350
400
450
500
0
SAMPLES
AMP
LITUDE
(2
0
0
V/D
IV)
V
DD
= 5V
V
REF
= 4.096
T
A
= 25C
10ns/SAMPLE
Figure 21. Glitch Energy
AD5061
Rev. 0 | Page 11 of 20
04762-025
CH1 2V/DIV CH2 1V/DIV TIME BASE = 100
s
V
DD
= 5V V
REF
= 4.096V
DD
RAMP RATE = 200
s
T
A
= 25C
CH1 = V
DD
CH2 = V
OUT
04762-022
40
20
0.10
0.10
0.08
0.06
0.04
0.02
0
0.02
0.04
0.06
0.08
140
120
100
80
60
40
20
0
GAIN E
RROR (%FS
R)
TEMPERATURE (
C)
V
DD
= 5.5V, V
REF
= 4.096V
V
DD
= 2.7V, V
REF
= 2.0V
GAIN ERROR @ V
DD
= 2.7V
GAIN ERROR @ V
DD
= 5.5V
Figure 22. Gain Error vs. Temperature
Figure 25. Hardware Power-Down Glitch
04762-026
CH1 2V/DIV CH2 2V/DIV CH3 20mV/DIV CH4 2V/DIV
TIME BASE 1
s/DIV
CH3 = V
OUT
CH4 = TRIGGER
CH2 = SYNC
CH1 = SCLK
V
DD
= 5V V
REF
= 4.096V
DD
T
A
= 25C
04762-023
0.83
0.84
0.85
0.86
0.87
0.88
0.89
0.90
0.91
0
16
14
12
10
8
6
4
2
MORE
FRE
Q
UE
NCY
BIN
Figure 26. Exiting Software Power-Down to Glitch
Figure 23. I
DD
Histogram @ V
DD
= 3 V
04762-091
2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1
0
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
5.5
5.3
HE
ADROOM (V
)
REFERENCE VOLTAGE (V)
04762-024
1.00 1.01 1.02 1.03 1.04 1.05 1.06 1.07 1.08 1.09 1.10 1.11
0
14
12
10
8
6
4
2
MORE
FRE
Q
UE
NCY
BIN
Figure 27. V
DD
Headroom vs. Reference Voltage
Figure 24. I
DD
Histogram @ V
DD
= 5 V
AD5061
Rev. 0 | Page 12 of 20
TERMINOLOGY
Relative Accuracy
For the DAC, relative accuracy or integral nonlinearity (INL) is
a measure of the maximum deviation, in LSBs, from a straight
line passing through the endpoints of the DAC transfer
function. A typical INL vs. code plot is shown in Figure 4.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of 1 LSB maximum
ensures monotonicity. This DAC is guaranteed monotonic by
design. A typical DNL vs. code plot is shown in Figure 7.
Zero-Code Error
Zero-code error is a measure of the output error when zero
code (0x0000) is loaded to the DAC register. Ideally, the output
should be 0 V. The zero-code error is always positive in the
AD5061 because the output of the DAC cannot go below 0 V.
This is due to a combination of the offset errors in the DAC and
output amplifier. Zero-code error is expressed in mV.
Full-Scale Error
Full-scale error is a measure of the output error when full-scale
code (0xFFFF) is loaded to the DAC register. Ideally, the output
should be V
DD
- 1 LSB. Full-scale error is expressed in percent
of full-scale range.
Gain Error
This is a measure of the span error of the DAC. It is the devia-
tion in slope of the DAC transfer characteristic from ideal
expressed as a percent of the full-scale range.
Total Unadjusted Error (TUE)
Total unadjusted error is a measure of the output error taking
all the various errors into account. A typical TUE vs. code plot
is shown in Figure 5.
Zero-Code Error Drift
This is a measure of the change in zero-code error with a
change in temperature. It is expressed in V/C.
Gain Error Drift
This is a measure of the change in gain error with changes in
temperature. It is expressed in (ppm of full-scale range)/C.
Digital-to-Analog Glitch Impulse
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nV-s
and is measured when the digital input code is changed by
1 LSB at the major carry transition; see Figure 17 and Figure 21.
The expanded view in Figure 17 shows the glitch generated
following completion of the calibration routine; Figure 21
zooms in on this glitch.
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into
the analog output of the DAC from the digital inputs of the
DAC, but is measured when the DAC output is not updated. It
is specified in nV-s and measured with a full-scale code change
on the data bus; that is, from all 0s to all 1s, and vice versa.
AD5061
Rev. 0 | Page 13 of 20
THEORY OF OPERATION
The AD5061 is a single 16-bit, serial input, voltage output DAC.
It operates from supply voltages of 2.7 V to 5.5 V. Data is writ-
ten to the AD5061 in a 24-bit word format, via a 3-wire serial
interface.
The AD5061 incorporates a power-on reset circuit that ensures
the DAC output powers up to zero-scale or midscale. The
device also has a software power-down mode pin that reduces
the typical current consumption to less than 1 A.
DAC ARCHITECTURE
The DAC architecture of the AD5061 consists of two matched
DAC sections. A simplified circuit diagram is shown in
Figure 28. The four MSBs of the 16-bit data word are decoded
to drive 15 switches, E1 to E15. Each of these switches connects
one of 15 matched resistors to either DACGND or V
REF
buffer
output.
The remaining 12 bits of the data word drive switches
S0 to S11 of a 12-bit voltage mode R-2R ladder network.
2R
047762-
027
S0
V
REF
2R
S1
2R
S11
2R
E1
2R
E2
2R
E15
2R
V
OUT
12-BIT R-2R LADDER
FOUR MSBs DECODED INTO
15 EQUAL SEGMENTS
Figure 28. DAC Ladder Structure
REFERENCE BUFFER
The AD5061 operates with an external reference. The reference
input (V
REF
) has an input range of 2 V to V
DD
- 50 mV. This
input voltage is then used to provide a buffered reference for the
DAC core.
SERIAL INTERFACE
The AD5061 has a 3-wire serial interface (SYNC, SCLK, and
DIN), which is compatible with SPI, QSPI, and MICROWIRE
interface standards, as well as most DSPs. See Figure 2 for a
timing diagram of a typical write sequence.
The write sequence begins by bringing the SYNC line low. Data
from the DIN line is clocked into the 24-bit shift register on the
falling edge of SCLK. The serial clock frequency can be as high
as 30 MHz, making these parts compatible with high speed
DSPs. On the 24th falling clock edge, the last data bit is clocked
in and the programmed function is executed (that is, a change
in the DAC register contents and/or a change in the mode of
operation).
At this stage, the SYNC line may be kept low or be brought
high. In either case, it must be brought high for a minimum of
33 ns before the next write sequence so that a falling edge of
SYNC can initiate the next write sequence. Because the SYNC
buffer draws more current when V
IN
= 1.8 V than it does when
V
IN
= 0.8 V, SYNC should be idled low between write sequences
for an even lower power operation of the part. As previously
indicated, however, it must be brought high again just before
the next write sequence.
Input Shift Register
The input shift register is 24 bits wide; see Figure 29. PD1 and
PD0 are control bits that control which mode of operation the
part is in (normal mode or any one of three power-down
modes). There is a more complete description of the various
modes in the Power-Down Modes section. The next 16 bits are
the data bits. These are transferred to the DAC register on the
24th falling edge of SCLK.
SYNC Interrupt
In a normal write sequence, the SYNC line is kept low for at
least 24 falling edges of SCLK and the DAC is updated on the
24th falling edge. However, if SYNC is brought high before the
24th falling edge, this acts as an interrupt to the write sequence.
The shift register is reset and the write sequence is seen as
invalid. Neither an update of the DAC register contents nor a
change in the operating mode occurs; see Figure 32.
DATA BITS
DB15 (MSB)
DB0 (LSB)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
NORMAL OPERATION
1k
TO GND
100k
TO GND
3-STATE
POWER-DOWN MODES
0
0
1
1
0
1
0
1
04762-
028
0
0
0
0
0
0
PD1
PD0
Figure 29. Input Register Contents
AD5061
Rev. 0 | Page 14 of 20
POWER-ON TO ZERO-SCALE OR MIDSCALE
The AD5061 contains a power-on reset circuit that controls the
output voltage during power-up. The DAC register is filled with
the zero-scale or midscale code and the output voltage is zero-
scale or midscale. It remains there until a valid write sequence is
made to the DAC. This is useful in applications where it is
important to know the state of the output of the DAC while it is
in the process of powering up.
SOFTWARE RESET
The device can be put into software reset by setting all bits in
the DAC register to 1; this includes writing 1s to Bit D23 to
Bit D16, which is not the normal mode of operation. Note that
the SYNC interrupt command cannot be performed if a
software reset command is started.
POWER-DOWN MODES
The AD5061 contains four separate modes of operation. These
modes are software-programmable by setting two bits (DB17
and DB16) in the control register. Table 6 shows how the state
of the bits corresponds to the mode of operation of the device.
Table 6. Modes of Operation
DB17 DB16 Operating
Mode
0 0 Normal
operation
Power-down
mode:
0 1
3-state
1 0
100 K
to GND
1 1
1 k
to GND
When both bits are set to 0, the part works normally with its
normal power consumption. However, for the three power-
down modes, the supply current falls to less than 1A at 5 V
(200 nA at 3 V). Not only does the supply current fall, but the
output stage is also internally switched from the output of the
amplifier to a resistor network of known values. This has the
advantage that the output impedance of the part is known while
the part is in power-down mode. There are three different
options. The output is connected internally to GND through a 1
k resistor or a 100 K resistor, or it is left open-circuited (3-
state). The output stage is illustrated in Figure 30.
POWER-DOWN
CIRCUITRY
AD5061
DAC
04762-029
V
OUT
RESISTOR
NETWORK
OUTPUT
BUFFER
Figure 30. Output Stage During Power-Down
The bias generator, the DAC core and other associated linear
circuitry are all shut down when the power-down mode is
activated. However, the contents of the DAC register are
unaffected when in power-down. The time to exit power-down
is typically 2.5 s for V
DD
= 5 V, and 5 s for V
DD
= 3 V;
see Figure 19.
MICROPROCESSOR INTERFACING
AD5061-to-ADSP-2101/ADSP-2103 Interface
Figure 31 shows a serial interface between the AD5061 and the
ADSP-2101/ADSP-2103. The ADSP-2101/ADSP-2103 should
be set up to operate in the SPORT transmit alternate framing
mode. The ADSP-2101/ADSP-2103 SPORT is programmed
through the SPORT control register and should be configured
as follows: internal clock operation, active low framing, 16-bit
word length. Transmission is initiated by writing a word to the
Tx register after the SPORT has been enabled.
AD5061
1
ADDITIONAL PINS OMITTED FOR CLARITY
TFS
DT
SCLK
SYNC
DIN
SCLK
04762-030
ADSP-2101/
ADSP-2103
1
Figure 31. AD5061-to-ADSP-2101/ADSP-2103 Interface
04762-031
DB23
DB23
DB0
DB0
INVALID WRITE SEQUENCE:
SYNC HIGH BEFORE 24
TH
FALLING EDGE
VALID WRITE SEQUENCE, OUTPUT UPDATES
ON THE 24
TH
FALLING EDGE
SYNC
SCLK
DIN
Figure 32. SYNC Interrupt Facility
AD5061
Rev. 0 | Page 15 of 20
AD5061-to-68HC11/68L11 Interface
Figure 33 shows a serial interface between the AD5061 and the
68HC11/68L11 microcontroller. SCK of the 68HC11/68L11
drives the SCLK pin of the AD5061, while the MOSI output
drives the serial data line of the DAC. The SYNC signal is
derived from a port line (PC7). The set-up conditions for
correct operation of this interface require that the 68HC11/
68L11 be configured so that its CPOL bit is 0 and its CPHA bit
is 1. When data is being transmitted to the DAC, the SYNC line
is taken low (PC7). When the 68HC11/68L11 is configured
where its CPOL bit is 0 and its CPHA bit is 1, data appearing on
the MOSI output is valid on the falling edge of SCK. Serial data
from the 68HC11/68L11 is transmitted in 8-bit bytes with only
eight falling clock edges occurring in the transmit cycle. Data is
transmitted MSB first. To load data to the AD5061, PC7 is left
low after the first eight bits are transferred, a second serial write
operation is performed to the DAC, and PC7 is taken high at
the end of this procedure.
AD5061
1
1
ADDITIONAL PINS OMITTED FOR CLARITY
PC7
SCK
MOSI
SYNC
SCLK
DIN
04762-032
68HC11/
68L11
1
Figure 33. AD5061-to-68HC11/68L11 Interface
AD5061-to-Blackfin ADSP-BF53x Interface
Figure 34 shows a serial interface between the AD5061 and the
Blackfin ADSP-53x microprocessor. The ADSP-BF53x proces-
sor family incorporates two dual-channel synchronous serial
ports, SPORT1 and SPORT0, for serial and multiprocessor
communications. Using SPORT0 to connect to the AD5061,
the setup for the interface is: DT0PRI drives the SDIN pin of
the AD5061, while TSCLK0 drives the SCLK of the part; the
SYNC is driven from TFS0.
ADSP-BF53x
1
AD5061
1
1
ADDITIONAL PINS OMITTED FOR CLARITY
DT0PRI
TSCLK0
TFS0
DIN
SCLK
SYNC
04762-033
Figure 34. AD5061-to-Blackfin ADSP-BF53x Interface
AD5061-to-80C51/80L51 Interface
Figure 35 shows a serial interface between the AD5061 and the
80C51/80L51 microcontroller. The setup for the interface is:
TxD of the 80C51/80L51 drives SCLK of the AD5061 while
RxD drives the serial data line of the part. The SYNC signal is
again derived from a bit-programmable pin on the port. In this
case, Port Line P3.3 is used. When data is to be transmitted to
the AD5061, P3.3 is taken low. The 80C51/80L51 transmits data
only in 8-bit bytes; thus only eight falling clock edges occur in
the transmit cycle. To load data to the DAC, P3.3 is left low after
the first eight bits are transmitted, and a second write cycle is
initiated to transmit the second byte of data. P3.3 is taken high
following the completion of this cycle. The 80C51/80L51 out-
puts the serial data in a format which has the LSB first. The
AD5061 requires its data with the MSB as the first bit received.
The 80C51/80L51 transmit routine should take this into account.
80C51/80L51
1
AD5061
1
1
ADDITIONAL PINS OMITTED FOR CLARITY
P3.3
TxD
RxD
SYNC
SCLK
DIN
04762-034
Figure 35. AD5061-to-80C51/80L51 Interface
AD5061-to-MICROWIRE Interface
Figure 36 shows an interface between the AD5061 and any
MICROWIRE-compatible device. Serial data is shifted out on
the falling edge of the serial clock and is clocked into the
AD5061 on the rising edge of the SK.
MICROWIRE
1
AD5061
1
1
ADDITIONAL PINS OMITTED FOR CLARITY
CS
SK
SO
SYNC
SCLK
DIN
04762-035
Figure 36. AD5061-to-MICROWIRE Interface
AD5061
Rev. 0 | Page 16 of 20
APPLICATIONS
CHOOSING A REFERENCE FOR THE AD5061
To achieve the optimum performance from the AD5061,
thought should be given to the choice of a precision voltage
reference. The AD5061 has just one reference input, V
REF
. The
voltage on the reference input is used to supply the positive
input to the DAC. Therefore, any error in the reference is
reflected in the DAC.
There are four possible sources of error when choosing a vol-
tage reference for high accuracy applications: initial accuracy,
ppm drift, long-term drift, and output voltage noise. Initial
accuracy on the output voltage of the DAC leads to a full-scale
error in the DAC. To minimize these errors, a reference with
high initial accuracy is preferred. Also, choosing a reference
with an output trim adjustment, such as the ADR43x family,
allows a system designer to trim out system errors by setting a
reference voltage to a voltage other than the nominal. The trim
adjustment can also be used at the operating temperature to
trim out any errors.
Because the supply current required by the AD5061 is
extremely low, the parts are ideal for low supply applications.
The ADR395 voltage reference is recommended. This requires
less than 100 A of quiescent current and can, therefore, drive
multiple DACs in one system, if required. It also provides very
good noise performance at 8 V p-p in the 0.1 Hz to 10 Hz range.
AD5061
SYNC
SCLK
DIN
7V
5V
V
OUT
= 0V TO 5V
ADR395
04762-036
3-WIRE
SERIAL
INTERFACE
Figure 37. ADR395 as Reference to the AD5061
Long-term drift is a measure of how much the reference drifts
over time. A reference with a tight long-term drift specification
ensures that the overall solution remains relatively stable during
its entire lifetime. The temperature coefficient of a reference's
output voltage affects INL, DNL, and TUE. A reference with a
tight temperature coefficient specification should be chosen to
reduce temperature dependence of the DAC output voltage on
ambient conditions.
In high accuracy applications, which have a relatively low noise
budget, reference output voltage noise needs to be considered. It
is important to choose a reference with as low an output noise
voltage as practical for the system noise resolution required.
Precision voltage references, such as the ADR435, produce low
output noise in the 0.1 Hz to 10 Hz region. Table 7 shows
examples of recommended precision references for use as a
supply to the AD5061.
Table 7. Precision References Part List for the AD5061
Part
No.
Initial
Accuracy
(mV max)
Temperature
Drift
(ppm/C max)
0.1 Hz to 10 Hz
Noise (V p-p typ)
ADR435 2
3
(SO-8)
8
ADR425
2
3 (SO-8)
3.4
ADR02 3
3
(SO-8)
10
ADR02 3
3
(SC70)
10
ADR395 5
9
(TSOT-23)
8
BIPOLAR OPERATION USING THE AD5061
The AD5061 has been designed for single-supply operation, but
a bipolar output range is also possible using the circuit shown in
Figure 38. The circuit shown yields an output voltage range of
5 V. Rail-to-rail operation at the amplifier output is achievable
using an AD820/AD8032 or an OP196/OP295.
The output voltage for any input code can be calculated as
follows:
-
+
=
1
R
2
R
V
1
R
2
R
1
R
D
V
V
DD
DD
O
65536
where D represents the input code in decimal (0 to 65536).
With V
REF
= 5 V, R1 = R2 = 10 k,
V
5
65536
10
-
=
D
V
O
This is an output voltage range of 5 V with 0x0000
corresponding to a -5 V output and 0xFFFF corresponding to a
+5 V output.
AD5061
+5V
10
F
04762-037
R1 = 10k
V
BF
V
OUT
V
REF
0.1
F
3-WIRE
SERIAL
INTERFACE
AD820/
OP295
+
5V
+5V
R2 = 10k
5V
Figure 38. Bipolar Operation with the AD5061
AD5061
Rev. 0 | Page 17 of 20
USING AD5061 WITH A GALVANICALLY-
ISOLATED INTERFACE CHIP
In process control applications in industrial environments, it is
often necessary to use a galvanically-isolated interface to protect
and isolate the controlling circuitry from any hazardous
common-mode voltages that may occur in the area where the
DAC is functioning. iCoupler
provides isolation in excess of
2.5 kV. Because the AD5061 uses a 3-wire serial logic interface,
the ADuM130x family provides an ideal digital solution for the
DAC interface.
The ADuM130x isolators provide three independent isolation
channels in a variety of channel configurations and data rates.
They operate across the full range from 2.7 V to 5.5 V, providing
compatibility with lower voltage systems and enabling a voltage
translation functionality across the isolation barrier.
Figure 39 shows a typical galvanically-isolated configuration
using the AD5061. The power supply to the part also needs to
be isolated; this is accomplished by using a transformer. On the
DAC side of the transformer, a 5 V regulator provides the 5 V
supply required for the AD5061.
0.1
F
10
F
V
DD
GND
POWER
5V
REGULATOR
AD5061
04762-038
ADuM130x
SCLK
V0A
V1A
SCLK
V
OUT
SYNC
V0B
V1B
SDI
DIN
V0C
V1C
DATA
Figure 39. AD5061 with a Galvanically-Isolated Interface
POWER SUPPLY BYPASSING AND GROUNDING
When accuracy is important in a circuit, it is helpful to carefully
consider the power supply and ground return layout on the
board. The printed circuit board containing the AD5061 should
have separate analog and digital sections, each having its own
area of the board. If the AD5061 is in a system where other
devices require an AGND-to-DGND connection, the
connection should be made at one point only. This ground
point should be as close as possible to the AD5061.
The power supply to the AD5061 should be bypassed with
10 F and 0.1 F capacitors. The capacitors should be physically
as close as possible to the device with the 0.1 F capacitor
ideally right up against the device. The 10 F capacitors are the
tantalum bead type. It is important that the 0.1 F capacitor has
low effective series resistance (ESR) and effective series
inductance (ESI), as do common ceramic types of capacitors.
This 0.1 F capacitor provides a low impedance path to ground
for high frequencies caused by transient currents due to internal
logic switching.
The power supply line itself should have as large a trace as
possible to provide a low impedance path and reduce glitch
effects on the supply line. Clocks and other fast switching
digital signals should be shielded from other parts of the board
by digital ground. Avoid crossover of digital and analog signals,
if possible. When traces cross on opposite sides of the board,
ensure that they run at right angles to each other to reduce
feedthrough effects through the board. The best board layout
technique is the microstrip technique where the component
side of the board is dedicated to the ground plane only, and the
signal traces are placed on the solder side. However, this is not
always possible with a 2-layer board.
AD5061
Rev. 0 | Page 18 of 20
OUTLINE DIMENSIONS
1
3
5
6
2
8
4
7
2.90 BSC
1.60 BSC
1.95
BSC
0.65 BSC
0.38
0.22
0.15 MAX
1.30
1.15
0.90
SEATING
PLANE
1.45 MAX
0.22
0.08
0.60
0.45
0.30
8
4
0
2.80 BSC
PIN 1
INDICATOR
COMPLIANT TO JEDEC STANDARDS MO-178-BA
Figure 40. 8-Lead Small Outline Transistor Package [SOT-23]
(RJ-8)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Temperature
Range INL
Description
Package
Description
Package
Option Branding
AD5061BRJZ-1REEL7
1
-40C to +85C
4 LSB
2.7 V to 5.5 V, Reset to 0 V
8 Lead SOT-23
RJ-8
D43
AD5061BRJZ-1500RL7
1
-40C to +85C
4 LSB
2.7 V to 5.5 V, Reset to 0 V
8 Lead SOT-23
RJ-8
D43
AD5061YRJZ-1500RL7
1
-40C to +125C
4 LSB
2.7 V to 5.5 V, Reset to 0 V
8 Lead SOT-23
RJ-8
D6G
AD5061YRJZ-1REEL7
1
-40C to +125C
4 LSB
2.7 V to 5.5 V, Reset to 0 V
8 Lead SOT-23
RJ-8
D6G
EVAL-AD5061EB
Evaluation
Board
1
Z = Pb-free part.
AD5061
Rev. 0 | Page 19 of 20
NOTES
AD5061
Rev. 0 | Page 20 of 20
NOTES
2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D0476207/05(0)
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