256-Position SPI/I
2
C Selectable
Digital Potentiometer
AD5161
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
2003 Analog Devices, Inc. All rights reserved.
FEATURES
256-position
End-to-end resistance 5 k, 10 k, 50 k, 100 k
Compact MSOP-10 (3 mm 4.9 mm) package
Pin selectable SPI/I
2
C compatible interface
Extra package address decode pin AD0
Full read/write of wiper register
Power-on preset to midscale
Single supply 2.7 V to 5.5 V
Low temperature coefficient 45 ppm/C
Low power, I
DD
= 8 A
Wide operating temperature 40C
to +125C
SDO output allows multiple device daisy-chaining
Evaluation board available
APPLICATIONS
Mechanical potentiometer replacement in new designs
Transducer adjustment of pressure, temperature, position,
chemical, and optical sensors
RF amplifier biasing
Automotive electronics adjustment
Gain control and offset adjustment
GENERAL OVERVIEW
The AD5161 provides a compact 3 mm 4.9 mm packaged
solution for 256-position adjustment applications. These devices
perform the same electronic adjustment function as mechanical
potentiometers or variable resistors, with enhanced resolution,
solid-state reliability, and superior low temperature coefficient
performance.
The wiper settings are controllable through a pin selectable SPI
or I
2
C compatible digital interface, which can also be used to
read back the wiper register content. When the SPI mode is
used, the device can be daisy-chained (SDO to SDI), allowing
several parts to share the same control lines. In the I
2
C mode,
address pin AD0 can be used to place up to two devices on the
same bus. In this same mode, command bits are available to
reset the wiper position to midscale or to shut down the device
into a state of zero power consumption.
Operating from a 2.7 V to 5.5 V power supply and consuming
less than 5 A allows for usage in portable battery-operated
applications.
FUNCTIONAL BLOCK DIAGRAM
WIPER
REGISTER
SDI/SDA
CLK/SCL
DIS
CS/AD0
GND
SDO/NC
V
DD
A
W
B
SPI OR I
2
C
INTERFACE
Figure 1.
PIN CONFIGURATION
1
2
3
4
5
10
9
8
7
6
A
B
CS/ADO
SDO/NC
SDI/SDA
DD
AD5161
TOP VIEW
(Not to Scale)
W
V
DIS
GND
CLK/SCL
Figure 2.
Note:
The terms digital potentiometer, VR, and RDAC are used interchangeably.
Purchase of licensed I
2
C components of Analog Devices or one of its sublicensed
Associated Companies conveys a license for the purchaser under the Philips I
2
C
Patent Rights to use these components in an I
2
C system, provided that the system
conforms to the I
2
C Standard Specification as defined by Philips.
AD5161
Rev. 0 | Page 2 of 20
TABLE OF CONTENTS
Electrical Characteristics--5 k Version ...................................... 3
Electrical Characteristics--10 k, 50 k, 100 k Versions ....... 4
Timing Characteristics--5 k, 10 k, 50 k, 100 k Versions 5
Absolute Maximum Ratings
1
.......................................................... 6
Typical Performance Characteristics ............................................. 7
Test Circuits..................................................................................... 11
SPI Interface .................................................................................... 12
I
2
C Interface..................................................................................... 13
Operation......................................................................................... 14
Programming the Variable Resistor ......................................... 14
Programming the Potentiometer Divider ............................... 15
Pin Selectable Digital Interface................................................. 15
Level Shifting for Bidirectional Interface ................................ 17
ESD Protection ........................................................................... 17
Terminal Voltage Operating Range.......................................... 17
Power-Up Sequence ................................................................... 17
Layout and Power Supply Bypassing ....................................... 17
Pin Configuration and Function Descriptions........................... 18
Pin Configuration ...................................................................... 18
Pin Function Descriptions ........................................................ 18
Outline Dimensions ....................................................................... 19
Ordering Guide .......................................................................... 19
ESD Caution................................................................................ 19
REVISION HISTORY
Revision 0: Initial Version
AD5161
Rev. 0 | Page 3 of 20
ELECTRICAL CHARACTERISTICS--5 k VERSION
(V
DD
= 5 V 10%, or 3 V 10%; V
A
= +V
DD
; V
B
= 0 V; 40C < T
A
< +125C; unless otherwise noted.)
Table 1.
Parameter Symbol
Conditions
Min
Typ
1
Max Unit
DC CHARACTERISTICS--RHEOSTAT MODE
Resistor Differential Nonlinearity
2
R-DNL
R
WB
, V
A
= no connect
1.5
0.1
+1.5
LSB
Resistor Integral Nonlinearity
2
R-INL
R
WB
, V
A
= no connect
4
0.75
+4
LSB
Nominal Resistor Tolerance
3
R
AB
T
A
= 25C
30
+30
%
Resistance Temperature Coefficient
R
AB
/T V
AB
= V
DD
, Wiper = no connect
45
ppm/C
Wiper
Resistance
R
W
50
120
DC CHARACTERISTICS--POTENTIOMETER DIVIDER MODE (Specifications apply to all VRs)
Resolution
N
8
Bits
Differential
Nonlinearity
4
DNL
1.5 0.1 +1.5 LSB
Integral
Nonlinearity
4
INL
1.5 0.6 +1.5 LSB
Voltage Divider Temperature Coefficient
V
W
/T
Code = 0x80
15
ppm/C
Full-Scale
Error
V
WFSE
Code = 0xFF
6
2.5
0
LSB
Zero-Scale
Error
V
WZSE
Code = 0x00
0
+2
+6
LSB
RESISTOR
TERMINALS
Voltage
Range
5
V
A,B,W
GND
V
DD
V
Capacitance
6
A, B
C
A,B
f = 1 MHz, measured to GND,
Code = 0x80
45
pF
Capacitance
6
W
C
W
f = 1 MHz, measured to GND,
Code = 0x80
60
pF
Shutdown Supply Current
7
I
DD_SD
V
DD
= 5.5 V
0.01
1
A
Common-Mode
Leakage
I
CM
V
A
= V
B
= V
DD
/2
1
nA
DIGITAL INPUTS AND OUTPUTS
Input Logic High
V
IH
2.4
V
Input Logic Low
V
IL
0.8
V
Input Logic High
V
IH
V
DD
= 3 V
2.1
V
Input Logic Low
V
IL
V
DD
= 3 V
0.6
V
Input
Current
I
IL
V
IN
= 0 V or 5 V
1
A
Input
Capacitance
6
C
IL
5
pF
POWER
SUPPLIES
Power Supply Range
V
DD RANGE
2.7
5.5 V
Supply
Current
I
DD
V
IH
= 5 V or V
IL
= 0 V
3
8
A
Power
Dissipation
8
P
DISS
V
IH
= 5 V or V
IL
= 0 V, V
DD
= 5 V
0.2
mW
Power Supply Sensitivity
PSS
V
DD
= +5 V 10%,
Code = Midscale
0.02 0.05 %/%
DYNAMIC CHARACTERISTICS
6, 9
Bandwidth
3dB
BW_5K R
AB
= 5 k, Code = 0x80
1.2
MHz
Total
Harmonic
Distortion
THD
W
V
A
= 1 V rms, V
B
= 0 V, f = 1 kHz
0.05
%
V
W
Settling Time
t
S
V
A
= 5 V, V
B
= 0 V, 1 LSB error
band
1
s
Resistor Noise Voltage Density
e
N_WB
R
WB
= 2.5 k, RS = 0
6
nV/Hz
AD5161
ELECTRICAL CHARACTERISTICS--10 k, 50 k, 100 k VERSIONS
(V
DD
= 5 V 10%, or 3 V 10%; V
A
= V
DD
; V
B
= 0 V; 40C < T
A
< +125C; unless otherwise noted.)
Table 2.
Parameter Symbol
Conditions
Min
Typ
1
Max
Unit
DC CHARACTERISTICS--RHEOSTAT MODE
Resistor Differential Nonlinearity
2
R-DNL
R
WB
, V
A
= no connect
1
0.1
+1
LSB
Resistor Integral Nonlinearity
2
R-INL
R
WB
, V
A
= no connect
2
0.25
+2
LSB
Nominal Resistor Tolerance
3
R
AB
T
A
= 25C
30
+30
%
Resistance Temperature Coefficient
R
AB
/T
V
AB
= V
DD
,
Wiper = no connect
45
ppm/C
Wiper
Resistance
R
W
V
DD
= 5 V
50
120
DC CHARACTERISTICS--POTENTIOMETER DIVIDER MODE (Specifications apply to all VRs)
Resolution
N
8
Bits
Differential
Nonlinearity
4
DNL
1
0.1
+1
LSB
Integral
Nonlinearity
4
INL
1
0.3
+1
LSB
Voltage Divider Temperature Coefficient
V
W
/T
Code = 0x80
15
ppm/C
Full-Scale
Error
V
WFSE
Code = 0xFF
3
1
0
LSB
Zero-Scale
Error
V
WZSE
Code = 0x00
0
1
3
LSB
RESISTOR TERMINALS
Voltage
Range
5
V
A,B,W
GND
V
DD
V
Capacitance
6
A, B
C
A,B
f = 1 MHz, measured to
GND, Code = 0x80
45
pF
Capacitance
6
W
C
W
f = 1 MHz, measured to
GND, Code = 0x80
60
pF
Shutdown Supply Current
7
I
DD_SD
V
DD
= 5.5 V
0.01
1
A
Common-Mode
Leakage
I
CM
V
A
= V
B
= V
DD
/2
1
nA
DIGITAL INPUTS AND OUTPUTS
Input Logic High
V
IH
2.4
V
Input Logic Low
V
IL
0.8
V
Input Logic High
V
IH
V
DD
= 3 V
2.1
V
Input Logic Low
V
IL
V
DD
= 3 V
0.6
V
Input
Current
I
IL
V
IN
= 0 V or 5 V
1
A
Input
Capacitance
6
C
IL
5
pF
POWER SUPPLIES
Power Supply Range
V
DD RANGE
2.7
5.5 V
Supply
Current
I
DD
V
IH
= 5 V or V
IL
= 0 V
3
8
A
Power
Dissipation
8
P
DISS
V
IH
= 5 V or V
IL
= 0 V,
V
DD
= 5 V
0.2
mW
Power Supply Sensitivity
PSS
V
DD
= +5 V 10%,
Code = Midscale
0.02 0.05
%/%
DYNAMIC CHARACTERISTICS
6, 9
Bandwidth
3dB
BW
R
AB
= 10 k/50 k/100 k,
Code = 0x80
600/100/40
kHz
Total
Harmonic
Distortion
THD
W
V
A
=1 V rms, V
B
= 0 V,
f = 1 kHz, R
AB
= 10 k
0.05 %
V
W
Settling Time (10 k/50 k/100 k)
t
S
V
A
= 5 V, V
B
= 0 V,
1 LSB error band
2
s
Resistor Noise Voltage Density
e
N_WB
R
WB
= 5 k, RS = 0
9
nV/Hz
Rev. 0 | Page 4 of 20
AD5161
TIMING CHARACTERISTICS--5 k, 10 k, 50 k, 100 k VERSIONS
(V
DD
= +5V 10%, or +3V 10%; V
A
= V
DD
; V
B
= 0 V; 40C < T
A
< +125C; unless otherwise noted.)
Table 3.
Parameter Symbol
Conditions
Min
Typ
1
Max Unit
SPI INTERFACE TIMING CHARACTERISTICS
6, 10
(Specifications Apply to All Parts)
Clock
Frequency
f
CLK
25 MHz
Input Clock Pulsewidth
t
CH
, t
CL
Clock level high or low
20
ns
Data Setup Time
t
DS
5
ns
Data Hold Time
t
DH
5
ns
CS Setup Time
t
CSS
15
ns
CS High Pulsewidth
t
CSW
40
ns
CLK Fall to CS Fall Hold Time
t
CSH0
0
ns
CLK Fall to CS Rise Hold Time
t
CSH1
0
ns
CS Rise to Clock Rise Setup
t
CS1
10
ns
I
2
C INTERFACE TIMING CHARACTERISTICS
6, 11
(Specifications Apply to All Parts)
SCL Clock Frequency
f
SCL
400
kHz
t
BUF
Bus Free Time between STOP and START
t
1
1.3
s
t
HD;STA
Hold Time (Repeated START)
t
2
After this period, the first clock pulse is
generated.
0.6
s
t
LOW
Low Period of SCL Clock
t
3
1.3
s
t
HIGH
High Period of SCL Clock
t
4
0.6
50
s
t
SU;STA
Setup Time for Repeated START Condition
t
5
0.6
s
t
HD;DAT
Data Hold Time
t
6
0.9
s
t
SU;DAT
Data Setup Time
t
7
100
ns
t
F
Fall Time of Both SDA and SCL Signals
t
8
300
ns
t
R
Rise Time of Both SDA and SCL Signals
t
9
300
ns
t
SU;STO
Setup Time for STOP Condition
t
10
0.6
s
NOTES
1
Typical specifications represent average readings at +25C and V
DD
= 5 V.
2
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
3
V
AB
= V
DD
, Wiper (V
W
) = no connect.
4
INL and DNL are measured at V
W
with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = V
DD
and V
B
= 0 V.
DNL specification limits of 1 LSB maximum are guaranteed monotonic operating conditions.
5
Resistor terminals A, B, W have no limitations on polarity with respect to each other.
6
Guaranteed by design and not subject to production test.
7
Measured at the A terminal. The A terminal is open circuited in shutdown mode.
8
P
DISS
is calculated from (I
DD
V
DD
). CMOS logic level inputs result in minimum power dissipation.
9
All dynamic characteristics use V
DD
= 5 V.
10
See timing diagram for location of measured values. All input control voltages are specified with t
R
= t
F
= 2 ns (10% to 90% of 3 V) and timed from a voltage
level of 1.5 V.
11
See timing diagrams for locations of measured values.
Rev. 0 | Page 5 of 20
AD5161
Rev. 0 | Page 6 of 20
ABSOLUTE MAXIMUM RATINGS
1
(T
A
= +25C, unless otherwise noted.)
Table 4
Parameter Value
V
DD
to GND
0.3 V to +7 V
V
A
, V
B
, V
W
to GND
V
DD
I
MAX
1
20
mA
Digital Inputs and Output Voltage to GND
0 V to +7 V
Operating Temperature Range
40C to +125C
Maximum Junction Temperature (T
JMAX
) 150C
Storage Temperature
65C to +150C
Lead Temperature (Soldering, 10 sec)
300C
Thermal Resistance
2
JA
: MSOP-10
200C/W
NOTES
1
Maximum terminal current is bounded by the maximum current handling of
the switches, maximum power dissipation of the package, and maximum
applied voltage across any two of the A, B, and W terminals at a given
resistance.
2
Package power dissipation = (T
JMAX
T
A
)/
JA
.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
AD5161
TYPICAL PERFORMANCE CHARACTERISTICS
CODE (Decimal)
1.0
0.8
0.6
0.4
0.2
0
0.2
0.4
0.6
1.0
32
0
96
64
128
160
192
224
256
RHEOSTAT MODE INL (LSB)
0.8
5V
3V
Figure 3. R-INL vs. Code vs. Supply Voltages
5V
3V
1.0
0.8
0.6
0.4
0.2
0
0.2
0.4
0.6
1.0
RHE
OS
TAT MODE
DNL (LS
B
)
0.8
CODE (Decimal)
32
0
96
64
128
160
192
224
256
Figure 4. R-DNL vs. Code vs. Supply Voltages
_40C
+25C
+85C
+125C
1.0
0.8
0.6
0.4
0.2
0
0.2
0.4
0.6
1.0
P
O
TE
NTIOME
TE
R MODE
INL (LS
B
)
0.8
CODE (Decimal)
32
0
96
64
128
160
192
224
256
Figure 5. INL vs. Code, V
DD
= 5 V
CODE (Decimal)
1.0
0.8
0.6
0.4
0.2
0
0.2
0.4
0.6
1.0
32
0
96
64
128
160
192
224
256
P
O
TE
NTIOME
TE
R MODE
DNL (LS
B
)
0.8
40C
+25C
+85C
+125C
Figure 6. DNL vs. Code, V
DD
= 5 V
1.0
0.8
0.6
0.4
0.2
0
0.2
0.4
0.6
1.0
P
O
TE
NTIOME
TE
R MODE
INL (LS
B
)
0.8
CODE (Decimal)
32
0
96
64
128
160
192
224
256
5V
3V
Figure 7. INL vs. Code vs. Supply Voltages
5V
3V
CODE (Decimal)
1.0
0.8
0.6
0.4
0.2
0
0.2
0.4
0.6
0.8
32
0
96
64
128
160
192
224
256
P
O
TE
NTIOME
TE
R MODE
DNL(LS
B
)
1.0
Figure 8. DNL vs. Code vs. Supply Voltages
Rev. 0 | Page 7 of 20
AD5161
Rev. 0 | Page 8 of 20
1.0
0.8
0.6
0.4
0.2
0
0.2
0.4
0.6
1.0
RHEOSTAT M
O
DE INL (LSB)
0.8
CODE (Decimal)
32
0
96
64
128
160
192
224
256
C
+25C
+85C
+125C
40
Figure 9. R-INL vs. Code, V
DD
= 5 V
1.0
0.8
0.6
0.4
0.2
0
0.2
0.4
0.6
1.0
RHE
OS
TAT MODE
DNL (LS
B
)
0.8
CODE (Decimal)
32
0
96
64
128
160
192
224
256
_40C
+25C
+85C
+125C
Figure 10. R-DNL vs. Code, V
DD
= 5 V
TEMPERATURE (C)
0
40
80
120
40
0
1.5
FSE, FU
LL-
SC
A
L
E ER
R
O
R
(
L
SB
)
0
40
80
120
40
1.0
2.5
V
DD
= 5.5V
V
DD
= 2.7V
2.0
0.5
Figure 11. Full-Scale Error vs. Temperature
0
40
80
120
40
0
1.5
ZS
E
,
ZE
RO-S
CALE
E
RROR (
A)
TEMPERATURE (C)
0
40
80
120
40
1.0
2.5
V
DD
= 5.5V
V
DD
= 2.7V
2.0
0.5
Figure 12. Zero-Scale Error vs. Temperature
TEMPERATURE (C)
0
40
80
120
40
0.1
1
10
I
DD
S
U
P
P
L
Y
CURRE
NT (
A)
V
DD
= 5.5V
V
DD
= 2.7V
Figure 13. Supply Current vs. Temperature
I
A
S
HUTDOWN CURRE
NT (nA)
TEMPERATURE (C)
0
0
70
20
10
30
40
50
60
40
80
120
40
V
DD
= 5V
Figure 14. Shutdown Current vs. Temperature
AD5161
Rev. 0 | Page 9 of 20
CODE (Decimal)
50
0
50
100
150
200
32
0
96
64
128
160
192
224
256
RHEOSTAT MODE TEMPCO
(ppm/C)
Figure 15. Rheostat Mode Tempco R
WB
/T vs. Code
CODE (Decimal)
20
0
20
40
60
80
100
120
140
160
32
0
96
64
128
160
192
224
256
P
O
TE
NTIOME
TE
R MODE
TE
MP
CO
(ppm/C)
Figure 16. Potentiometer Mode Tempco V
WB
/T vs. Code
1k
10k
100k
1M
0
6
12
18
24
30
36
42
48
54
60
0x80
0x40
0x20
0x10
0x08
0x04
0x02
0x01
REF LEVEL
0.000dB
/DIV
6.000dB
MARKER 1 000 000.000Hz
MAG (A/R)
8.918dB
START 1 000.000Hz STOP 1 000 000.000Hz
Figure 17. Gain vs. Frequency vs. Code, R
AB
= 5 k
1k
10k
100k
1M
0
6
12
18
24
30
36
42
48
54
60
0x80
0x40
0x20
0x10
0x08
0x04
0x02
0x01
REF LEVEL
0.000dB
/DIV
6.000dB
MARKER 510 634.725Hz
MAG (A/R)
9.049dB
START 1 000.000Hz STOP 1 000 000.000Hz
Figure 18. Gain vs. Frequency vs. Code, R
AB
= 10 k
1k
10k
100k
1M
0
6
12
18
24
30
36
42
48
54
60
0x80
0x40
0x20
0x10
0x08
0x04
0x02
0x01
REF LEVEL
0.000dB
/DIV
6.000dB
MARKER 100 885.289Hz
MAG (A/R)
9.014dB
START 1 000.000Hz STOP 1 000 000.000Hz
Figure 19. Gain vs. Frequency vs. Code, R
AB
= 50 k
1k
10k
100k
1M
0
6
12
18
24
30
36
42
48
54
60
0x80
0x40
0x20
0x10
0x08
0x04
0x02
0x01
REF LEVEL
0.000dB
/DIV
6.000dB
MARKER 54 089.173Hz
MAG (A/R)
9.052dB
START 1 000.000Hz STOP 1 000 000.000Hz
Figure 20. Gain vs. Frequency vs. Code, R
AB
= 100 k
AD5161
Rev. 0 | Page 10 of 20
10k
100k
1M
10M
5.5
6.0
6.5
7.0
7.5
8.0
8.5
9.0
9.5
10.0
10.5
REF LEVEL
5.000dB
/DIV
0.500dB
START 1 000.000Hz STOP 1 000 000.000Hz
R = 5k
R = 10k
R = 50k
R = 100k
5k
1.026 MHz
10k
511 MHz
50k
101 MHz
100k
54 MHz
Figure 21. 3 dB Bandwidth @ Code = 0x80
FREQUENCY (Hz)
10k
100
100k
1M
1k
0
20
40
60
P
S
RR (dB)
CODE = 0x80, V
A
= V
DD
, V
B
= 0V
PSRR @ V
DD
= 3V DC 10% p-p AC
PSRR @ V
DD
= 5V DC 10% p-p AC
Figure 22. PSRR vs. Frequency
I
DD
(
A)
FREQUENCY (Hz)
10k
800
700
600
500
400
300
900
200
100
100k
1M
10M
0
CODE = 0x55
CODE = 0xFF
V
DD
= 5V
Figure 23. I
DD
vs. Frequency
VW
CLK
Ch 1 200mV
BW
Ch 2 5.00 V
BW
M 100ns A CH2 3.00 V
1
2
Figure 24. Digital Feedthrough
VW
CS
Ch 1 100mV
BW
Ch 2 5.00 V
BW
M 200ns A CH1 152mV
1
2
V
A
= 5V
V
B
= 0V
Figure 25. Midscale Glitch, Code 0x800x7F
VW
CS
Ch 1 5.00V
BW
Ch 2 5.00 V
BW
M 200ns A CH1 3.00 V
1
2
V
A
= 5V
V
B
= 0V
Figure 26. Large Signal Settling Time, Code 0xFF0x00
AD5161
Rev. 0 | Page 11 of 20
TEST CIRCUITS
Figure 27 to Figure 35 illustrate the test circuits that define the
test conditions used in the product specification tables.
V
MS
A
W
B
DUT
V+ = V
DD
1LSB = V+/2
N
V+
Figure 27. Test Circuit for Potentiometer Divider Nonlinearity Error (INL, DNL)
NO CONNECT
I
W
V
MS
A
W
B
DUT
Figure 28. Test Circuit for Resistor Position Nonlinearity Error
(Rheostat Operation; R-INL, R-DNL)
V
MS1
I
W
= V
DD
/R
NOMINAL
V
MS2
V
W
R
W
= [V
MS1
V
MS2
]/I
W
A
W
B
DUT
Figure 29. Test Circuit for Wiper Resistance
V
V
V
V
MS
%
DD
%
PSS (%/%) =
V+ = V
DD
10%
PSRR (dB) = 20 LOG
MS
DD
( )
V
DD
V
A
V
MS
A
W
B
V+
Figure 30. Test Circuit for Power Supply Sensitivity (PSS, PSSR)
OP279
W
5V
B
V
OUT
OFFSET
GND
OFFSET
BIAS
A
DUT
V
IN
Figure 31. Test Circuit for Inverting Gain
B
A
V
IN
OP279
W
5V
V
OUT
OFFSET
GND
OFFSET
BIAS
DUT
Figure 32. Test Circuit for Noninverting Gain
+15V
15V
W
A
2.5V
B
V
OUT
OFFSET
GND
DUT
AD8610
V
IN
Figure 33. Test Circuit for Gain vs. Frequency
W
B
V
SS
TO V
DD
DUT
I
SW
CODE = 0x00
R
SW
=
0.1V
I
SW
0.1V
Figure 34. Test Circuit for Incremental ON Resistance
W
B
V
CM
I
CM
A
NC
GND
NC
V
SS
V
DD
DUT
NC = NO CONNECT
Figure 35. Test Circuit for Common-Mode Leakage current
AD5161
Rev. 0 | Page 12 of 20
SPI INTERFACE
Table 5. AD5161 Serial Data-Word Format
B7 B6 B5 B4 B3 B2 B1 B0
D7 D6 D5 D4 D3 D2 D1 D0
MSB
LSB
2
7
2
0
SDI
CLK
CS
VOUT
1
0
1
0
1
0
1
0
D7
D6
D5
D4
D3
D2
D1
D0
RDAC REGISTER LOAD
Figure 36. AD5161 SPI Interface Timing Diagram
(V
A
= 5 V, V
B
= 0 V, V
W
= V
OUT
)
t
CSHO
t
CSS
t
CL
t
CH
t
DS
t
CSW
t
S
t
CS1
t
CSH1
t
CH
SDI
CLK
CS
VOUT
1
0
1
0
1
0
V
DD
0
1LSB
(DATA IN)
Dx
Dx
Figure 37. SPI Interface Detailed Timing Diagram (V
A
= 5 V, V
B
= 0 V, V
W
= V
OUT
)
AD5161
Rev. 0 | Page 13 of 20
I
2
C INTERFACE
Table 6. Write Mode
S 0 1 0 1 1 0
AD0
W
A X RS SD X X X X X A D7 D6 D5 D4 D3 D2 D1 D0 A P
Slave Address Byte
Instruction Byte
Data Byte
Table 7. Read Mode
S 0 1 0 1 1 0 AD0 R A D7 D6 D5 D4 D3 D2 D1 D0 A P
Slave Address Byte
Data Byte
S = Start Condition
P = Stop Condition
A = Acknowledge
X = Don't Care
W = Write
R = Read
RS = Reset wiper to Midscale 80
H
SD = Shutdown connects wiper to B terminal and open
circuits A terminal. It does not change contents of wiper
register.
D7, D6, D5, D4, D3, D2, D1, D0 = Data Bits
t
1
t
3
t
4
t
2
t
7
t
8
t
9
P
S
P
S
t
10
t
5
t
9
t
8
SCL
SDA
t
2
t
6
Figure 38. I
2
C Interface Detailed Timing Diagram
SCL
FRAME 1
FRAME 2
START BY
MASTER
ACK BY
AD5161
SLAVE ADDRESS BYTE
STOP BY
MASTER
INSTRUCTION BYTE
SDA
0
1
0
1
1
0
AD0
R/W
X
RS
X
X
X
X
X
1
9
1
9
D7
D6
D5
D4
D3
D2
D1
D0
ACK BY
AD5161
FRAME 3
DATA BYTE
1
9
ACK BY
AD5161
SD
Figure 39
. Writing to the RDAC Register
NO ACK
BY MASTER
SCL
SDA
0
1
0
1
1
0
AD0
R/W
D7
D6
D5
D4
D3
D2
D1
D0
1
9
1
9
FRAME 1
FRAME 2
START BY
MASTER
ACK BY
AD5161
SLAVE ADDRESS BYTE
RDAC REGISTER
STOP BY
MASTER
Figure 40. Reading Data from a Previously Selected RDAC Register in Write Mode
AD5161
Rev. 0 | Page 14 of 20
OPERATION
The AD5161 is a 256-position digitally controlled variable
resistor (VR) device.
An internal power-on preset places the wiper at midscale
during power-on, which simplifies the fault condition recovery
at power-up.
PROGRAMMING THE VARIABLE RESISTOR
Rheostat Operation
The nominal resistance of the RDAC between terminals A and
B is available in 5 k, 10 k, 50 k, and 100 k. The final two
or three digits of the part number determine the nominal
resistance value, e.g., 10 k = 10; 50 k = 50. The nominal
resistance (R
AB
) of the VR has 256 contact points accessed by
the wiper terminal, plus the B terminal contact. The 8-bit data
in the RDAC latch is decoded to select one of the 256 possible
settings. Assume a 10 k part is used, the wiper's first
connection starts at the B terminal for data 0x00. Since there is a
60 wiper contact resistance, such connection yields a
minimum of 60 resistance between terminals W and B. The
second connection is the first tap point, which corresponds to
99 (R
WB
= R
AB
/256 + R
W
= 39 + 60 ) for data 0x01.
The third connection is the next tap point, representing 177
(2 39 + 60 ) for data 0x02, and so on. Each LSB data value
increase moves the wiper up the resistor ladder until the last tap
point is reached at 9961 (R
AB
1 LSB + R
W
). Figure 41 shows
a simplified diagram of the equivalent RDAC circuit where the
last resistor string will not be accessed; therefore, there is 1 LSB
less of the nominal resistance at full scale in addition to the
wiper resistance.
B
RDAC
LATCH
AND
DECODER
W
A
R
S
R
S
R
S
R
S
SD BIT
D7
D6
D4
D5
D2
D3
D1
D0
Figure 41. AD5161 Equivalent RDAC Circuit
The general equation determining the digitally programmed
output resistance between W and B is
W
AB
WB
R
R
D
D
R
+
=
256
)
(
(1)
where
D
is the decimal equivalent of the binary code loaded in
the 8-bit RDAC register,
R
AB
is the end-to-end resistance, and
R
W
is the wiper resistance contributed by the on resistance of
the internal switch.
In summary, if R
AB
= 10 k and the A terminal is open
circuited, the following output resistance R
WB
will be set for the
indicated RDAC latch codes.
Table 8. Codes and Corresponding R
WB
Resistance
D (Dec.)
R
WB
()
Output State
255
9,961
Full Scale (R
AB
1 LSB + R
W
)
128 5,060
Midscale
1 99
1
LSB
0
60
Zero Scale (Wiper Contact Resistance)
Note that in the zero-scale condition a finite wiper resistance of
60 is present. Care should be taken to limit the current flow
between W and B in this state to a maximum pulse current of
no more than 20 mA. Otherwise, degradation or possible
destruction of the internal switch contact can occur.
Similar to the mechanical potentiometer, the resistance of the
RDAC between the wiper W and terminal A also produces a
digitally controlled complementary resistance R
WA
. When these
terminals are used, the B terminal can be opened. Setting the
resistance value for R
WA
starts at a maximum value of resistance
and decreases as the data loaded in the latch increases in value.
The general equation for this operation is
W
AB
WA
R
R
D
D
R
+
-
=
256
256
)
(
(2)
For R
AB
= 10 k and the B terminal open circuited, the
following output resistance R
WA
will be set for the indicated
RDAC latch codes.
Table 9. Codes and Corresponding R
WA
Resistance
D (Dec.)
R
WA
()
Output State
255 99 Full
Scale
128 5,060
Midscale
1 9,961
1
LSB
0 10,060
Zero
Scale
Typical device to device matching is process lot dependent and
may vary by up to 30%. Since the resistance element is
processed in thin film technology, the change in R
AB
with
temperature has a very low 45 ppm/C temperature coefficient.
AD5161
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
The digital potentiometer easily generates a voltage divider at
wiper-to-B and wiper-to-A proportional to the input voltage at
A-to-B. Unlike the polarity of V
DD
to GND, which must be
positive, voltage across A-B, W-A, and W-B can be at either
polarity.
If ignoring the effect of the wiper resistance for approximation,
connecting the A terminal to 5 V and the B terminal to ground
produces an output voltage at the wiper-to-B starting at 0 V up
to 1 LSB less than 5 V. Each LSB of voltage is equal to the
voltage applied across terminal AB divided by the 256 positions
of the potentiometer divider. The general equation defining the
output voltage at V
W
with respect to ground for any valid input
voltage applied to terminals A and B is
B
A
W
V
D
V
D
D
V
256
256
256
)
(
-
+
=
(3)
For a more accurate calculation, which includes the effect of
wiper resistance, V
W
, can be found as
B
WA
A
WB
W
V
D
R
V
D
R
D
V
256
)
(
256
)
(
)
(
+
=
(4)
Operation of the digital potentiometer in the divider mode
results in a more accurate operation over temperature. Unlike
the rheostat mode, the output voltage is dependent mainly on
the ratio of the internal resistors R
WA
and R
WB
and not the
absolute values. Therefore, the temperature drift reduces to
15 ppm/C.
PIN SELECTABLE DIGITAL INTERFACE
The AD5161 provides the flexibility of a selectable interface.
When the digital interface select (DIS) pin is tied low, the SPI
mode is engaged. When the DIS pin is tied high, the I
2
C mode is
engaged.
SPI Compatible 3-W re Serial Bus (DIS = 0)
i
The AD5161 contains a 3-wire SPI compatible digital interface
(SDI, CS, and CLK). The 8-bit serial word must be loaded MSB
first. The format of the word is shown in Table 5.
The positive-edge sensitive CLK input requires clean transitions
to avoid clocking incorrect data into the serial input register.
Standard logic families work well. If mechanical switches are
used for product evaluation, they should be debounced by a
flip-flop or other suitable means. When CS is low, the clock
loads data into the serial register on each positive clock edge
(see Figure 36).
The data setup and data hold times in the specification table
determine the valid timing requirements. The AD5161 uses an
8-bit serial input data register word that is transferred to the
internal RDAC register when the CS line returns to logic high.
Extra MSB bits are ignored.
Daisy-Chain Operation
The serial data output (SDO) pin contains an open-drain
N-channel FET. This output requires a pull-up resistor in order
to transfer data to the next package's SDI pin. This allows for
daisy-chaining several RDACs from a single processor serial
data line. The pull-up resistor termination voltage can be larger
than the V
DD
supply voltage. It is recommended to increase the
clock period when using a pull-up resistor to the SDI pin of the
following device because capacitive loading at the daisy-chain
node SDO-SDI between devices may induce time delay to
subsequent devices. Users should be aware of this potential
problem to achieve data transfer successfully (see Figure 42). If
two AD5161s are daisy-chained, a total of at least 16 bits of data
is required. The first eight bits, complying with the format
shown in Table 5, go to U2 and the second eight bits with the
same format go to U1. CS should be kept low until all 16 bits are
clocked into their respective serial registers. After this, CS is
pulled high to complete the operation and load the RDAC latch.
If the data word during the CS low period is greater than 16
bits, any additional MSBs will be discarded.
AD5161
AD5161
U2
C
U1
CS
SDI
CLK
CLK
SDO
CS
CLK
SDI
SDO
SC
MOSI
V
DD
R
P
2.2k
Figure 42. Daisy-Chain Configuration
I
2
C Compatible 2-W re Serial Bus (DIS = 1)
i
The AD5161 can also be controlled via an I
2
C compatible serial
bus with DIS tied high. The RDACs are connected to this bus as
slave devices.
The first byte of the AD5161 is a slave address byte (see Table 6
and Table 7). It has a 7-bit slave address and a R/W bit. The six
MSBs of the slave address are 010110, and the following bit is
determined by the state of the AD0 pin of the device. AD0
allows the user to place up to two of the I
2
C compatible devices
on one bus.
The 2-wire I
2
C serial bus protocol operates as follows:
1. The master initiates data transfer by establishing a START
condition, which is when a high-to-low transition on the
SDA line occurs while SCL is high (see Figure 39). The
following byte is the slave address byte, which consists of
Rev. 0 | Page 15 of 20
AD5161
Rev. 0 | Page 16 of 20
the 7-bit slave address followed by an R/W bit (this bit
determines whether data will be read from or written to
the slave device).
The slave whose address corresponds to the transmitted
address responds by pulling the SDA line low during the
ninth clock pulse (this is termed the acknowledge bit). At
this stage, all other devices on the bus remain idle while the
selected device waits for data to be written to or read from
its serial register. If the R/W bit is high, the master will read
from the slave device. On the other hand, if the R/W bit is
low, the master will write to the slave device.
2. A write operation contains an extra instruction byte that a
read operation does not contain. Such an instruction byte
in write mode follows the slave address byte. The first bit
(MSB) of the instruction byte is a don't care.
The second MSB, RS, is the midscale reset. A logic high on
this bit moves the wiper to the center tap where R
WA
= R
WB
.
This feature effectively writes over the contents of the
register, and thus, when taken out of reset mode, the RDAC
will remain at midscale.
The third MSB, SD, is a shutdown bit. A logic high causes
an open circuit at terminal A while shorting the wiper to
terminal B. This operation yields almost 0 in rheostat
mode or 0 V in potentiometer mode. It is important to note
that the shutdown operation does not disturb the contents
of the register. When brought out of shutdown, the
previous setting will be applied to the RDAC. Also, during
shutdown, new settings can be programmed. When the
part is returned from shutdown, the corresponding VR
setting will be applied to the RDAC.
The remainder of the bits in the instruction byte are don't
cares (see Table 6).
3. After acknowledging the instruction byte, the last byte in
write mode is the data byte. Data is transmitted over the
serial bus in sequences of nine clock pulses (eight data bits
followed by an acknowledge bit). The transitions on the
SDA line must occur during the low period of SCL and
remain stable during the high period of SCL (see Table 6).
4. In the read mode, the data byte follows immediately after
the acknowledgment of the slave address byte. Data is
transmitted over the serial bus in sequences of nine clock
pulses (a slight difference with the write mode, where there
are eight data bits followed by an acknowledge bit).
Similarly, the transitions on the SDA line must occur
during the low period of SCL and remain stable during the
high period of SCL (see Figure 40).
5. When all data bits have been read or written, a STOP
condition is established by the master. A STOP condition is
defined as a low-to-high transition on the SDA line while
SCL is high. In write mode, the master will pull the SDA
line high during the tenth clock pulse to establish a STOP
condition (see Figure 39). In read mode, the master will
issue a No Acknowledge for the ninth clock pulse (i.e., the
SDA line remains high). The master will then bring the
SDA line low before the tenth clock pulse which goes high
to establish a STOP condition (see Figure 40).
A repeated write function gives the user flexibility to update the
RDAC output a number of times after addressing and
instructing the part only once. During the write cycle, each data
byte will update the RDAC output. For example, after the RDAC
has acknowledged its slave address and instruction bytes, the
RDAC output will update after these two bytes. If another byte
is written to the RDAC while it is still addressed to a specific
slave device with the same instruction, this byte will update the
output of the selected slave device. If different instructions are
needed, the write mode has to start again with a new slave
address, instruction, and data byte. Similarly, a repeated read
function of the RDAC is also allowed.
Readback RDAC Value
The AD5161 allows the user to read back the RDAC values in
the read mode. Refer to Table 6 and Table 7 for the
programming format.
Multiple Devices on One Bus
Figure 43 shows two AD5161 devices on the same serial bus.
Each has a different slave address since the states of their AD0
pins are different. This allows each RDAC within each device to
be written to or read from independently. The master device
output bus line drivers are open-drain pull-downs in a fully I
2
C
compatible interface.
MASTER
AD5161
SDA SCL
R
P
R
P
+5V
+5V
SDA
SCL
SDA SCL
AD5161
AD0
AD0
Figure 43. Multiple AD5161 Devices on One I
2
C Bus
AD5161
Rev. 0 | Page 17 of 20
LEVEL SHIFTING FOR BIDIRECTIONAL INTERFACE
While most legacy systems may be operated at one voltage, a
new component may be optimized at another. When two
systems operate the same signal at two different voltages, proper
level shifting is needed. For instance, one can use a 3.3 V
E
2
PROM to interface with a 5 V digital potentiometer. A level
shifting scheme is needed to enable a bidirectional
communication so that the setting of the digital potentiometer
can be stored to and retrieved from the E
2
PROM. Figure 44
shows one of the implementations. M1 and M2 can be any
N-channel signal FETs, or if V
DD
falls below 2.5 V, low threshold
FETs such as the FDV301N.
E
2
PROM
AD5161
SDA1
SCL1
D
G
R
P
R
P
3.3V
5V
S
M1
SCL2
SDA2
R
P
R
P
G
S
M2
V
DD1
= 3.3V
V
DD2 =
5V
D
Figure 44. Level Shifting for Operation at Different Potentials
ESD PROTECTION
All digital inputs are protected with a series input resistor and
parallel Zener ESD structures shown in Figure 45 and Figure 46.
This applies to the digital input pins SDI/SDA, CLK/SCL, and
CS/AD0.
LOGIC
340
Vss
Figure 45. ESD Protection of Digital Pins
A,B,W
V
SS
Figure 46. ESD Protection of Resistor Terminals
TERMINAL VOLTAGE OPERATING RANGE
The AD5161 V
DD
and GND power supply defines the boundary
conditions for proper 3-terminal digital potentiometer
operation. Supply signals present on terminals A, B, and W that
exceed V
DD
or GND will be clamped by the internal forward
biased diodes (see Figure 47).
A
V
DD
B
W
V
SS
Figure 47. Maximum Terminal Voltages Set by V
DD
and V
SS
POWER-UP SEQUENCE
Since the ESD protection diodes limit the voltage compliance at
terminals A, B, and W (see Figure 47), it is important to power
V
DD
/GND before applying any voltage to terminals A, B, and W;
otherwise, the diode will be forward biased such that V
DD
will be
powered unintentionally and may affect the rest of the user's
circuit. The ideal power-up sequence is in the following order:
GND, V
DD
, digital inputs, and then V
A/B/W
. The relative order of
powering V
A
, V
B
, V
W
, and the digital inputs is not important as
long as they are powered after V
DD
/GND.
LAYOUT AND POWER SUPPLY BYPASSING
It is a good practice to employ compact, minimum lead length
layout design. The leads to the inputs should be as direct as
possible with a minimum conductor length. Ground paths
should have low resistance and low inductance.
Similarly, it is also a good practice to bypass the power supplies
with quality capacitors for optimum stability. Supply leads to the
device should be bypassed with disc or chip ceramic capacitors
of 0.01 F to 0.1 F. Low ESR 1 F to 10 F tantalum or
electrolytic capacitors should also be applied at the supplies to
minimize any transient disturbance and low frequency ripple
(see Figure 48). Note that the digital ground should also be
joined remotely to the analog ground at one point to minimize
the ground bounce.
AD5161
V
DD
C1
C3
GND
10
F
0.1
F
+
V
DD
Figure 48. Power Supply Bypassing
AD5161
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN CONFIGURATION
1
2
3
4
5
10
9
8
7
6
A
B
CS/ADO
SDO/NC
SDI/SDA
DD
AD5161
TOP VIEW
(Not to Scale)
W
V
DIS
GND
CLK/SCL
Figure 49.
PIN FUNCTION DESCRIPTIONS
Table 10.
Pin Name Description
1 A
A
Terminal.
2 B
B
Terminal.
3
CS/AD0
CS: Chip Select Input, Active Low. When CS
returns high, data will be loaded into the DAC
register.
AD0: Programmable address bit 0 for multiple
package decoding.
4 SDO/NC
SDO: Serial Data Output. Open-drain transistor
requires pull-up resistor.
NC: No Connect.
5
SDI/SDA
SDI: Serial Data Input.
SDA: Serial Data Input/Output.
6
CLK/SCL
Serial Clock Input. Positive edge triggered.
7 GND Digital
Ground.
8 DIS
Digital Interface Select (SPI/I
2
C Select).
SPI when DIS = 0, I
2
C when DIS = 1.
9 V
DD
Positive Power Supply.
10 W
W Terminal.
Rev. 0 | Page 18 of 20
AD5161
OUTLINE DIMENSIONS
0.23
0.20
0.17
0.80
0.40
8
0
0.15
0.00
0.27
0.17
0.95
0.85
0.75
SEATING
PLANE
1.10 MAX
10
6
5
1
0.50 BSC
3.00 BSC
3.00 BSC
4.90 BSC
PIN 1
COMPLIANT TO JEDEC STANDARDS MO-187BA
COPLANARITY
0.10
Figure 50. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
ORDERING GUIDE
Model R
AB
()
Temperature
Package Description
Package Option
Branding
AD5161BRM5
5k
40C to +125C
MSOP-10
RM-10
D0C
AD5161BRM5-RL7
5k
40C to +125C
MSOP-10
RM-10
D0C
AD5161BRM10
10k
40C to +125C
MSOP-10
RM-10
D0D
AD5161BRM10-RL7
10k
40C to +125C
MSOP-10
RM-10
D0D
AD5161BRM50
50k
40C to +125C
MSOP-10
RM-10
D0E
AD5161BRM50-RL7
50k
40C to +125C
MSOP-10
RM-10
D0E
AD5161BRM100
100k
40C to +125C
MSOP-10
RM-10
D0F
AD5161BRM100-RL7
100k
40C to +125C
MSOP-10
RM-10
D0F
AD5161EVAL
See Note 1
Evaluation Board
1
The evaluation board is shipped with the 10 k R
AB
resistor option; however, the board is compatible with all available resistor value options.
The AD5161 contains 2532 transistors. Die size: 30.7 mil 76.8 mil = 2358 sq. mil.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 19 of 20
AD5161
Rev. 0 | Page 20 of 20
NOTES
2003 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective companies.
C0343505/03(0)
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