Document Outline
- FEATURES
- APPLICATIONS
- GENERAL OVERVIEW
- FUNCTIONAL BLOCK DIAGRAM
-
-
-
-
-
-
-
-
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-
-
256-Position Two-Time Programmable
I
2
C Digital Potentiometer
AD5170
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
2004 Analog Devices, Inc. All rights reserved.
FEATURES
256-position
TTP (two-time programmable) set-and-forget resistance
setting allows second-chance permanent programming
Unlimited adjustments prior to OTP (one-time
programming) activation
OTP overwrite allows dynamic adjustments with user
defined preset
End-to-end resistance: 2.5 k, 10 k, 50 k, 100 k
Compact MSOP-10 (3 mm 4.9 mm) package
Fast settling time: t
S
= 5 s typ in power-up
Full read/write of wiper register
Power-on preset to midscale
Extra package address decode pins AD0 and AD1
Single-supply 2.7 V to 5.5 V
Low temperature coefficient: 35 ppm/C
Low power, I
DD
= 6 A maximum
Wide operating temperature: 40C to +125C
Evaluation board and software are available
Software replaces C in factory programming applications
APPLICATIONS
Systems calibration
Electronics level setting
Mechanical Trimmers replacement in new designs
Permanent factory PCB setting
Transducer adjustment of pressure, temperature, position,
chemical, and optical sensors
RF amplifier biasing
Automotive electronics adjustment
Gain control and offset adjustment
GENERAL OVERVIEW
The AD5170 is a 256-position, two-time programmable (TTP)
digital potentiometer
1
that employs fuse link technology to
enable two opportunities at permanently programming the
resistance setting. OTP is a cost-effective alternative to EEMEM
for users who do not need to program the digital potentiometer
setting in memory more than once. This device performs the
same electronic adjustment function as mechanical
potentiometers or variable resistors with enhanced resolution,
solid-state reliability, and superior low temperature coefficient
performance.
FUNCTIONAL BLOCK DIAGRAM
V
DD
GND
SDA
SCL
AD0
AD1
W
RDAC
REGISTER
ADDRESS
DECODE
SERIAL INPUT
REGISTER
B
A
FUSE
LINKS
1
2
/
8
04104-0-001
Figure 1.
The AD5170 is programmed using a 2-wire, I
2
C compatible
digital interface. Unlimited adjustments are allowed before
permanently (there are actually two opportunities) setting the
resistance value. During OTP activation, a permanent blow fuse
command freezes the wiper position (analogous to placing
epoxy on a mechanical trimmer).
Unlike traditional OTP digital potentiometers, the AD5170 has
a unique temporary OTP overwrite feature that allows for new
adjustments even after the fuse has been blown. However, the
OTP setting is restored during subsequent power-up
conditions. This feature allows users to treat these digital
potentiometers as volatile potentiometers with a programmable
preset.
For applications that program the AD5170 at the factory,
Analog Devices offers device programming software running
on Windows NT, 2000, and XP operating systems. This
software effectively replaces any external I
2
C controllers, thus
enhancing the time-to-market of the user's systems.
1
The terms digital potentiometer, VR, and RDAC are used interchangeably.
AD5170
Rev. A | Page 2 of 24
TABLE OF CONTENTS
Electrical Characteristics -- 2.5 k ............................................... 3
Electrical Characteristics -- 10 k, 50 k, 100 k Versions..... 4
Timing Characteristics -- 2.5 k, 10 k, 50 k, 100 k
Versions.............................................................................................. 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Typical Performance Characteristics ............................................. 7
Test Circuits..................................................................................... 11
Theory of Operation ...................................................................... 12
One-Time Programming (OTP) .............................................. 12
Programming the Variable Resistor and Voltage ................... 12
Programming the Potentiometer Divider ............................... 13
ESD Protection ........................................................................... 14
Terminal Voltage Operating Range ......................................... 14
Power-Up Sequence ................................................................... 14
Power Supply Considerations................................................... 14
Layout Considerations............................................................... 15
Evaluation Software/Hardware..................................................... 16
Software Programming ............................................................. 16
I
2
C Interface .................................................................................... 18
I
2
C Compatible 2-Wire Serial Bus ........................................... 20
Pin Configuration and Function Descriptions........................... 22
Outline Dimensions ....................................................................... 23
Ordering Guide .......................................................................... 23
REVISION HISTORY
11/04--Data Sheet Changed from Rev. 0 to Rev. A
Changes to Electrical Characteristics Table 1 ............................... 3
Changes to Electrical Characteristics Table 2 ............................... 4
Changes to One-Time Programming ......................................... 12
Changes to Figure 37, Figure 38, and Figure 39 ........................ 14
Changes to Power Supply Considerations................................... 14
Changes to Figure 40...................................................................... 15
Changes to Layout Considerations .............................................. 15
11/03--Revision 0: Initial Version
AD5170
Rev. A | Page 3 of 24
ELECTRICAL CHARACTERISTICS -- 2.5 k
V
DD
= 5 V 10% or 3 V 10%, V
A
= +V
DD
, V
B
= 0 V, 40C < T
A
< +125C, unless otherwise noted.
Table 1.
Parameter Symbol
Conditions
Min
Typ
1
Max Unit
DC CHARACTERISTICS--RHEOSTAT MODE
Resistor Differential Nonlinearity
2
R-DNL R
WB
, V
A
= no connect
2
0.1
+2
LSB
Resistor Integral Nonlinearity
2
R-INL
R
WB
, V
A
= no connect
6
0.75
+6
LSB
Nominal Resistor Tolerance
3
R
AB
T
A
= 25C
20
+55
%
Resistance Temperature Coefficient
(R
AB
/R
AB
)/T V
AB
= V
DD
, Wiper = no connect
35
ppm/C
R
WB
(Wiper Resistance)
R
WB
Code = 0x00, V
DD
= 5 V
160
200
DC CHARACTERISTICS -- POTENTIOMETER DIVIDER MODE (Specifications apply to all VRs)
Differential Nonlinearity
4
DNL
1.5
0.1
+1.5
LSB
Integral Nonlinearity
4
INL
2
0.6
+2
LSB
Voltage Divider Temperature Coefficient
(V
W
/V
W
)/T
Code = 0x80
15
ppm/C
Full-Scale Error
V
WFSE
Code = 0xFF
10
2.5
0
LSB
Zero-Scale Error
V
WZSE
Code = 0x00
0
2
10
LSB
RESISTOR TERMINALS
Voltage Range
5
V
A
,V
B
,V
W
GND
V
DD
V
Capacitance
6
A, B
C
A
, C
B
f = 1 MHz, measured to GND, code = 0x80
45
pF
Capacitance W
C
W
f = 1 MHz, measured to GND, code = 0x80
60
pF
Shutdown Supply Current
7
I
A_SD
V
DD
= 5.5 V
0.01
1
A
Common-Mode Leakage
I
CM
V
A
= V
B
= V
DD
/2
1
nA
DIGITAL INPUTS AND OUTPUTS
Input Logic High
V
IH
V
DD
= 5 V
2.4
V
Input Logic Low
V
IL
V
DD
= 5 V
0.8
V
Input Logic High
V
IH
V
DD
= 3 V
2.1
V
Input Logic Low
V
IL
V
DD
= 3 V
0.6
V
Input Current
I
IL
V
IN
= 0 V or 5 V
1
A
Input Capacitance
5
C
IL
5
pF
POWER SUPPLIES
Power Supply Range
V
DD RANGE
2.7
5.5
V
OTP Supply Voltage
V
DD_OTP
T
A
= 25C
5.25
5.5
V
Supply Current
I
DD
V
IH
= 5 V or V
IL
= 0 V
3.5
6
A
OTP Supply Current
I
DD_OTP
V
DD_OTP
= 5.5 V, T
A
= 25C
100
mA
Power Dissipation
8
P
DISS
V
IH
= 5 V or V
IL
= 0 V, V
DD
= 5 V
30
W
Power Supply Sensitivity
PSS
V
DD
= 5 V 10%, Code = midscale
0.02
0.08
%/%
DYNAMIC CHARACTERISTICS
9
Bandwidth 3 dB
BW_2.5K
Code = 0x80
4.8
MHz
Total Harmonic Distortion
THD
W
V
A
= 1 V rms, V
B
= 0 V, f = 1 kHz
0.1
%
V
W
Settling Time
t
S
V
A
= 5 V, V
B
= 0 V, 1 LSB error band
1
s
Resistor Noise Voltage Density
e
N_WB
R
WB
= 1.25 k, R
S
= 0
3.2
nV/Hz
1
Typical specifications represent average readings at 25C and V
DD
= 5 V.
2
Resistor position nonlinearity error, R-INL, is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
3
V
AB
= V
DD
, Wiper (V
W
) = no connect.
4
INL and DNL are measured at V
W
with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V
A
= V
DD
and V
B
= 0 V.
DNL specification limits of 1 LSB maximum are guaranteed monotonic operating conditions.
5
Resistor terminals A, B, W have no limitations on polarity with respect to each other.
6
Guaranteed by design and not subject to production test.
7
Measured at the A terminal. The A terminal is open circuited in shutdown mode.
8
P
DISS
is calculated from (I
DD
V
DD
). CMOS logic level inputs result in minimum power dissipation.
9
All dynamic characteristics use V
DD
= 5 V.
AD5170
Rev. A | Page 4 of 24
ELECTRICAL CHARACTERISTICS -- 10 k, 50 k, 100 k VERSIONS
V
DD
= 5 V 10% or 3 V 10%, V
A
= V
DD
; V
B
= 0 V, 40C < T
A
< +125C, unless otherwise noted.
Table 2.
Parameter Symbol
Conditions
Min
Typ
1
Max Unit
DC CHARACTERISTICS--RHEOSTAT MODE
Resistor Differential Nonlinearity
2
R-DNL
R
WB
, V
A
= no connect
1
0.1
+1
LSB
Resistor Integral Nonlinearity
2
R-INL R
WB
, V
A
= no connect
2.5
0.25
+2.5
LSB
Nominal Resistor Tolerance
3
R
AB
T
A
= 25C
20
+20
%
Resistance Temperature Coefficient
(R
AB
/R
AB
)/T V
AB
= V
DD
, wiper = no connect
35
ppm/C
R
WB
(Wiper Resistance)
R
WB
Code = 0x00, V
DD
= 5 V
160
200
DC CHARACTERISTICS -- POTENTIOMETER DIVIDER MODE (Specifications apply to all VRs)
Differential Nonlinearity
4
DNL
1
0.1
+1
LSB
Integral Nonlinearity
4
INL
1
0.3
+1
LSB
Voltage Divider Temperature
Coefficient
(V
W
/V
W
)/T
Code = 0x80
15
ppm/C
Full-Scale Error
V
WFSE
Code = 0xFF
2.5
1
0
LSB
Zero-Scale Error
V
WZSE
Code = 0x00
0
1
2.5
LSB
RESISTOR TERMINALS
Voltage Range
5
V
A
,V
B
,V
W
GND
V
DD
V
Capacitance
6
A, B
C
A,
C
B
f = 1 MHz, measured to GND, code = 0x80
45
pF
Capacitance
6
W
C
W
f = 1 MHz, measured to GND, code = 0x80
60
pF
Shutdown Supply Current
7
I
A_SD
V
DD
= 5.5 V
0.01
1
A
Common-Mode Leakage
I
CM
V
A
= V
B
= V
DD
/2
1
nA
DIGITAL INPUTS AND OUTPUTS
Input Logic High
V
IH
V
DD
= 5 V
2.4
V
Input Logic Low
V
IL
V
DD
= 5 V
0.8
V
Input Logic High
V
IH
V
DD
= 3 V
2.1
V
Input Logic Low
V
IL
V
DD
= 3 V
0.6
V
Input Current
I
IL
V
IN
= 0 V or 5 V
1
A
Input Capacitance
6
C
IL
5
pF
POWER SUPPLIES
Power Supply Range
V
DD RANGE
2.7
5.5
V
OTP Supply Voltage
8
V
DD_OTP
5.25
5.5
V
Supply Current
I
DD
V
IH
= 5 V or V
IL
= 0 V
3.5
6
A
OTP Supply Current
9
I
DD_OTP
V
DD_OTP
= 5.5 V, T
A
= 25C
100
mA
Power Dissipation
10
P
DISS
V
IH
= 5 V or V
IL
= 0 V, V
DD
= 5 V
30
W
Power Supply Sensitivity
PSS
V
DD
= 5 V 10%, code = midscale
0.02
0.08
%/%
DYNAMIC CHARACTERISTICS
11
Bandwidth 3 dB
BW
R
AB
= 10 k, code = 0x80
600
kHz
R
AB
= 50 k, code = 0x80
100
kHz
R
AB
= 100 k, code = 0x80
40
kHz
Total Harmonic Distortion
THD
W
V
A
=1 V rms, V
B
= 0 V, f = 1 kHz, R
AB
= 10 k
0.1
%
V
W
Settling Time
(10 k/50 k/100 k)
t
S
V
A
= 5 V, V
B
= 0 V, 1 LSB error band
2
s
Resistor Noise Voltage Density
e
N_WB
R
WB
= 5 k, R
S
= 0
9
nV/Hz
1
Typical specifications represent average readings at 25C and V
DD
= 5 V.
2
Resistor position nonlinearity error, R-INL, is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
3
V
AB
= V
DD
, Wiper (V
W
) = no connect.
4
INL and DNL are measured at V
W
with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V
A
= V
DD
and V
B
= 0 V.
DNL specification limits of 1 LSB maximum are guaranteed monotonic operating conditions.
5
Resistor terminals A, B, W have no limitations on polarity with respect to each other.
6
Guaranteed by design and not subject to production test.
7
Measured at the A terminal. The A terminal is open circuited in shutdown mode.
8
Different from operating power supply, power supply OTP is used one time only.
9
Different from operating current, supply current for OTP lasts approximately 400 ms for one time only.
10
P
DISS
is calculated from (I
DD
V
DD
). CMOS logic level inputs result in minimum power dissipation.
11
All dynamic characteristics use V
DD
= 5 V.
AD5170
Rev. A | Page 5 of 24
TIMING CHARACTERISTICS -- 2.5 k, 10 k, 50 k, 100 k VERSIONS
V
DD
= 5 V 10% or 3 V 10%, V
A
= V
DD
; V
B
= 0 V, 40C < T
A
< +125C, unless otherwise noted.
Table 3.
Parameter
Symbol Conditions
Min Typ Max Unit
I
2
C INTERFACE TIMING CHARACTERISTICS
1
(Specifications apply to all parts)
SCL Clock Frequency
f
SCL
400
kHz
t
BUF
Bus Free Time between STOP and START
t
1
1.3
s
t
HD;STA
Hold Time (Repeated START)
t
2
After this period, the first clock
pulse is generated.
0.6
s
t
LOW
Low Period of SCL Clock
t
3
1.3
s
t
HIGH
High Period of SCL Clock
t
4
0.6
s
t
SU;STA
Setup Time for Repeated START Condition
t
5
0.6
s
t
HD;DAT
Data Hold Time
2
t
6
0.9
s
t
SU;DAT
Data Setup Time
t
7
100
ns
t
F
Fall Time of Both SDA and SCL Signals
t
8
300
ns
t
R
Rise Time of Both SDA and SCL Signals
t
9
300
ns
t
SU;STO
Setup Time for STOP Condition
t
10
0.6
s
1
See timing diagrams for locations of measured values.
2
The maximum t
HD;DAT
has only to be met if the device does not stretch the LOW period (t
LOW
) of the SCL signal.
AD5170
Rev. A | Page 6 of 24
ABSOLUTE MAXIMUM RATINGS
T
A
= 25C, unless otherwise noted.
Table 4.
Parameter Value
V
DD
to GND
0.3 V to +7 V
V
A
, V
B
, V
W
to GND
V
DD
Terminal Current, AxBx, AxWx, BxWx
1
Pulsed 20
mA
Continuous 5
mA
Digital Inputs and Output Voltage to GND
0 V to 7 V
Operating Temperature Range
40C to +125C
Maximum Junction Temperature (T
JMAX
) 150C
Storage Temperature
65C to +150C
Lead Temperature (Soldering, 10 sec)
300C
Thermal Resistance
2
JA
: MSOP-10
230C/W
1
Maximum terminal current is bound by the maximum current handling of
the switches, maximum power dissipation of the package, and maximum
applied voltage across any two of the A, B, and W terminals at a given
resistance.
2
Package power dissipation = (T
JMAX
T
A
)/
JA
.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
AD5170
Rev. A | Page 7 of 24
TYPICAL PERFORMANCE CHARACTERISTICS
2.0
1.5
1.0
0.5
0
0.5
RHEOSTAT MODE INL (LSB)
1.0
1.5
2.0
128
96
32
64
0
160
192
224
256
CODE (DECIMAL)
04104-0-002
V
DD
= 5.5V
T
A
= 25C
R
AB
= 10k
V
DD
= 2.7V
Figure 2. R-INL vs. Code vs. Supply Voltages
0.5
0.4
0.3
0.2
0.1
0
0.1
0.2
0.3
0.4
0.5
RHE
OS
TAT MODE
DNL (LS
B
)
128
96
32
64
0
160
192
224
256
CODE (DECIMAL)
04104-0-003
T
A
= 25C
R
AB
= 10k
V
DD
= 2.7V
V
DD
= 5.5V
Figure 3. R-DNL vs. Code vs. Supply Voltages
0.5
0.4
0.3
0.2
0.1
0
0.1
0.2
0.3
0.4
0.5
P
O
TE
NTIOME
TE
R MODE
INL (LS
B
)
128
96
32
64
0
160
192
224
256
CODE (DECIMAL)
04104-0-004
R
AB
= 10k
V
DD
= 2.7V
T
A
= 40C, +25C, +85C, +125C
V
DD
= 5.5V
T
A
= 40C, +25C, +85C, +125C
Figure 4. INL vs. Code vs. Temperature
0.5
0.4
0.3
0.2
0.1
0
0.1
0.2
0.3
0.4
0.5
P
O
TE
NTIOME
TE
R MODE
DNL (LS
B
)
128
96
32
64
0
160
192
224
256
CODE (DECIMAL)
04104-0-005
V
DD
= 2.7V; T
A
= 40C, +25C, +85C, +125C
R
AB
= 10k
Figure 5. DNL vs. Code vs. Temperature
1.0
0.8
0.6
0.4
0.2
0
0.2
0.4
0.6
0.8
1.0
P
O
TE
NTIOME
TE
R MODE
INL (LS
B
)
128
96
32
64
0
160
192
224
256
CODE (DECIMAL)
04104-0-006
T
A
= 25C
R
AB
= 10k
V
DD
= 2.7V
V
DD
= 5.5V
Figure 6. INL vs. Code vs. Supply Voltages
0.5
0.4
0.3
0.2
0.1
0
0.1
0.2
0.3
0.4
0.5
P
O
TE
NTIOME
TE
R MODE
DNL (LS
B
)
128
96
32
64
0
160
192
224
256
CODE (DECIMAL)
04104-0-007
T
A
= 25C
R
AB
= 10k
V
DD
= 2.7V
V
DD
= 5.5V
Figure 7. DNL vs. Code vs. Supply Voltages
AD5170
Rev. A | Page 8 of 24
2.0
1.5
1.0
0.5
0
0.5
RHEOSTAT MODE INL (LSB)
1.0
1.5
2.0
128
96
32
64
0
160
192
224
256
CODE (DECIMAL)
04104-0-008
R
AB
= 10k
V
DD
= 2.7V
T
A
= 40C, +25C, +85C, +125C
V
DD
= 5.5V
T
A
= 40C, +25C, +85C, +125C
Figure 8. R-INL vs. Code vs. Temperature
0.5
0.4
0.3
0.2
0.1
0
0.1
0.2
0.3
0.4
0.5
RHE
OS
TAT MODE
DNL (LS
B
)
128
96
32
64
0
160
192
224
256
CODE (DECIMAL)
04104-0-009
V
DD
= 2.7V, 5.5V; T
A
= 40C, +25C, +85C, +125C
R
AB
= 10k
Figure 9. R-DNL vs. Code vs. Temperature
2.0
1.5
1.0
0.5
0
0.5
FSE, FU
LL-
SC
A
L
E ER
R
O
R
(
L
SB
)
1.0
1.5
2.0
TEMPERATURE (C)
40 25 10
5
20
35
50
65
80
95
110 125
04104-0-010
V
DD
= 5.5V, V
A
= 5.0V
R
AB
= 10k
V
DD
= 2.7V, V
A
= 2.7V
Figure 10. Full-Scale Error vs. Temperature
0
0.75
1.50
2.25
3.00
3.75
4.50
ZS
E
,
ZE
RO-S
CALE
E
RROR (LS
B
)
TEMPERATURE (C)
40 25 10
5
20
35
50
65
80
95
110 125
04104-0-011
V
DD
= 5.5V, V
A
= 5.0V
R
AB
= 10k
V
DD
= 2.7V, V
A
= 2.7V
Figure 11. Zero-Scale Error vs. Temperature
I
DD
, S
U
P
P
L
Y
CURRE
NT (
A)
0.1
1
10
40
7
26
59
92
125
TEMPERATURE (C)
04104-0-012
V
DD
= 5V
V
DD
= 3V
Figure 12. Supply Current vs. Temperature
20
0
20
40
60
80
100
120
RHEOSTAT MODE TE
MP
CO (ppm/
C)
128
96
32
64
0
160
192
224
256
CODE (DECIMAL)
04104-0-013
R
AB
= 10k
V
DD
= 2.7V
T
A
= 40C TO +85C, 40C TO +125C
V
DD
= 5.5V
T
A
= 40C TO +85C, 40C TO +125C
Figure 13. Rheostat Mode Tempco R
WB
/T vs. Code
AD5170
Rev. A | Page 9 of 24
30
20
10
0
10
20
P
O
TE
NTIOME
TE
R MODE
TE
MP
CO (ppm/
C)
30
40
50
128
96
32
64
0
160
192
224
256
CODE (DECIMAL)
04104-0-014
R
AB
= 10k
V
DD
= 2.7V
T
A
= 40C TO +85C, 40C TO +125C
V
DD
= 5.5V
T
A
= 40C TO +85C, 40C TO +125C
Figure 14. Potentiometer Mode Tempco V
WB
/T vs. Code
60
54
48
42
36
30
24
18
12
6
0
GAIN (
d
B)
FREQUENCY (Hz)
10k
1M
100k
10M
04104-0-015
0x80
0x40
0x20
0x10
0x08
0x04
0x01
0x02
Figure 15. Gain vs. Frequency vs. Code, R
AB
= 2.5 k
60
54
48
42
36
30
24
18
12
6
0
GAIN (
d
B)
FREQUENCY (Hz)
1k
100k
10k
1M
04104-0-016
0x80
0x40
0x20
0x10
0x08
0x04
0x01
0x02
Figure 16. Gain vs. Frequency vs. Code, R
AB
= 10 k
60
54
48
42
36
30
24
18
12
6
0
GAIN (
d
B)
FREQUENCY (Hz)
1k
100k
10k
1M
04104-0-017
0x80
0x40
0x20
0x10
0x08
0x04
0x01
0x02
Figure 17. Gain vs. Frequency vs. Code, R
AB
= 50 k
60
54
48
42
36
30
24
18
12
6
0
GAIN (
d
B)
FREQUENCY (Hz)
1k
100k
10k
1M
04104-0-018
0x80
0x40
0x20
0x10
0x08
0x04
0x01
0x02
Figure 18. Gain vs. Frequency vs. Code, R
AB
= 100 k
60
54
48
42
36
30
24
18
12
6
0
GAIN (
d
B)
FREQUENCY (Hz)
10k
1k
100k
1M
10M
04104-0-019
100k
60kHz
50k
120kHz
10k
570kHz
2.5k
2.2MHz
Figure 19. 3 dB Bandwidth at Code = 0x80
AD5170
Rev. A | Page 10 of 24
I
DD
, S
U
P
P
LY
CURRE
NT (mA)
0.01
1
0.1
10
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
DIGITAL INPUT VOLTAGE (V)
04104-0-020
T
A
= 25C
V
DD
= 2.7V
V
DD
= 5.5V
Figure 20. I
DD
vs. Input Voltage
04104-0-021
SCL
V
W
Figure 21. Digital Feedthrough
04104-0-025
V
W
Figure 22. Midscale Glitch, Code 0x80 to 0x7F
04104-0-023
SCL
V
W
Figure 23. Large Signal Settling Time
AD5170
Rev. A | Page 11 of 24
TEST CIRCUITS
Figure 24 to Figure 29 illustrate the test circuits that define the
test conditions used in the product specification tables.
04104-0-026
V
MS
A
W
B
DUT
V+
V+ = V
DD
1LSB = V+/2
N
Figure 24. Test Circuit for Potentiometer Divider Nonlinearity Error (INL, DNL)
04104-0-027
NO CONNECT
I
W
V
MS
A W
B
DUT
Figure 25. Test Circuit for Resistor Position Nonlinearity Error
(Rheostat Operation; R-INL, R-DNL)
04104-0-028
V
MS2
V
MS1
V
W
A
W
B
DUT
I
W
= V
DD
/R
NOMINAL
R
W
= [V
MS1
V
MS2
]/I
W
Figure 26. Test Circuit for Wiper Resistance
04104-0-029
V
MS
%
DUT
( )
A
W
B
V+
V
DD
%
V
MS
V
DD
V
DD
V
A
V
MS
V+ = V
DD
10%
PSRR (dB) = 20 LOG
PSS (%/%) =
Figure 27. Test Circuit for Power Supply Sensitivity (PSS, PSSR)
04104-0-030
+15V
15V
W
A
2.5V
B
V
OUT
OFFSET
GND
DUT
AD8610
V
IN
Figure 28. Test Circuit for Gain vs. Frequency
W
B
V
CM
I
CM
A
NC
GND
NC
V
DD
DUT
NC = NO CONNECT
04104-0-032
Figure 29. Test Circuit for Common-Mode Leakage Current
AD5170
Rev. A | Page 12 of 24
THEORY OF OPERATION
SDA
SCL
A
W
B
FUSES
EN
DAC
REG.
I
2
C INTERFACE
COMPARATOR
ONE-TIME
PROGRAM/TEST
CONTROL BLOCK
MUX
DECODER
FUSE
REG.
04103-0-026
Figure 30. Detailed Functional Block Diagram
The AD5170 is a 256-position, digitally controlled variable
resistor (VR) that employs fuse link technology to achieve
memory retention of resistance setting.
An internal power-on preset places the wiper at midscale
during power-on. If the OTP function has been activated, the
device powers up at the user-defined permanent setting.
ONE-TIME PROGRAMMING (OTP)
Prior to OTP activation, the AD5170 presets to midscale during
initial power-on. After the wiper is set at the desired position,
the resistance can be permanently set by programming the T bit
high along with the proper coding (see Table 7 and Table 8) and
one time V
DD_OTP
. Note that fuse link technology of the
AD517x family of digital pots requires V
DD_OTP
between 5.25 V
and 5.5 V to blow the fuses to achieve a given nonvolatile
setting. On the other hand, V
DD
can be 2.7 V to 5.5 V during
operation. As a result, system supply that is lower than 5.25 V
requires external supply for one-time programming. Note that
the user is allowed only one attempt in blowing the fuses. If the
user fails to blow the fuses at the first attempt, the fuses'
structures may have changed such that they may never be
blown regardless of the energy applied at subsequent events. For
details, see the Power Supply Considerations section.
The device control circuit has two validation bits, E1 and E0,
that can be read back to check the programming status (see
Table 7). Users should always read back the validation bits to
ensure that the fuses are properly blown. After the fuses have
been blown, all fuse latches are enabled upon subsequent
power-on; therefore, the output corresponds to the stored
setting. Figure 30 shows a detailed functional block diagram.
PROGRAMMING THE VARIABLE RESISTOR AND
VOLTAGE
Rheostat Operation
The nominal resistance of the RDAC between Terminal A and
Terminal B is available in 2.5 k, 10 k, 50 k, and 100 k.
The nominal resistance (R
AB
) of the VR has 256 contact points
accessed by the wiper terminal, plus the B terminal contact. The
8-bit data in the RDAC latch is decoded to select one of 256
possible settings.
A
W
B
A
W
B
A
W
B
04103-0-027
Figure 31. Rheostat Mode Configuration
Assuming a 10 k part is used, the wiper's first connection
starts at the B terminal for data 0x00. Because there is a 50
wiper contact resistance, such a connection yields a minimum
of 100 (2 50 ) resistance between Terminal W and
Terminal B. The second connection is the first tap point, which
corresponds to 139 (R
WB
= R
AB
/256 + 2 R
W
= 39 + 2 50 )
for data 0x01. The third connection is the next tap point, repre-
senting 178 (2 39 + 2 50 ) for data 0x02, and so on.
Each LSB data value increase moves the wiper up the resistor
ladder until the last tap point is reached at 10,100 (R
AB
+ 2 R
W
).
AD5170
Rev. A | Page 13 of 24
D5
D4
D3
D7
D6
D2
D1
D0
RDAC
LATCH
AND
DECODER
R
S
R
S
R
S
R
S
A
W
B
SD BIT
04104-0-034
Figure 32. AD5170 Equivalent RDAC Circuit
The general equation that determines the digitally programmed
output resistance between Terminal W and Terminal B is
W
AB
WB
R
R
D
D
R
+
=
2
128
)
(
(1)
where D is the decimal equivalent of the binary code loaded in
the 8-bit RDAC register, R
AB
is the end-to-end resistance, and
R
W
is the wiper resistance contributed by the on resistance of
the internal switch.
In summary, if R
AB
= 10 k and the A terminal is open-
circuited, the output resistance R
WB
is set for the RDAC latch
codes, as shown in Table 5.
Table 5. Codes and Corresponding R
WB
Resistance
D (Dec.)
R
WB
()
Output State
255
9,961
Full Scale (R
AB
1 LSB + R
W
)
128 5,060
Midscale
1 139
1
LSB
0
100
Zero Scale (Wiper Contact Resistance)
Note that in the zero-scale condition, a finite wiper resistance of
100 is present. Care should be taken to limit the current flow
between Terminal W and Terminal B in this state to a maximum
pulse current of no more than 20 mA. Otherwise, degradation
or possible destruction of the internal switch contact can occur.
Similar to the mechanical potentiometer, the resistance of the
RDAC between the wiper, Terminal W, and Terminal A also
produces a digitally controlled complementary resistance, R
WA
.
When these terminals are used, the B terminal can be opened.
Setting the resistance value for R
WA
starts at a maximum value
of resistance and decreases as the data loaded in the latch
increases in value. The general equation for this operation is
W
AB
WA
R
R
D
D
R
+
=
2
128
256
)
(
(2)
For R
AB
= 10 k and the B terminal open-circuited, the
following output resistance, R
WA,
is set for the RDAC latch
codes, as shown in Table 6.
Table 6. Codes and Corresponding R
WA
Resistance
D (Dec.)
R
WA
()
Output State
255 139 Full
Scale
128 5,060
Midscale
1 9,961
1
LSB
0 10,060
Zero
Scale
Typical device-to-device matching is process lot dependent and
may vary by up to 30%. Since the resistance element is pro-
cessed using thin film technology, the change in R
AB
with
temperature has a very low 35 ppm/C temperature coefficient.
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
The digital potentiometer easily generates a voltage divider at
wiper-to-B and wiper-to-A proportional to the input voltage at
A-to-B. Unlike the polarity of V
DD
to GND, which must be
positive, voltage across AB, WA, and WB can be at either
polarity.
A
V
I
W
B
V
O
04104-0-035
Figure 33. Potentiometer Mode Configuration
If ignoring the effect of the wiper resistance for approximation,
connecting the A terminal to 5 V and the B terminal to ground
produces an output voltage at the wiper-to-B starting at 0 V up
to 1 LSB less than 5 V. Each LSB of voltage is equal to the
voltage applied across Terminal AB divided by the 256 positions
of the potentiometer divider. The general equation defining the
output voltage at V
W
with respect to ground for any valid input
voltage applied to Terminal A and Terminal B is
B
A
W
V
D
V
D
D
V
256
256
256
)
(
-
+
=
(3)
For a more accurate calculation, which includes the effect of
wiper resistance, V
W
can be found as
B
AB
WA
A
AB
WB
W
V
R
D
R
V
R
D
R
D
V
)
(
)
(
)
(
+
=
(4)
Operation of the digital potentiometer in the divider mode
results in a more accurate operation over temperature. Unlike
the rheostat mode, the output voltage is dependent mainly on
the ratio of the internal resistors, R
WA
and R
WB
, and not the ab-
solute values. Thus, the temperature drift reduces to 15 ppm/C.
AD5170
Rev. A | Page 14 of 24
ESD PROTECTION
All digital inputs--SDA, SCL, AD0, and AD1--are protected
with a series input resistor and parallel Zener ESD structures, as
shown in Figure 34 and Figure 35.
LOGIC
340
GND
04104-0-037
Figure 34. ESD Protection of Digital Pins
A, B, W
GND
04104-0-038
Figure 35. ESD Protection of Resistor Terminals
TERMINAL VOLTAGE OPERATING RANGE
The AD5170 V
DD
to GND power supply defines the boundary
conditions for proper 3-terminal digital potentiometer opera-
tion. Supply signals present on Terminal A, Terminal B, and
Terminal W that exceed V
DD
or GND will be clamped by the
internal forward-biased diodes (see Figure 36).
GND
A
W
B
V
DD
04104-0-039
Figure 36. Maximum Terminal Voltages Set by V
DD
and GND
POWER-UP SEQUENCE
Because the ESD protection diodes limit the voltage compliance
at Terminal A, Terminal B, and Terminal W (see Figure 36), it is
important to power V
DD
/GND before applying any voltage to
Terminal A, Terminal B, and Terminal W. Otherwise, the diode
will be forward biased such that V
DD
is powered unintentionally
and may affect the rest of the user's circuit. The ideal power-up
sequence is GND, V
DD
, the digital inputs, and then V
A
/V
B
/V
W
.
The relative order of powering V
A
, V
B
, V
W
, and the digital
inputs is not important as long as they are powered after
V
DD
/GND.
POWER SUPPLY CONSIDERATIONS
To minimize the package pin count, both the one-time pro-
gramming and normal operating voltage supplies share the
same V
DD
terminal of the AD5170. The AD5170 employs fuse
link technology that requires 5.25 V to 5.5 V for blowing the
internal fuses to achieve a given setting, but normal V
DD
can be
anywhere between 2.7 V and 5.5 V after the fuse programming
process. As a result, dual voltage supplies and isolation are
needed if system V
DD
is lower than the required V
DD_OTP
. The
fuse programming supply (either an on-board regulator or
rack-mount power supply) must be rated at 5.25 V to 5.5 V and
able to provide a 100 mA current for 400 ms for successful one-
time programming. Once fuse programming is completed, the
V
DD_OTP
supply must be removed to allow normal operation at
2.7 V to 5.5 V and the device will consume current in A range.
Figure 37 shows the simplest implementation of a dual supply
requirement by using a jumper. This approach saves one voltage
supply, but draws additional current and requires manual
configuration.
V
DD
5.5V
R1
50k
R2
C1
10
F
C2
1nF
250k
CONNECT J1 HERE
FOR OTP
CONNECT J1 HERE
AFTER OTP
AD5170
04104-0-049
Figure 37. Power Supply Requirement
An alternate approach in 3.5 V to 5.25 V systems adds a signal
diode between the system supply and the OTP supply for
isolation, as shown in Figure 38.
V
DD
3.5V5.25V
5.5V
D1
C1
1
F
C2
1nF
APPLY FOR OTP ONLY
AD5170
04104-0-050
Figure 38. Isolate 5.5 V OTP Supply from 3.5 V to 5.25 V Normal Operating
Supply. The V
DD_OTP
must be removed once OTP is completed.
V
DD
2.7V
5.5V
P1
P1=P2=FDV302P, NDS0610
R1
10k
P2
C1
10
F
C2
1nF
APPLY FOR OTP ONLY
AD5170
04104-0-051
Figure 39. Isolate 5.5 V OTP Supply from 2.7 V Normal Operating Supply.
The V
DD_OTP
supply must be removed once OTP is completed.
For users who operate their systems at 2.7 V, use of the
bidirectional low threshold P-Ch MOSFETs is recommended
for the supply's isolation. As shown in Figure 39, this assumes
AD5170
Rev. A | Page 15 of 24
the 2.7 V system voltage is applied first, and the P1 and P2 gates
are pulled to ground, thus turning on P1 and subsequently P2.
As a result, V
DD
of the AD5170 approaches 2.7 V. When the
AD5170 setting is found, the factory tester applies the V
DD_OTP
to both the V
DD
and the MOSFETs gates turning off P1 and P2.
The OTP command is executed at this time to program the
AD5170 while the 2.7 V source is protected. Once the fuse
programming is completed, the tester withdraws the V
DD_OTP
and the setting for AD5170 is permanently fixed.
AD5170 achieves the OTP function through blowing internal
fuses. Users should always apply the 5.25 V to 5.5 V one-time
program voltage requirement at the first fuse programming
attempt. Failure to comply with this requirement may lead to a
change in the fuse structures, rendering programming
inoperable.
Poor PCB layout introduces parasitics that may affect the fuse
programming. Therefore, it is recommended to add a 10 F
tantalum capacitor in parallel with a 1 nF ceramic capacitor as
close as possible to the V
DD
pin. The type and value chosen for
both capacitors are important. This combination of capacitor
values provides both a fast response and larger supply current
handling with minimum supply droop during transients. As a
result, these capacitors increase the OTP programming success
by not inhibiting the proper energy needed to blow the internal
fuses. Additionally, C1
minimizes transient disturbance and low
frequency ripple while C2 reduces high frequency noise during
normal operation.
LAYOUT CONSIDERATIONS
It is good practice to employ compact, minimum lead length
layout design. The leads to the inputs should be as direct as
possible with a minimum conductor length. Ground paths
should have low resistance and low inductance.
Note that the digital ground should also be joined remotely to
the analog ground at one point to minimize the ground bounce.
V
DD
GND
V
DD
C1
10
F
C2
1nF
AD5170
+
04104-0-040
Figure 40. Power Supply Bypassing
AD5170
Rev. A | Page 16 of 24
EVALUATION SOFTWARE/HARDWARE
Figure 41. AD5170 Computer Software Interface
There are two ways of controlling the AD5170. Users can either
program the devices with computer software or external I
2
C
controllers.
SOFTWARE PROGRAMMING
Due to the advantages of the one-time programmable feature,
users may consider programming the device in the factory
before shipping the final product to end-users. ADI offers
device programming software that can be implemented in the
factory on PCs running Windows 95 or later. As a result,
external controllers are not required, which significantly
reduces development time. The program is an executable file
that does not require knowledge of any programming languages
or programming skills. It is easy to set up and to use. Figure 41
shows the software interface. The software can be downloaded
from
www.analog.com
.
The AD5170 starts at midscale after power-up prior to OTP
programming. To increment or decrement the resistance, the
user may simply move the scrollbars on the left. To write any
specific value, the user should use the bit pattern in the upper
screen and press the Run button. The format of writing data to
the device is shown in Table 7. Once the desired setting is
found, the user presses the Program Permanent button to blow
the internal fuse links.
To read the validation bits and data from the device, the user
simply presses the Read button. The format of the read bits is
shown in Table 8.
To apply the device programming software in the factory, users
must modify a parallel port cable and configure Pin 2, Pin 3,
Pin 15, and Pin 25 for SDA_write, SCL, SDA_read, and DGND,
respectively, for the control signals (Figure 42). Users should
also lay out the PCB of the AD5170 with SCL and SDA pads, as
shown in Figure 43, such that pogo pins can be inserted for
factory programming.
AD5170
Rev. A | Page 17 of 24
13
25
12
24
11
23
10
22
9
21
8
20
7
19
6
18
5
17
4
16
3
15
2
14
1
SCL
R3
100
R2
100
R1
100
SDA
READ
WRITE
04104-0-042
Figure 42. Parallel Port Connection. Pin 2 = SDA_write, Pin 3 = SCL,
Pin 15 = SDA_read, and Pin 25 = DGND.
AD5170
B
A
AD0
GND
VDD
W
NC
AD1
SDA
SCL
04104-0-043
Figure 43. Recommended AD5170 PCB Layout. The SCL and SDA pads allow
pogo pins to be inserted so that signals can be communicated through the
parallel port for programming (Figure 42).
AD5170
Rev. A | Page 18 of 24
I
2
C INTERFACE
Table 7. Write Mode
S 0 1 0 1 1
AD1
AD0
W
A 2T
SD
T 0 OW X X X A D7 D6 D5 D4
D3
D2
D1 D0
A P
Slave Address Byte
Instruction Byte
Data Byte
Table 8. Read Mode
S 0 1 0 1 1
AD1
AD0
R A D7
D6 D5 D4 D3 D2 D1 D0
A E1
E0
X X X X X X A P
Slave Address Byte
Instruction Byte
Data Byte
S = Start Condition.
P = Stop Condition.
A = Acknowledge.
AD0, AD1 = Package Pin Programmable Address Bits.
X = Don't Care.
W = Write.
R = Read.
2T = Second fuse link array for two-time programming. Logic 0
corresponds to first trim. Logic 1 corresponds to second trim.
Note that blowing trim #2 before trim #1 effectively disables
trim #1 and in turn only allows one-time programming.
SD = Shutdown connects wiper to B terminal and open circuits
the A terminal. It does not change the contents of the wiper
register.
T = OTP Programming Bit. Logic 1 permanently programs the
wiper.
OW = Overwrite the fuse setting and program the digital
potentiometer to a different setting. Note that upon power-up,
the digital potentiometer presets to either midscale or fuse
setting depending on whether the fuse link has been blown.
D7, D6, D5, D4, D3, D2, D1, D0 = Data Bits.
E1, E0 = OTP Validation Bits.
0, 0 = Ready to Program.
1, 0 = Fatal Error. Some fuses not blown. Do not retry.
Discard this unit.
1, 1 = Programmed Successfully. No further adjustments are
possible.
AD5170
Rev. A | Page 19 of 24
04104-0-044
t
1
t
2
t
3
t
8
t
8
t
9
t
9
t
6
t
4
t
7
t
5
t
2
t
10
P
S
S
SCL
SDA
P
Figure 44. I
2
C Interface Detailed Timing Diagram
04104-0-045
SCL
START BY
MASTER
SDA
0
1
1
FRAME 1
SLAVE ADDRESS BYTE
0
1
1
AD1 AD0
FRAME 2
INSTRUCTION BYTE
ACK BY
AD5170
R/W
A0
SD
0
OW X
X
X
1
9
D7
D6
D5
D4
D3
ACK BY
AD5170
FRAME 3
DATA BYTE
1
9
T
STOP BY
MASTER
9
D2
D1
D0
ACK BY
AD5170
Figure 45. Writing to the RDAC Register
04104-0-046
SCL
START BY
MASTER
SDA
0
1
1
FRAME 1
SLAVE ADDRESS BYTE
0
1
1
AD1 AD0
FRAME 2
INSTRUCTION BYTE
ACK BY
AD5170
R/W
D7
D6
D4
D3
D2
D1
D0
1
9
E1
E0
X
X
X
ACK BY
MASTER
FRAME 3
DATA BYTE
1
9
D5
STOP BY
MASTER
9
X
X
X
NO ACK
BY MASTER
Figure 46. Reading Data from the RDAC Register
AD5170
Rev. A | Page 20 of 24
I
2
C COMPATIBLE 2-WIRE SERIAL BUS
The 2-wire I
2
C serial bus protocol operates as follows:
1.
The master initiates data transfer by establishing a START
condition, which is when a high-to-low transition on the
SDA line occurs while SCL is high (see Figure 45). The
following byte is the slave address byte, which consists of
the slave address followed by an R/W bit (this bit deter-
mines whether data is read from, or written to, the slave
device). AD0 and AD1 are configurable address bits which
allow up to four devices on one bus (see Table 7).
The slave address corresponding to the transmitted address
bits responds by pulling the SDA line low during the ninth
clock pulse (this is termed the Acknowledge bit). At this
stage, all other devices on the bus remain idle while the
selected device waits for data to be written to, or read from,
its serial register. If the R/W bit is high, the master will read
from the slave device. If the R/W bit is low, the master will
write to the slave device.
2.
In the write mode, the second byte is the instruction byte.
The first bit (MSB), 2T, of the instruction byte is the
second trim enable bit. A logic low selects the first array of
fuses, and a logic high selects the second array. This means
that after blowing the fuses with trim#1, the user still has
another chance to blow them again with trim#2. Note that
using trim#2 before trim#1 effectively disables trim#1 and,
in turn, only allows one-time programming.
The second MSB, SD, is a shutdown bit. A logic high causes
an open circuit at Terminal A while shorting the wiper to
Terminal B. This operation yields almost 0 in rheostat
mode or 0 V in potentiometer mode. It is important to
note that the shutdown operation does not disturb the
contents of the register. When brought out of shutdown,
the previous setting is applied to the RDAC. Also, during
shutdown, new settings can be programmed. When the
part is returned from shutdown, the corresponding VR
setting is applied to the RDAC.
The third MSB, T, is the OTP (one-time programmable)
programming bit. A logic high blows the poly fuses and
programs the resistor setting permanently. For example, if
the user wanted to blow the first array of fuses, the
instruction byte would be 00100XXX. To blow the second
array of fuses, the instruction byte would be 10100XXX. A
logic low of the T bit simply allows the device to act as a
typical volatile digital potentiometer.
The fourth MSB must always be at Logic 0.
The fifth MSB, OW, is an overwrite bit. When raised to a
logic high, OW allows the RDAC setting to be changed
even after the internal fuses have been blown. However,
once OW is returned to a logic zero, the position of the
RDAC returns to the setting prior to overwrite. Because
OW is not static, if the device is powered off and on, the
RDAC presets to midscale or to the setting at which the
fuses were blown, depending on whether the fuses have
been permanently set.
The remainder of the bits in the instruction byte are Don't
Care bits (see Figure 45).
After acknowledging the instruction byte, the last byte in
write mode is the data byte. Data is transmitted over the
serial bus in sequences of nine clock pulses (eight data bits
followed by an Acknowledge bit). The transitions on the
SDA line must occur during the low period of SCL and
remain stable during the high period of SCL (see
Figure 44).
3.
In the read mode, the data byte follows immediately after
the acknowledgment of the slave address byte. Data is
transmitted over the serial bus in sequences of nine clock
pulses (a slight difference from the write mode, with eight
data bits followed by an Acknowledge bit). Similarly, the
transitions on the SDA line must occur during the low
period of SCL and remain stable during the high period of
SCL (see Figure 46).
Following the data byte, the validation byte contains two
validation bits, E0 and E1. These bits signify the status of
the one-time programming (see Figure 46).
4.
After all data bits have been read or written, a STOP
condition is established by the master. A STOP condition is
defined as a low-to-high transition on the SDA line while
SCL is high. In write mode, the master pulls the SDA line
high during the 10
th
clock pulse to establish a STOP
condition (see Figure 45). In read mode, the master issues a
No Acknowledge for the 9
th
clock pulse (i.e., the SDA line
remains high). The master then brings the SDA line low
before the 10
th
clock pulse, which goes high to establish a
STOP condition (see Figure 46).
A repeated write function gives the user flexibility to update the
RDAC output a number of times after addressing and instructing
the part only once. For example, after the RDAC has acknowledged
its slave address and instruction bytes in the write mode, the
RDAC output updates on each successive byte. If different
instructions are needed, the write/read mode has to start again
with a new slave address, instruction, and data byte. Similarly, a
repeated read function of the RDAC is also allowed.
AD5170
Rev. A | Page 21 of 24
Table 9. Validation Status
E1 E0 Status
0
0
Ready for Programming.
1 0 Fatal Error. Some fuses not blown. Do not retry.
Discard this unit.
1
1
Successful. No further programming is possible.
Multiple Devices on One Bus
Figure 47 shows four AD5170s on the same serial bus. Each has
a different slave address because the states of their AD0 and
AD1 pins are different. This allows each device on the bus to be
written to, or read from, independently. The master device
output bus line drivers are open-drain pull-downs in a fully I
2
C
compatible interface.
SDA
SDA
AD1
AD0
MASTER
SCL
SCL
AD5170
SDA
AD1
AD0
SCL
AD5170
SDA
AD1
AD0
SCL
AD5170
SDA
5V
R
P
R
P
5V
5V
5V
AD1
AD0
SCL
AD5170
04104-0-047
Figure 47. Multiple AD5170s on One I
2
C Bus
AD5170
Rev. A | Page 22 of 24
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
10
9
8
7
1
2
3
4
B
A
AD0
W
NC
AD1
SDA
GND
6
5
SCL
V
DD
TOP VIEW
AD5170
04104-0-048
Figure 48. Pin Configuration
Table 10. Pin Function Descriptions
Pin Mnemonic
Description
1 B
B
Terminal.
2 A
A
Terminal.
3
AD0
Programmable Address Bit 0 for Multiple Package Decoding.
4 GND
Digital
Ground.
5 V
DD
Positive Power Supply.
6
SCL
Serial Clock Input. Positive Edge Triggered.
7
SDA
Serial Data Input/Output.
8
AD1
Programmable Address Bit 1 for Multiple Package Decoding.
9 NC
No
Connect.
10 W
W
Terminal.
AD5170
Rev. A | Page 23 of 24
OUTLINE DIMENSIONS
0.23
0.08
0.80
0.60
0.40
8
0
0.15
0.00
0.27
0.17
0.95
0.85
0.75
SEATING
PLANE
1.10 MAX
10
6
5
1
0.50 BSC
3.00 BSC
3.00 BSC
4.90 BSC
PIN 1
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187BA
Figure 49. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
ORDERING GUIDE
Model R
AB
(k)
Temperature
Package Description
Package Option
Branding
AD5170BRM2.5
2.5
40C to +125C
MSOP-10
RM-10
D0Y
AD5170BRM2.5-RL7
2.5
40C to +125C
MSOP-10
RM-10
D0Y
AD5170BRM10
10
40C to +125C
MSOP-10
RM-10
D0Z
AD5170BRM10-RL7
10
40C to +125C
MSOP-10
RM-10
D0Z
AD5170BRM50
50
40C to +125C
MSOP-10
RM-10
D0W
AD5170BRM50-RL7
50
40C to +125C
MSOP-10
RM-10
D0W
AD5170BRM100
100
40C to +125C
MSOP-10
RM-10
D0X
AD5170BRM100-RL7
100
40C to +125C
MSOP-10
RM-10
D0X
AD5170EVAL
1
Evaluation
Board
1
The evaluation board is shipped with the 10 k RAB resistor option; however, the board is compatible with all available resistor value options.
AD5170
Rev. A | Page 24 of 24
NOTES
Purchase of licensed I
2
C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I
2
C Patent
Rights to use these components in an I
2
C system, provided that the system conforms to the I
2
C Standard Specification as defined by Philips.
2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04104011/04(A)
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