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Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
AD5307/AD5317/AD5327*
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
Analog Devices, Inc., 2000
FEATURES
AD5307: Four Buffered 8-Bit DACs in 16-Lead TSSOP
AD5317: Four Buffered 10-Bit DACs in 16-Lead TSSOP
AD5327: Four Buffered 12-Bit DACs in 16-Lead TSSOP
Low Power Operation: 400 A @ 3 V, 500 A @ 5 V
2.5 V to 5.5 V Power Supply
Guaranteed Monotonic By Design over All Codes
Power-Down to 90 nA @ 3 V, 300 nA @ 5 V (
PD Pin)
Double-Buffered Input Logic
Buffered/Unbuffered Reference Input Options
Output Range: 0V
REF
or 02 V
REF
Power-On-Reset to Zero Volts
Simultaneous Update of Outputs (
LDAC Pin)
Asynchronous Clear Facility (
CLR Pin)
Low Power, SPITM, QSPITM, MICROWIRETM and DSP-
Compatible 3-Wire Serial Interface
SDO Daisy-Chaining Option
On-Chip Rail-to-Rail Output Buffer Amplifiers
Temperature Range 40 C to +105 C
APPLICATIONS
Portable Battery-Powered Instruments
Digital Gain and Offset Adjustment
Programmable Voltage and Current Sources
Programmable Attenuators
Industrial Process Control
GENERAL DESCRIPTION
The AD5307/AD5317/AD5327 are quad 8-, 10-, and 12-bit
buffered voltage-output DACs, in a 16-lead TSSOP package,
which operate from a single 2.5 V to 5.5 V supply consuming
400
A at 3 V. Their on-chip output amplifiers allow the outputs
to swing rail-to-rail with a slew rate of 0.7 V/
s. The AD5307/
AD5317/AD5327 utilize a versatile 3-wire serial interface that
operates at clock rates up to 30 MHz and is compatible with stan-
dard SPI, QSPI, MICROWIRE, and DSP interface standards.
The references for the four DACs are derived from two refer-
ence pins (one per DAC pair). These reference inputs can be
configured as buffered or unbuffered inputs. The parts incorpo-
rate a power-on-reset circuit that ensures that the DAC outputs
power-up to 0 V and remain there until a valid write to the device
takes place. There is also an asynchronous active-low
CLR pin
that clears all DACs to 0 V. The outputs of all DACs may be
updated simultaneously using the asynchronous
LDAC input.
The parts contain a power-down feature that reduces the current
consumption of the devices to 300 nA @ 5 V (90 nA @ 3 V).
The parts may also be used in daisy-chaining applications using
the SDO pin.
All three parts are offered in the same pinout, which allows
users to select the amount of resolution appropriate for their
application without redesigning their circuit board.
FUNCTIONAL BLOCK DIAGRAM
INPUT
REGISTER
V
OUT
A
BUFFER
STRING
DAC A
V
DD
GND
AD5307/AD5317/AD5327
V
OUT
B
BUFFER
STRING
DAC B
V
OUT
C
BUFFER
STRING
DAC C
V
OUT
D
BUFFER
STRING
DAC D
GAIN-SELECT
LOGIC
V
REF
AB
V
REF
CD
SYNC
SCLK
DIN
SDO
CLR
DCEN
LDAC
PD
POWER-ON
RESET
POWER-DOWN
LOGIC
LDAC
DAC
REGISTER
INPUT
REGISTER
DAC
REGISTER
INPUT
REGISTER
DAC
REGISTER
INPUT
REGISTER
DAC
REGISTER
INTERFACE
LOGIC
*Protected by U.S. Patent No. 5,969,657; other patents pending.
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corporation.
2.5 V to 5.5 V, 400 A, Quad Voltage Output
8-/10-/12-Bit DACs in 16-Lead TSSOP
REV. 0
2
B Version
2
Parameter
1
Min
Typ
Max
Unit
Conditions/Comments
DC PERFORMANCE
3, 4
AD5307
Resolution
8
Bits
Relative Accuracy
0.15
1
LSB
Differential Nonlinearity
0.02
0.25 LSB
Guaranteed Monotonic by Design Over All Codes
AD5317
Resolution
10
Bits
Relative Accuracy
0.5
4
LSB
Differential Nonlinearity
0.05
0.5
LSB
Guaranteed Monotonic by Design Over All Codes
AD5327
Resolution
12
Bits
Relative Accuracy
2
16
LSB
Differential Nonlinearity
0.2
1
LSB
Guaranteed Monotonic by Design Over All Codes
Offset Error
5
60
mV
V
DD
= 4.5 V, Gain = 2; See Figures 4 and 5
Gain Error
0.3
1.25 % of FSR
V
DD
= 4.5 V, Gain = 2; See Figures 4 and 5
Lower Deadband
5
10
60
mV
See Figure 4. Lower Deadband Exists Only If Offset Error Is Negative
Upper Deadband
5
10
60
mV
See Figure 5. Upper Deadband Exists Only If V
REF
= V
DD
and
Offset Plus Gain Error is Positive
Offset Error Drift
6
12
ppm of FSR/
C
Gain Error Drift
6
5
ppm of FSR/
C
DC Power Supply Rejection Ratio
6
60
dB
V
DD
=
10%
DC Crosstalk
6
200
V
R
L
= 2 k
to GND or V
DD
DAC REFERENCE INPUTS
6
V
REF
Input Range
1
V
DD
V
Buffered Reference Mode
0.25
V
DD
V
Unbuffered Reference Mode
V
REF
Input Impedance (R
DAC
)
>10
M
Buffered Reference Mode and Power-Down Mode
74
90
k
Unbuffered Reference Mode. 0V
REF
Output Range
37
45
k
Unbuffered Reference Mode. 02 V
REF
Output Range
Reference Feedthrough
90
dB
Frequency = 10 kHz
Channel-to-Channel Isolation
75
dB
Frequency = 10 kHz
OUTPUT CHARACTERISTICS
6
Minimum Output Voltage
7
0.001
V
This is a measure of the minimum and maximum drive
Maximum Output Voltage
7
V
DD
0.001
V
capability of the output amplifier.
DC Output Impedance
0.5
Short Circuit Current
25
mA
V
DD
= 5 V
16
mA
V
DD
= 3 V
Power-Up Time
2.5
s
Coming Out of Power-Down Mode. V
DD
= 5 V
5
s
Coming Out of Power-Down Mode. V
DD
= 3 V
LOGIC INPUTS
6
Input Current
1
A
V
IL
, Input Low Voltage
0.8
V
V
DD
= 5 V
10%
0.6
V
V
DD
= 3 V
10%
0.5
V
V
DD
= 2.5 V
V
IH
, Input High Voltage (excl. DCEN)
1.7
V
V
DD
= 2.5 V to 5.5 V; TTL and 1.8 V CMOS-Compatible
V
IH
, Input High Voltage (DCEN)
2.4
V
V
DD
= 5 V
10%
2.1
V
V
DD
= 3 V
10%
2.0
V
V
DD
= 2.5 V
Pin Capacitance
3
pF
LOGIC OUTPUT (SDO)
6
V
DD
= 4.5 V to 5.5 V
Output Low Voltage, V
OL
0.4
V
I
SINK
= 2 mA
Output High Voltage, V
OH
V
DD
1
V
I
SOURCE
= 2 mA
V
DD
= 2.5 V to 3.6 V
Output Low Voltage, V
OL
0.4
V
I
SINK
= 2 mA
Output High Voltage, V
OH
V
DD
0.5
V
I
SOURCE
= 2 mA
Floating-State Leakage Current
1
A
DCEN = GND
Floating State O/P Capacitance
3
pF
DCEN = GND
POWER REQUIREMENTS
V
DD
2.5
5.5
V
I
DD
(Normal Mode)
8
V
IH
= V
DD
and V
IL
= GND
V
DD
= 4.5 V to 5.5 V
500
900
A
All DACs in Unbuffered Mode. In Buffered Mode, extra
V
DD
= 2.5 V to 3.6 V
400
750
A
current is typically x
A per DAC where x = 5 A + V
REF
/R
DAC
.
I
DD
(Power-Down Mode)
V
IH
= V
DD
and V
IL
= GND
V
DD
= 4.5 V to 5.5 V
0.3
1
A
V
DD
= 2.5 V to 3.6 V
0.09
1
A
AD5307/AD5317/AD5327SPECIFICATIONS
(V
DD
= 2.5 V to 5.5 V; V
REF
= 2 V; R
L
= 2 k
to
GND; C
L
= 200 pF to GND; all specifications T
MIN
to T
MAX
unless otherwise noted.)
REV. 0
3
AD5307/AD5317/AD5327
NOTES
1
See Terminology.
2
Temperature range: B Version: 40
C to +105C; typical at 25C.
3
DC specifications tested with the outputs unloaded unless stated otherwise.
4
Linearity is tested using a reduced code range: AD5307 (Code 8 to 255); AD5317 (Code 28 to 1023); AD5327 (Code 115 to 4095).
5
This corresponds to x codes. x = Deadband Voltage/LSB size.
6
Guaranteed by design and characterization; not production tested.
7
For the amplifier output to reach its minimum voltage, Offset Error must be negative; for the amplifier output to reach its maximum voltage, V
REF
= V
DD
and Offset plus Gain
Error must be positive.
8
Interface Inactive. All DACs active. DAC outputs unloaded.
Specifications subject to change without notice.
AC CHARACTERISTICS
1
B Version
3
Parameter
2
Min
Typ
Max
Unit
Conditions/Comments
Output Voltage Settling Time
V
REF
= V
DD
= 5 V
AD5307
6
8
s
1/4 Scale to 3/4 Scale
Change
(40 Hex to C0 Hex)
AD5317
7
9
s
1/4 Scale to 3/4 Scale
Change
(100 Hex to 300 Hex)
AD5327
8
10
s
1/4 Scale to 3/4 Scale
Change
(400 Hex to C00 Hex)
Slew Rate
0.7
V/
s
Major-Code Change Glitch Energy
12
nV sec
1 LSB Change Around Major Carry
Digital Feedthrough
0.5
nV sec
SDO Feedthrough
4
nV sec
Daisy-Chain Mode; SDO Load is 10 pF
Digital Crosstalk
0.5
nV sec
Analog Crosstalk
1
nV sec
DAC-to-DAC Crosstalk
3
nV sec
Multiplying Bandwidth
200
kHz
V
REF
= 2 V
0.1 V p-p. Unbuffered Mode
Total Harmonic Distortion
70
dB
V
REF
= 2.5 V
0.1 V p-p. Frequency = 10 kHz
NOTES
1
Guaranteed by design and characterization; not production tested.
2
See Terminology.
3
Temperature range: B Version: 40
C to +105C
; typical at 25
C.
Specifications subject to change without notice.
TIMING CHARACTERISTICS
1, 2, 3
B Version
Parameter
Limit at T
MIN
, T
MAX
Unit
Conditions/Comments
t
1
33
ns min
SCLK Cycle Time
t
2
13
ns min
SCLK High Time
t
3
13
ns min
SCLK Low Time
t
4
13
ns min
SYNC to SCLK Falling Edge Setup Time
t
5
5
ns min
Data Setup Time
t
6
4.5
ns min
Data Hold Time
t
7
0
ns min
SCLK Falling Edge to
SYNC Rising Edge
t
8
50
ns min
Minimum
SYNC High Time
t
9
20
ns min
LDAC Pulsewidth
t
10
20
ns min
SCLK Falling Edge to
LDAC Rising Edge
t
11
20
ns min
CLR Pulsewidth
t
12
0
ns min
SCLK Falling Edge to
LDAC Falling Edge
t
13
4, 5
20
ns max
SCLK Rising Edge to SDO Valid (V
DD
= 3.6 V to 5.5 V)
25
ns max
SCLK Rising Edge to SDO Valid (V
DD
= 2.5 V to 3.5 V)
t
14
5
5
ns min
SCLK Falling Edge to
SYNC Rising Edge
t
15
5
8
ns min
SYNC Rising Edge to SCLK Rising Edge
t
16
5
0
ns min
SYNC Rising Edge to LDAC Falling Edge
NOTES
1
Guaranteed by design and characterization; not production tested.
2
All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2.
3
See Figures 2 and 3.
4
This is measured with the load circuit of Figure 1. t
13
determines maximum SCLK frequency in Daisy-Chain Mode.
5
Daisy-Chain Mode only.
Specifications subject to change without notice.
(V
DD
= 2.5 V to 5.5 V; R
L
= 2 k
to GND; C
L
= 200 pF to GND; all specifications T
MIN
to T
MAX
unless
otherwise noted.)
(V
DD
= 2.5 V to 5.5 V; all specifications T
MIN
to T
MAX
unless otherwise noted.)
REV. 0
AD5307/AD5317/AD5327
4
I
OH
I
OL
TO OUTPUT
PIN
V
OH (MIN)
C
L
50pF
2mA
2mA
Figure 1. Load Circuit for Digital Output (SDO) Timing Specifications
SCLK
SYNC
DIN
t
2
t
3
t
5
t
6
t
7
DB15
t
1
DB0
t
9
t
10
LDAC
1
LDAC
2
t
8
t
11
CLR
t
12
NOTES
1. ASYNCHRONOUS
LDAC UPDATE MODE.
2. SYNCHRONOUS
LDAC UPDATE MODE.
t
4
Figure 2. Serial Interface Timing Diagram
SCLK
SYNC
DIN
t
2
t
3
t
5
t
6
t
4
t
1
t
14
DB15
DB0
DB15'
DB0'
DB0
SDO
INPUT WORD FOR DAC N
INPUT WORD FOR DAC (N+1)
UNDEFINED
INPUT WORD FOR DAC N
t
8
t
15
t
13
DB15
t
16
t
9
LDAC
Figure 3. Daisy-Chaining Timing Diagram
REV. 0
AD5307/AD5317/AD5327
5
ABSOLUTE MAXIMUM RATINGS
1, 2
(T
A
= 25
C unless otherwise noted)
V
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to +7 V
Digital Input Voltage to GND . . . . . . . 0.3 V to V
DD
+ 0.3 V
Digital Output Voltage to GND . . . . . 0.3 V to V
DD
+ 0.3 V
Reference Input Voltage to GND . . . . 0.3 V to V
DD
+ 0.3 V
V
OUT
AV
OUT
D to GND . . . . . . . . . . . 0.3 V to V
DD
+ 0.3 V
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . 40
C to +105C
Storage Temperature Range . . . . . . . . . . . . 65
C to +150C
Junction Temperature (T
J
max) . . . . . . . . . . . . . . . . . . 150
C
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD5307/AD5317/AD5327 features proprietary ESD protection circuitry, permanent damage
may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
16-Lead TSSOP Package
Power Dissipation . . . . . . . . . . . . . . . . . . (T
J
max T
A
)/
JA
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . 150.4
C/W
Reflow Soldering
Peak Temperature . . . . . . . . . . . . . . . . . . . 220 +5/0
C
Time at Peak Temperature . . . . . . . . . . 10 sec to 40 sec
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
Transient currents of up to 100 mA will not cause SCR latch-up.
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
AD5307BRU
40
C to +105C
Thin Shrink Small Outline Package (TSSOP)
RU-16
AD5317BRU
40
C to +105C
Thin Shrink Small Outline Package (TSSOP)
RU-16
AD5327BRU
40
C to +105C
Thin Shrink Small Outline Package (TSSOP)
RU-16
Document Outline
- FEATURES
- GENERAL DESCRIPTION
- SPECIFICATIONS
- ABSOLUTE MAXIMUM RATINGS
- ORDERING GUIDE
- PIN FUNCTION DESCRIPTIONS
- TERMINOLOGY
- FUNCTIONAL DESCRIPTION
- SERIAL INTERFACE
- POWER-DOWN MODE
- MICROPROCESSOR INTERFACING
- APPLICATIONS
- OUTLINE DIMENSIONS
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