Document Outline
- FEATURES
- APPLICATIONS
- GENERAL DESCRIPTION
- FUNCTIONAL BLOCK DIAGRAM
- SPECIFICATIONS
- AC CHARACTERISTICS
- TIMING CHARACTERISTICS
- ABSOLUTE MAXIMUM RATINGS
- ORDERING GUIDE
- PIN CONFIGURATION
- PIN FUNCTION DESCRIPTIONS
- TERMINOLOGY
- Relative Accuracy
- Differential Nonlinearity
- Offset Error
- Gain Error
- Offset Error Drift
- Gain Error Drift
- Power Supply Rejection Ratio (PSRR)
- DC Crosstalk
- Reference Feedthrough
- Major-Code Transition Glitch Energy
- Digital Feedthrough
- Digital Crosstalk
- DAC-to-DAC Crosstalk
- Multiplying Bandwidth
- Total Harmonic Distortion
- Typical Performance Characteristics
- FUNCTIONAL DESCRIPTION
- Digital-to-Analog Section
- Resistor String
- DAC Reference Inputs
- Output Amplifier
- POWER-ON RESET
- SERIAL INTERFACE
- Read/Write Sequence
- Pointer Byte Bits
- Input Shift Register
- Default Readback Condition
- Multiple-DAC Write Sequence
- Multiple-DAC Readback Sequence
- WRITE OPERATION
- READ OPERATION
- DOUBLE-BUFFERED INTERFACE
- POWER-DOWN MODES
- APPLICATIONS
- Typical Application Circuit
- Bipolar Operation Using the AD5305/AD5315/AD5325
- Multiple Devices on One Bus
- AD5305/AD5315/AD5325 as a Digitally Programmable Window Detector
- Coarse and Fine Adjustment Using the AD5305/AD5315/AD5325
- POWER SUPPLY DECOUPLING
- OUTLINE DIMENSIONS
- Revision History
REV. F
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
2004 Analog Devices, Inc. All rights reserved.
AD5305/AD5315/AD5325
*
2.5 V to 5.5 V, 500 A, 2-Wire Interface
Quad Voltage Output, 8-/10-/12-Bit DACs
*Protected by U.S.Patent No. 5,969,657and 5,684,481.
FEATURES
AD5305: 4 Buffered 8-Bit DACs in 10-Lead MSOP
A Version: 1 LSB INL, B Version: 0.625 LSB INL
AD5315: 4 Buffered 10-Bit DACs in 10-Lead MSOP
A Version: 4 LSB INL, B Version: 2.5 LSB INL
AD5325: 4 Buffered 12-Bit DACs in 10-Lead MSOP
A Version: 16 LSB INL, B Version: 10 LSB INL
Low Power Operation: 500 A @ 3 V, 600 A @ 5 V
2-Wire (I
2
C
Compatible) Serial Interface
2.5 V to 5.5 V Power Supply
Guaranteed Monotonic by Design over All Codes
Power-Down to 80 nA @ 3 V, 200 nA @ 5 V
Three Power-Down Modes
Double-Buffered Input Logic
Output Range: 0 V to V
REF
Power-On Reset to 0 V
Simultaneous Update of Outputs (
LDAC Function)
Software Clear Facility
Data Readback Facility
On-Chip Rail-to-Rail Output Buffer Amplifiers
Temperature Range 40 C to +105 C
APPLICATIONS
Portable Battery-Powered Instruments
Digital Gain and Offset Adjustment
Programmable Voltage and Current Sources
Programmable Attenuators
Industrial Process Control
FUNCTIONAL BLOCK DIAGRAM
INPUT
REGISTER
V
OUT
A
BUFFER
DAC
REGISTER
STRING
DAC A
V
DD
REF IN
GND
AD5305/AD5315/AD5325
INPUT
REGISTER
V
OUT
B
BUFFER
DAC
REGISTER
INPUT
REGISTER
V
OUT
C
BUFFER
DAC
REGISTER
INPUT
REGISTER
V
OUT
D
BUFFER
DAC
REGISTER
POWER-ON
RESET
SDA
SCL
A0
INTERFACE
LOGIC
POWER-DOWN
LOGIC
LDAC
STRING
DAC B
STRING
DAC C
STRING
DAC D
GENERAL DESCRIPTION
The AD5305/AD5315/AD5325 are quad 8-, 10-, and 12-bit
buffered voltage output DACs in a 10-lead MSOP that operate
from a single 2.5 V to 5.5 V supply, consuming 500
A at 3 V.
Their on-chip output amplifiers allow rail-to-rail output swing
with a slew rate of 0.7 V/
s. A 2-wire serial interface, which
operates at clock rates up to 400 kHz, is used. This interface is
SMBus compatible at V
DD
< 3.6 V. Multiple devices can be
placed on the same bus.
The references for the four DACs are derived from one reference
pin. The outputs of all DACs may be updated simultaneously
using the software
LDAC function. The parts incorporate a
power-on reset circuit, which ensures that the DAC outputs power
up to 0 V and remain there until a valid write takes place to the
device. There is also a software clear function that resets all input
and DAC registers to 0 V. The parts contain a power-down
feature that reduces the current consumption of the devices to
200 nA @ 5 V (80 nA @ 3 V).
The low power consumption of these parts in normal operation
makes them ideally suited to portable battery-operated equipment.
The power consumption is 3 mW at 5 V, 1.5 mW at 3 V, reducing
to 1
W in power-down mode.
REV. F
2
AD5305/AD5315/AD5325SPECIFICATIONS
(V
DD
= 2.5 V to 5.5 V; V
REF
= 2 V; R
L
= 2 k to GND;
C
L
= 200 pF to GND; all specifications T
MIN
to T
MAX
, unless otherwise noted.)
A Version
2
B Version
2
Parameter
1
Min
Typ
Max
Min
Typ
Max
Unit
Conditions/Comments
DC PERFORMANCE
3, 4
AD5305
Resolution
8
8
Bits
Relative Accuracy
0.15
1
0.15
0.625
LSB
Differential Nonlinearity
0.02
0.25
0.02
0.25
LSB
Guaranteed Monotonic by Design
over All Codes
AD5315
Resolution
10
10
Bits
Relative Accuracy
0.5
4
0.5
2.5
LSB
Differential Nonlinearity
0.05
0.5
0.05
0.5
LSB
Guaranteed Monotonic by Design
over All Codes
AD5325
Resolution
12
12
Bits
Relative Accuracy
2
16
2
10
LSB
Differential Nonlinearity
0.2
1
0.2
1
LSB
Guaranteed Monotonic by Design
over All Codes
Offset Error
0.4
3
0.4
3
% of FSR
Gain Error
0.15
1
0.15
1
% of FSR
Lower Deadband
20
60
20
60
mV
Lower deadband exists only if
offset error is negative.
Offset Error Drift
5
12
12
ppm of FSR/
C
Gain Error Drift
5
5
5
ppm of FSR/
C
Power Supply Rejection Ratio
5
60
60
dB
V
DD
=
10%
DC Crosstalk
5
200
200
V
R
L
= 2 k
to GND or V
DD
DAC REFERENCE INPUTS
5
V
REF
Input Range
0.25
V
DD
0.25
V
DD
V
V
REF
Input Impedance
37
45
37
45
k
Normal Operation
>10
>10
M
Power-Down Mode
Reference Feedthrough
90
90
dB
Frequency = 10 kHz
OUTPUT CHARACTERISTICS
5
Minimum Output Voltage
6
0.001
0.001
V
This is a measure of the minimum
and maximum drive capability
Maximum Output Voltage
6
V
DD
0.001
V
DD
0.001
V
of the output amplifier.
DC Output Impedance
0.5
0.5
Short Circuit Current
25
25
mA
V
DD
= 5 V
16
16
mA
V
DD
= 3 V
Power-Up Time
2.5
2.5
s
Coming out of Power-Down Mode.
V
DD
= 5 V
5
5
s
Coming out of Power-Down Mode.
V
DD
= 3 V
LOGIC INPUTS (A0)
5
Input Current
1
1
A
V
IL
, Input Low Voltage
0.8
0.8
V
V
DD
= 5 V
10%
0.6
0.6
V
V
DD
= 3 V
10%
0.5
0.5
V
V
DD
= 2.5 V
V
IH
, Input High Voltage
2.4
2.4
V
V
DD
= 5 V
10%
2.1
2.1
V
V
DD
= 3 V
10%
2.0
2.0
V
V
DD
= 2.5 V
Pin Capacitance
3
3
pF
LOGIC INPUTS (SCL, SDA)
5
V
IH
, Input High Voltage
0.7 V
DD
V
DD
+ 0.3
0.7 V
DD
V
DD
+ 0.3
V
SMBus Compatible at V
DD
< 3.6 V
V
IL
, Input Low Voltage
0.3
0.3 V
DD
0.3
0.3 V
DD
V
SMBus Compatible at V
DD
< 3.6 V
I
IN
, Input Leakage Current
1
1
A
V
HYST
, Input Hysteresis
0.05 V
DD
0.05 V
DD
V
C
IN
, Input Capacitance
8
8
pF
Glitch Rejection
50
50
ns
Input filtering suppresses noise
spikes of less than 50 ns.
LOGIC OUTPUT (SDA)
5
V
OL
, Output Low Voltage
0.4
0.4
V
I
SINK
= 3 mA
0.6
0.6
V
I
SINK
= 6 mA
Three-State Leakage Current
1
1
A
Three-State Output Capacitance
8
8
pF
REV. F
AD5305/AD5315/AD5325
3
AC CHARACTERISTICS
1
(V
DD
= 2.5 V to 5.5 V; R
L
= 2 k
to GND; C
L
= 200 pF to GND; all specifications T
MIN
to T
MAX
, unless
otherwise noted.)
A Version
2
B Version
2
Parameter
1
Min
Typ
Max
Min
Typ
Max
Unit
Conditions/Comments
POWER REQUIREMENTS
V
DD
2.5
5.5
2.5
5.5
V
I
DD
(Normal Mode)
7
V
IH
= V
DD
and V
IL
= GND
V
DD
= 4.5 V to 5.5 V
600
900
600
900
A
V
DD
= 2.5 V to 3.6 V
500
700
500
700
A
I
DD
(Power-Down Mode)
V
IH
= V
DD
and V
IL
= GND
V
DD
= 4.5 V to 5.5 V
0.2
1
0.2
1
A
I
DD
= 4
A (Max) During 0
Readback on SDA
V
DD
= 2.5 V to 3.6 V
0.08
1
0.08
1
A
I
DD
= 1.5
A (Max) During 0
Readback on SDA
NOTES
1
See the Terminology section.
2
Temperature range (A, B Version): 40
C to +105C; typical at +25C.
3
DC specifications tested with the outputs unloaded.
4
Linearity is tested using a reduced code range: AD5305 (Code 8 to 248); AD5315 (Code 28 to 995); AD5325 (Code 115 to 3981).
5
Guaranteed by design and characterization, not production tested.
6
For the amplifier output to reach its minimum voltage, offset error must be negative; to reach its maximum voltage, V
REF
= V
DD
and offset plus gain error must be
positive.
7
I
DD
specification is valid for all DAC codes. Interface inactive. All DACs active and excluding load currents.
Specifications subject to change without notice.
A, B Version
3
Parameter
2
Min
Typ
Max
Unit
Conditions/Comments
Output Voltage Settling Time
V
REF
= V
DD
= 5 V
AD5305
6
8
s
1/4 Scale to 3/4 Scale Change (0x40 to 0xC0)
AD5315
7
9
s
1/4 Scale to 3/4 Scale Change (0x100 to 0x300)
AD5325
8
10
s
1/4 Scale to 3/4 Scale Change (0x400 to 0xC00)
Slew Rate
0.7
V/
s
Major-Code Transition Glitch Energy
12
nV-s
1 LSB Change around Major Carry
Digital Feedthrough
1
nV-s
Digital Crosstalk
1
nV-s
DAC-to-DAC Crosstalk
3
nV-s
Multiplying Bandwidth
200
kHz
V
REF
= 2 V
0.1 V p-p
Total Harmonic Distortion
70
dB
V
REF
= 2.5 V
0.1 V p-p, Frequency = 10 kHz
NOTES
1
Guaranteed by design and characterization, not production tested.
2
See the Terminology section.
3
Temperature range (A, B Version): 40
C to +105C; typical at +25C.
Specifications subject to change without notice.
REV. F
4
AD5305/AD5315/AD5325
TIMING CHARACTERISTICS
1, 2
(V
DD
= 2.5 V to 5.5 V; all specifications T
MIN
to T
MAX
, unless otherwise noted.)
Limit at T
MIN
, T
MAX
Parameter
(A, B Version)
Unit
Conditions/Comments
f
SCL
400
kHz max
SCL Clock Frequency
t
1
2.5
s min
SCL Cycle Time
t
2
0.6
s min
t
HIGH
, SCL High Time
t
3
1.3
s min
t
LOW
, SCL Low Time
t
4
0.6
s min
t
HD,STA
, Start/Repeated Start Condition Hold Time
t
5
100
ns min
t
SU,DAT
, Data Setup Time
t
6
3
0.9
s max
t
HD,DAT
, Data Hold Time
0
s min
t
HD,DAT
, Data Hold Time
t
7
0.6
s min
t
SU,STA
, Setup Time for Repeated Start
t
8
0.6
s min
t
SU,STO
, Stop Condition Setup Time
t
9
1.3
s min
t
BUF
, Bus Free Time between a STOP and a START Condition
t
10
300
ns max
t
R
, Rise Time of SCL and SDA when Receiving
0
ns min
t
R
, Rise Time of SCL and SDA when Receiving (CMOS Compatible)
t
11
250
ns max
t
F
, Fall Time of SDA when Transmitting
0
ns min
t
F
, Fall Time of SDA when Receiving (CMOS Compatible)
300
ns max
t
F
, Fall Time of SCL and SDA when Receiving
20 + 0.1C
B
4
ns min
t
F
, Fall Time of SCL and SDA when Transmitting
C
B
400
pF max
Capacitive Load for Each Bus Line
NOTES
1
See Figure 1.
2
Guaranteed by design and characterization; not production tested.
3
A master device must provide a hold time of at least 300 ns for the SDA signal (referred to V
IH
min of the SCL signal) in order to bridge the undefined region of
SCL's falling edge.
4
C
B
is the total capacitance of one bus line in pF. t
R
and t
F
measured between 0.3 V
DD
and 0.7 V
DD
.
Specifications subject to change without notice.
SCL
SDA
START
CONDITION
t
9
t
3
t
4
t
6
t
2
t
5
t
7
t
8
t
1
t
4
t
11
t
10
REPEATED
START
CONDITION
STOP
CONDITION
Figure 1. 2-Wire Serial Interface Timing Diagram
REV. F
AD5305/AD5315/AD5325
5
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD5305/AD5315/AD5325 feature proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS
1, 2
(T
A
= 25
C, unless otherwise noted.)
V
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to +7 V
SCL, SDA to GND . . . . . . . . . . . . . . . . 0.3 V to V
DD
+ 0.3 V
A0 to GND . . . . . . . . . . . . . . . . . . . . . . 0.3 V to V
DD
+ 0.3 V
Reference Input Voltage to GND . . . . . 0.3 V to V
DD
+ 0.3 V
V
OUT
AD to GND . . . . . . . . . . . . . . . . 0.3 V to V
DD
+ 0.3 V
Operating Temperature Range
Industrial (A, B Version) . . . . . . . . . . . . . . 40
C to +105C
Storage Temperature Range . . . . . . . . . . . . . 65
C to +150C
Junction Temperature (T
J
max) . . . . . . . . . . . . . . . . . . . 150
C
MSOP
Power Dissipation . . . . . . . . . . . . . . . . . . . (T
J
max T
A
)/
JA
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 206
C/W
JC
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 44
C/W
Reflow Soldering
Peak Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
C
Time at Peak Temperature . . . . . . . . . . . . . 10 sec to 40 sec
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
2
Transient currents of up to 100 mA will not cause SCR latch-up.
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
Branding
AD5305ARM
40
C to +105C
10-Lead MSOP
RM-10
DEA
AD5305ARM-REEL7
40
C to +105C
10-Lead MSOP
RM-10
DEA
AD5315ARM
40
C to +105C
10-Lead MSOP
RM-10
DFA
AD5315ARM-REEL7
40
C to +105C
10-Lead MSOP
RM-10
DFA
AD5325ARM
40
C to +105C
10-Lead MSOP
RM-10
DGA
AD5325ARM-REEL7
40
C to +105C
10-Lead MSOP
RM-10
DGA
AD5305BRM
40
C to +105C
10-Lead MSOP
RM-10
DEB
AD5305BRM-REEL
40
C to +105C
10-Lead MSOP
RM-10
DEB
AD5305BRM-REEL7
40
C to +105C
10-Lead MSOP
RM-10
DEB
AD5315BRM
40
C to +105C
10-Lead MSOP
RM-10
DFB
AD5315BRM-REEL
40
C to +105C
10-Lead MSOP
RM-10
DFB
AD5315BRM-REEL7
40
C to +105C
10-Lead MSOP
RM-10
DFB
AD5325BRM
40
C to +105C
10-Lead MSOP
RM-10
DGB
AD5325BRM-REEL
40
C to +105C
10-Lead MSOP
RM-10
DGB
AD5325BRM-REEL7
40
C to +105C
10-Lead MSOP
RM-10
DGB
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