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Information furnished by Analog Devices is believed to be accurate and
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which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
AD5330/AD5331/AD5340/AD5341*
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
Analog Devices, Inc., 2000
2.5 V to 5.5 V, 115 A, Parallel Interface
Single Voltage-Output 8-/10-/12-Bit DACs
AD5330 FUNCTIONAL BLOCK DIAGRAM
(Other Diagrams Inside)
BUFFER
8-BIT
DAC
DAC
REGISTER
INPUT
REGISTER
INTER-
FACE
LOGIC
POWER-DOWN
LOGIC
BUF
GAIN
DB
7
DB
0
.
.
CS
WR
CLR
LDAC
V
REF
V
DD
V
OUT
PD
GND
AD5330
POWER-ON
RESET
RESET
FEATURES
AD5330: Single 8-Bit DAC in 20-Lead TSSOP
AD5331: Single 10-Bit DAC in 20-Lead TSSOP
AD5340: Single 12-Bit DAC in 24-Lead TSSOP
AD5341: Single 12-Bit DAC in 20-Lead TSSOP
Low Power Operation: 115 A @ 3 V, 140 A @ 5 V
Power-Down to 80 nA @ 3 V, 200 nA @ 5 V via
PD Pin
2.5 V to 5.5 V Power Supply
Double-Buffered Input Logic
Guaranteed Monotonic by Design Over All Codes
Buffered/Unbuffered Reference Input Options
Output Range: 0V
REF
or 02 V
REF
Power-On Reset to Zero Volts
Simultaneous Update of DAC Outputs via
LDAC Pin
Asynchronous
CLR Facility
Low Power Parallel Data Interface
On-Chip Rail-to-Rail Output Buffer Amplifiers
Temperature Range: 40 C to +105 C
APPLICATIONS
Portable Battery-Powered Instruments
Digital Gain and Offset Adjustment
Programmable Voltage and Current Sources
Programmable Attenuators
Industrial Process Control
GENERAL DESCRIPTION
The AD5330/AD5331/AD5340/AD5341 are single 8-, 10-, and
12-bit DACs. They operate from a 2.5 V to 5.5 V supply con-
suming just 115
A at 3 V, and feature a power-down mode that
further reduces the current to 80 nA. These devices incorporate
an on-chip output buffer that can drive the output to both
supply rails, while the AD5330, AD5340, and AD5341 allow a
choice of buffered or unbuffered reference input.
The AD5330/AD5331/AD5340/AD5341 have a parallel interface.
CS selects the device and data is loaded into the input registers
on the rising edge of
WR.
The GAIN pin allows the output range to be set at 0 V to V
REF
or 0 V to 2
V
REF
.
Input data to the DACs is double-buffered, allowing simultaneous
update of multiple DACs in a system using the
LDAC pin.
An asynchronous
CLR input is also provided, which resets the
contents of the Input Register and the DAC Register to all zeros.
These devices also incorporate a power-on reset circuit that ensures
that the DAC output powers on to 0 V and remains there until
valid data is written to the device.
The AD5330/AD5331/AD5340/AD5341 are available in Thin
Shrink Small Outline Packages (TSSOP).
*Protected by U.S. Patent Number 5,969,657; other patents pending.
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2
AD5330/AD5331/AD5340/AD5341SPECIFICATIONS
(V
DD
= 2.5 V to 5.5 V, V
REF
= 2 V. R
L
= 2 k
to GND; C
L
= 200 pF to GND; all specifications T
MIN
to T
MAX
unless otherwise noted.)
B Version
2
Parameter
1
Min
Typ
Max
Unit
Conditions/Comments
DC PERFORMANCE
3, 4
AD5330
Resolution
8
Bits
Relative Accuracy
0.15
1
LSB
Differential Nonlinearity
0.02
0.25
LSB
Guaranteed Monotonic By Design Over All Codes
AD5331
Resolution
10
Bits
Relative Accuracy
0.5
4
LSB
Differential Nonlinearity
0.05
0.5
LSB
Guaranteed Monotonic By Design Over All Codes
AD5340/AD5341
Resolution
12
Bits
Relative Accuracy
2
16
LSB
Differential Nonlinearity
0.2
1
LSB
Guaranteed Monotonic By Design Over All Codes
Offset Error
0.4
3
% of FSR
Gain Error
0.15
1
% of FSR
Lower Deadband
5
10
60
mV
Lower Deadband Exists Only if Offset Error Is Negative
Upper Deadband
10
60
mV
V
DD
= 5 V. Upper Deadband Exists Only if V
REF =
V
DD
Offset Error Drift
6
12
ppm of FSR/
C
Gain Error Drift
6
5
ppm of FSR/
C
DC Power Supply Rejection Ratio
6
60
dB
V
DD
=
10%
DAC REFERENCE INPUT
6
V
REF
Input Range
1
V
DD
V
Buffered Reference (AD5330, AD5340, and AD5341)
0.25
V
DD
V
Unbuffered Reference
V
REF
Input Impedance
>10
M
Buffered Reference (AD5330, AD5340, and AD5341)
180
k
Unbuffered Reference. Gain = 1, Input Impedance = R
DAC
90
k
Unbuffered Reference. Gain = 2, Input Impedance = R
DAC
Reference Feedthrough
90
dB
Frequency = 10 kHz
OUTPUT CHARACTERISTICS
6
Minimum Output Voltage
4,
7
0.001
V min
Rail-to-Rail Operation
Maximum Output Voltage
4, 7
V
DD
0.001
V max
DC Output Impedance
0.5
Short Circuit Current
25
mA
V
DD
= 5 V
15
mA
V
DD
= 3 V
Power-Up Time
2.5
s
Coming Out of Power-Down Mode. V
DD
= 5 V
5
s
Coming Out of Power-Down Mode. V
DD
= 3 V
LOGIC INPUTS
6
Input Current
1
A
V
IL
, Input Low Voltage
0.8
V
V
DD
= 5 V
10%
0.6
V
V
DD
= 3 V
10%
0.5
V
V
DD
= 2.5 V
V
IH
, Input High Voltage
2.4
V
V
DD
= 5 V
10%
2.1
V
V
DD
= 3 V
10%
2.0
V
V
DD
= 2.5 V
Pin Capacitance
3
pF
POWER REQUIREMENTS
V
DD
2.5
5.5
V
I
DD
(Normal Mode)
DACs active and excluding load currents. Unbuffered
V
DD
= 4.5 V to 5.5 V
140
250
A
Reference. V
IH
= V
DD
, V
IL
= GND.
V
DD
= 2.5 V to 3.6 V
115
200
A
I
DD
increases by 50
A at V
REF
> V
DD
100 mV.
In Buffered Mode extra current is (5 + V
REF
/R
DAC
)
A,
where R
DAC
is the resistance of the resistor string.
I
DD
(Power-Down Mode)
V
DD
= 4.5 V to 5.5 V
0.2
1
A
V
DD
= 2.5 V to 3.6 V
0.08
1
A
NOTES
1
See Terminology section.
2
Temperature range: B Version: 40
C to +105C; typical specifications are at 25C.
3
Linearity is tested using a reduced code range: AD5330 (Code 8 to 255); AD5331 (Code 28 to 1023); AD5340/AD5341 (Code 115 to 4095).
4
DC specifications tested with output unloaded.
5
This corresponds to x codes. x = Deadband voltage/LSB size.
6
Guaranteed by design and characterization, not production tested.
7
In order for the amplifier output to reach its minimum voltage, Offset Error must be negative. In order for the amplifier output to reach its maximum voltage, V
REF
= V
DD
and
"Offset plus Gain" Error must be positive.
Specifications subject to change without notice.
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3
AD5330/AD5331/AD5340/AD5341
AC CHARACTERISTICS
1
B Version
3
Parameter
2
Min
Typ
Max
Unit
Conditions/Comments
Output Voltage Settling Time
V
REF
= 2 V. See Figure 20
AD5330
6
8
s
1/4 Scale to 3/4 Scale Change (40 H to C0 H)
AD5331
7
9
s
1/4 Scale to 3/4 Scale Change (100 H to 300 H)
AD5340
8
10
s
1/4 Scale to 3/4 Scale Change (400 H to C00 H)
AD5341
8
10
s
1/4 Scale to 3/4 Scale Change (400 H to C00 H)
Slew Rate
0.7
V/
s
Major Code Transition Glitch Energy
6
nV-s
1 LSB Change Around Major Carry
Digital Feedthrough
0.5
nV-s
Multiplying Bandwidth
200
kHz
V
REF
= 2 V
0.1 V p-p. Unbuffered Mode
Total Harmonic Distortion
70
dB
V
REF
= 2.5 V
0.1 V p-p. Frequency = 10 kHz
NOTES
1
Guaranteed by design and characterization, not production tested.
2
See Terminology section.
3
Temperature range: B Version: 40
C to +105C; typical specifications are at 25C.
Specifications subject to change without notice.
TIMING CHARACTERISTICS
1, 2, 3
Parameter
Limit at T
MIN
, T
MAX
Unit
Condition/Comments
t
1
0
ns min
CS to WR Setup Time
t
2
0
ns min
CS to WR Hold Time
t
3
20
ns min
WR Pulsewidth
t
4
5
ns min
Data, GAIN, BUF, HBEN Setup Time
t
5
4.5
ns min
Data, GAIN, BUF, HBEN Hold Time
t
6
5
ns min
Synchronous Mode.
WR Falling to LDAC Falling.
t
7
5
ns min
Synchronous Mode.
LDAC Falling to WR Rising.
t
8
4.5
ns min
Synchronous Mode.
WR Rising to LDAC Rising.
t
9
5
ns min
Asynchronous Mode.
LDAC Rising to WR Rising.
t
10
4.5
ns min
Asynchronous Mode.
WR Rising to LDAC Falling.
t
11
20
ns min
LDAC Pulsewidth
t
12
20
ns min
CLR Pulsewidth
t
13
50
ns min
Time Between
WR Cycles
NOTES
1
Guaranteed by design and characterization, not production tested.
2
All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2.
3
See Figure 1.
CS
WR
DATA,
GAIN,
BUF,
HBEN
LDAC
1
LDAC
2
CLR
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
t
11
t
12
t
13
NOTES:
1
SYNCHRONOUS
LDAC UPDATE MODE
2
ASYNCHRONOUS
LDAC UPDATE MODE
Figure 1. Parallel Interface Timing Diagram
(V
DD
= 2.5 V to 5.5 V, All specifications T
MIN
to T
MAX
unless otherwise noted.)
(V
DD
= 2.5 V to 5.5 V. R
L
= 2 k
to GND; C
L
= 200 pF to GND; all specifications T
MIN
to T
MAX
unless otherwise noted.)
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AD5330/AD5331/AD5340/AD5341
4
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD5330/AD5331/AD5340/AD5341 features proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ABSOLUTE MAXIMUM RATINGS
*
(T
A
= 25
C unless otherwise noted)
V
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to +7 V
Digital Input Voltage to GND . . . . . . . 0.3 V to V
DD
+ 0.3 V
Digital Output Voltage to GND . . . . . 0.3 V to V
DD
+ 0.3 V
Reference Input Voltage to GND . . . . 0.3 V to V
DD
+ 0.3 V
V
OUT
to GND . . . . . . . . . . . . . . . . . . . 0.3 V to V
DD
+ 0.3 V
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . 40
C to +105C
Storage Temperature Range . . . . . . . . . . . . 65
C to +150C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150
C
TSSOP Package
Power Dissipation . . . . . . . . . . . . . . . (T
J
max T
A
)/
JA
mW
JA
Thermal Impedance (20-Lead TSSOP) . . . . . 143
C/W
JA
Thermal Impedance (24-Lead TSSOP) . . . . . 128
C/W
JA
Thermal Impedance (20-Lead TSSOP) . . . . . . 45
C/W
JC
Thermal Impedance (24-Lead TSSOP) . . . . . . 42
C/W
Reflow Soldering
Peak Temperature . . . . . . . . . . . . . . . . . . . . . 220 +5/0
C
Time at Peak Temperature . . . . . . . . . . . . 10 sec to 40 sec
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
ORDERING GUIDE
Package
Model
Temperature Range
Package Description
Option
AD5330BRU
40
C to +105C
TSSOP (Thin Shrink Small Outline Package)
RU-20
AD5331BRU
40
C to +105C
TSSOP (Thin Shrink Small Outline Package)
RU-20
AD5340BRU
40
C to +105C
TSSOP (Thin Shrink Small Outline Package)
RU-24
AD5341BRU
40
C to +105C
TSSOP (Thin Shrink Small Outline Package)
RU-20
REV. 0
AD5330/AD5331/AD5340/AD5341
5
AD5330 FUNCTIONAL BLOCK DIAGRAM
BUFFER
8-BIT
DAC
DAC
REGISTER
INPUT
REGISTER
INTER-
FACE
LOGIC
POWER-DOWN
LOGIC
BUF
GAIN
DB
7
DB
0
.
.
CS
WR
CLR
LDAC
V
REF
V
DD
V
OUT
PD
GND
AD5330
POWER-ON
RESET
RESET
AD5330 PIN FUNCTION DESCRIPTIONS
Pin
No.
Mnemonic
Function
1
BUF
Buffer Control Pin. This pin controls whether the reference input to the DAC is buffered or unbuffered.
2
NC
No Connect.
3
V
REF
Reference Input.
4
V
OUT
Output of DAC. Buffered output with rail-to-rail operation.
5
GND
Ground reference point for all circuitry on the part.
6
CS
Active Low Chip Select Input. This is used in conjunction with
WR to write data to the parallel interface.
7
WR
Active Low Write Input. This is used in conjunction with
CS to write data to the parallel interface.
8
GAIN
Gain Control Pin. This controls whether the output range from the DAC is 0V
REF
or 02 V
REF.
9
CLR
Asynchronous active low control input that clears all input registers and DAC registers to zero.
10
LDAC
Active low control input that updates the DAC registers with the contents of the input registers.
11
PD
Power-Down Pin. This active low control pin puts the DAC into power-down mode.
12
V
DD
Power Supply Input. These parts can operate from 2.5 V to 5.5 V and the supply should be decoupled
with a 10
F capacitor in parallel with a 0.1 F capacitor to GND.
1320
DB
0
DB
7
Eight Parallel Data Inputs. DB
7
is the MSB of these eight bits.
AD5330 PIN CONFIGURATION
TOP VIEW
(Not to Scale)
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
AD5330
LDAC
GAIN
WR
CS
GND
BUF
V
REF
V
OUT
PD
V
DD
DB
0
DB
1
DB
2
DB
3
DB
4
DB
5
DB
6
DB
7
8-BIT
CLR
NC = NO CONNECT
NC
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