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2.5 V to 5.5 V, Parallel Interface
Octal Voltage Output 8-/10-/12-Bit DACs
AD5346/AD5347/AD5348
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
2003 Analog Devices, Inc. All rights reserved.
FEATURES
AD5346: octal 8-bit DAC
AD5347: octal 10-bit DAC
AD5348: octal 12-bit DAC
Low power operation: 1.4 mA (max) @ 3.6 V
Power-down to 120 nA @ 3 V, 400 nA @ 5 V
Guaranteed monotonic by design over all codes
Rail-to-rail output range: 0 V to V
REF
or 0 V to 2 V
REF
Power-on reset to 0 V
Simultaneous update of DAC outputs via LDAC pin
Asynchronous CLR
facility
Readback
Buffered/unbuffered reference inputs
20 ns WR
time
38-lead TSSOP/6 mm 6 mm 40-lead LFCSP packaging
Temperature range: 40C to +105C
APPLICATIONS
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Optical networking
Automatic test equipment
Mobile communications
Programmable attenuators
Industrial process control
GENERAL DESCRIPTION
The AD5346/AD5347/AD5348
1
are octal 8-, 10-, and 12-bit
DACs, operating from a 2.5 V to 5.5 V supply. These devices
incorporate an on-chip output buffer that can drive the output
to both supply rails, and also allow a choice of buffered or
unbuffered reference input.
The AD5346/AD5347/AD5348 have a parallel interface. CS
selects the device and data is loaded into the input registers on
the rising edge of WR. A readback feature allows the internal
DAC registers to be read back through the digital port.
The GAIN pin on these devices allows the output range to be
set at 0 V to V
REF
or 0 V to 2 V
REF
.
Input data to the DACs is double-buffered, allowing simultane-
ous update of multiple DACs in a system using the LDAC pin.
An asynchronous CLR input is also provided, which resets the
contents of the input register and the DAC register to all zeros.
These devices also incorporate a power-on reset circuit that
ensures that the DAC output powers on to 0 V and remains
there until valid data is written to the device.
All three parts are pin compatible, which allows users to select
the amount of resolution appropriate for their application
without redesigning their circuit board.
FUNCTIONAL BLOCK DIAGRAM
INPUT
REGISTER
DAC
REGISTER
STRING
DAC C
STRING
DAC A
STRING
DAC B
STRING
DAC D
STRING
DAC E
STRING
DAC F
STRING
DAC G
STRING
DAC H
DGND
V
OUT
B
V
OUT
C
V
OUT
D
V
OUT
E
V
OUT
G
V
OUT
H
V
OUT
F
V
DD
POWER-ON
RESET
V
OUT
A
V
REF
EF
V
REF
AB
PD
INTER-
FACE
LOGIC
GAIN
DB11
DB0
CS
WR
A0
A1
CLR
LDAC
.
.
.
BUF
A2
RD
V
REF
GH
V
REF
CD
AGND
BUFFER
BUFFER
BUFFER
BUFFER
BUFFER
BUFFER
BUFFER
BUFFER
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
AD5348
POWER-DOWN
LOGIC
03331-
0-
001
Figure 1.
1
Protected by U.S. Patent No. 5,969,657; other patents pending.
AD5346/AD5347/AD5348
Rev. 0 | Page 2 of 24
TABLE OF CONTENTS
Specifications..................................................................................... 3
AC Characteristics............................................................................ 4
Timing Characteristics..................................................................... 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
AD5346 Pin Configurations and Function Descriptions ........... 7
AD5347 Pin Configurations and Function Descriptions ........... 8
AD5348 Pin Configurations and Function Descriptions ........... 9
Terminology .................................................................................... 10
Typical Performance Characteristics ........................................... 12
Functional Description .................................................................. 16
Digital-to-Analog Section ......................................................... 16
Resistor String ............................................................................. 16
DAC Reference Input................................................................. 16
Output Amplifier ........................................................................ 16
Parallel Interface ......................................................................... 17
Power-On Reset.......................................................................... 17
Power-Down Mode .................................................................... 17
Suggested Data Bus Formats..................................................... 18
Applications Information .............................................................. 19
Typical Application Circuits ..................................................... 19
Driving V
DD
from the Reference Voltage................................. 19
Bipolar Operation Using the AD5346/AD5347/AD5348..... 19
Decoding Multiple AD5346/AD5347/AD5348s.................... 20
AD5346/AD5347/AD5348 as Digitally Programmable
Window Detectors ...................................................................... 20
Programmable Current Source ................................................ 20
Coarse and Fine Adjustment Using the
AD5346/AD5347/AD5348 ....................................................... 21
Power Supply Bypassing and Grounding................................ 21
Outline Dimensions ....................................................................... 23
Ordering Guides......................................................................... 24
REVISION HISTORY
Revision 0: Initial Version
AD5346/AD5347/AD5348
Rev. 0 | Page 3 of 24
SPECIFICATIONS
Table 1. V
DD
= 2.5 V to 5.5 V; V
REF
= 2 V; R
L
= 2 k to GND; C
L
= 200 pF to GND; all specifications T
MIN
to T
MAX
,
unless otherwise noted
B
Version
1
Parameter
2
Min
Typ
Max
Unit
Conditions/Comments
DC PERFORMANCE
3,4
AD5346
Resolution
8
Bits
Relative Accuracy
0.15
1
LSB
Differential Nonlinearity
0.02
0.25
LSB
Guaranteed monotonic by design over all codes
AD5347
Resolution
10
Bits
Relative Accuracy
0.5
4
LSB
Differential Nonlinearity
0.05
0.5
LSB
Guaranteed monotonic by design over all codes
AD5348
Resolution
12
Bits
Relative Accuracy
2
16
LSB
Differential Nonlinearity
0.2
1
LSB
Guaranteed monotonic by design over all codes
Offset Error
0.4
3
% of FSR
Gain Error
0.1
1
% of FSR
Lower Deadband
5
10
60
mV
Lower deadband exists only if offset error is negative
Upper Deadband
5
10
60
mV
V
DD
= 5 V; upper deadband exists only if V
REF
= V
DD
Offset Error Drift
6
12
ppm of FSR/C
Gain Error Drift
6
5
ppm of FSR/C
DC Power Supply Rejection
Ratio
6
60
dB
V
DD
= 10%
DC Crosstalk
6
200
V
R
L
= 2 k to GND, 2 k to V
DD
; C
L
= 200 pF to GND;
Gain = +1
DAC REFERENCE INPUT
6
V
REF
Input Range
1
V
DD
V
Buffered reference mode
V
REF
Input Range
0.25
V
DD
V
Unbuffered reference mode
V
REF
Input Impedance
>10
M
Buffered reference mode and power-down mode
90
k
Gain = +1; input impedance = R
DAC
45
k
Gain = +2; input impedance = R
DAC
Reference Feedthrough
90
dB
Frequency = 10 kHz
Channel-to-Channel Isolation
75
dB
Frequency = 10 kHz
OUTPUT CHARACTERISTICS
6
Minimum Output Voltage
4, 7
0.001
V min
Rail-to-rail operation
Maximum Output Voltage
4, 7
V
DD
0.001
V
max
DC Output Impedance
0.5
Short Circuit Current
25
mA
V
DD
= 5 V
16
mA
V
DD
= 3 V
Power-Up Time
2.5
s
Coming out of power-down mode; V
DD
= 5 V
5
s
Coming out of power-down mode; V
DD
= 3 V
LOGIC INPUTS
6
Input Current
1
A
V
IL
, Input Low Voltage
0.8
V
V
DD
= 5 V 10%
0.7
V
V
DD
= 3 V 10%
0.6
V
V
DD
= 2.5 V
V
IH
, Input High Voltage
1.7
V
V
DD
= 2.5 V to 5.5 V
Pin Capacitance
5
pF
AD5346/AD5347/AD5348
Rev. 0 | Page 4 of 24
B
Version
1
Parameter
2
Min
Typ
Max
Unit
Conditions/Comments
LOGIC OUTPUTS
6
V
DD
= 4.5 V to 5.5 V
Output Low Voltage, V
OL
0.4
V
I
SINK
= 200 A
Output High Voltage, V
OH
V
DD
1
V
I
SOURCE
= 200 A
V
DD
= 2.5 V to 3.6 V
Output Low Voltage, V
OL
0.4
V
I
SINK
= 200 A
Output High Voltage, V
OH
V
DD
0.5
V
I
SOURCE
= 200 A
POWER REQUIREMENTS
V
DD
2.5
5.5
V
I
DD
(Normal Mode)
V
IH
= V
DD
, V
IL
= GND
V
DD
= 4.5 V to 5.5 V
1
1.65
mA
All DACs in unbuffered mode. In buffered mode,
V
DD
= 2.5 V to 3.6 V
0.8
1.4
mA
extra current is typically x A per DAC, where x = 5 A +
V
REF
/R
DAC
I
DD
(Power-Down Mode)
V
IH
= V
DD
, V
IL
= GND
V
DD
= 4.5 V to 5.5 V
0.4
1
A
V
DD
= 2.5 V to 3.6 V
0.12
1
A
See footnotes after the AC Characteristics table.
AC CHARACTERISTICS
6
Table 2. V
DD
= 2.5 V to 5.5 V; R
L
= 2 k to GND; C
L
= 200 pF to GND; all specifications T
MIN
to T
MAX
, unless otherwise noted
B
Version
1
Parameter
2
Min Typ
Max
Unit
Conditions/Comments
Output Voltage Settling Time
V
REF
= 2 V
AD5346
6
8
s
1/4 scale to 3/4 scale change (40 H to C0 H)
AD5347
7
9
s
1/4 scale to 3/4 scale change (100 H to 300 H)
AD5348
8
10
s
1/4 scale to 3/4 scale change (400 H to C00 H)
Slew Rate
0.7
V/s
Major Code Transition Glitch
Energy
8
nV-s
1 LSB change around major carry
Digital Feedthrough
0.5
nV-s
Digital Crosstalk
1
nV-s
Analog Crosstalk
1
nV-s
DAC-to-DAC Crosstalk
3.5
nV-s
Multiplying Bandwidth
200
kHz
V
REF
= 2 V 0.1 V p-p; unbuffered mode
Total Harmonic Distortion
70
dB
V
REF
= 2. V 0.1 V p-p; frequency = 10 kHz; unbuffered mode
1
Temperature range: B Version: 40C to +105C; typical specifications are at 25C.
2
See Terminology section.
3
Linearity is tested using a reduced code range: AD5346 (Code 8 to 255); AD5347 (Code 28 to 1023); AD5348 (Code 115 to 4095).
4
DC specifications tested with outputs unloaded.
5
This corresponds to x codes. x = deadband voltage/LSB size.
6
Guaranteed by design and characterization, not production tested.
7
For the amplifier output to reach its minimum voltage, offset error must be negative. For the amplifier output to reach its maximum voltage, V
REF
= V
DD
and
the offset plus gain error must be positive.
I
OH
I
OL
TO OUTPUT
PIN
V
OH
(min) + V
OL
(max)
2
C
L
50pF
200
A
200
A
03331-0-002
Figure 2. Load Circuit for Digital Output Timing Specifications
AD5346/AD5347/AD5348
Rev. 0 | Page 5 of 24
TIMING CHARACTERISTICS
1, 2, 3
Table 3. V
DD
= 2.5 V to 5.5 V; all specifications T
MIN
to T
MAX
, unless otherwise noted
Parameter
Limit at T
MIN
, T
MAX
Unit
Condition/Comments
Data Write Mode (Figure 3)
t
1
0
ns min
CS to WR setup time
t
2
0
ns min
CS to WR hold time
t
3
20
ns min
WR pulse width
t
4
5
ns min
Data, GAIN, BUF setup time
t
5
4.5
ns min
Data, GAIN, BUF hold time
t
6
5
ns min
Synchronous mode. WR falling to LDAC falling.
t
7
5
ns min
Synchronous mode. LDAC falling to WR rising.
t
8
4.5
ns min
Synchronous mode. WR rising to LDAC rising.
t
9
5
ns min
Asynchronous mode. LDAC rising to WR rising.
t
10
4.5
ns min
Asynchronous mode. WR rising to LDAC falling.
t
11
20
ns min
LDAC pulse width
t
12
10
ns min
CLR pulse width
t
13
20
ns min
Time between WR cycles
t
14
20
ns min
A0, A1, A2 setup time
t
15
0
ns min
A0, A1, A2 hold time
Data Readback Mode (Figure 4)
t
16
0
ns min
A0, A1, A2 to CS setup time
t
17
0
ns min
A0, A1, A2 to CS hold time
t
18
0
ns min
CS to falling edge of RD
t
19
20
ns min
RD pulse width; V
DD
= 3.6 V to 5.5 V
30
ns min
RD pulse width; V
DD
= 2.5 V to 3.6 V
t
20
0
ns min
CS to RD hold time
t
21
22
ns max
Data access time after falling edge of RD; V
DD
= 3.6 V to 5.5 V
30
ns max
Data access time after falling edge of RD V
DD
= 2.5 V to 3.6 V
t
22
4
ns min
Bus relinquish time after rising edge of RD
30
ns max
t
23
22
ns max
CS falling edge to data; V
DD
= 3.6 V to 5.5 V
30
ns max
CS falling edge to data; V
DD
= 2.5 V to 3.6 V
t
24
30 ns
min
Time between RD cycles
t
25
30 ns
min
Time from RD to WR
t
26
30 ns
min
Time from WR to RD, V
DD
= 3.6 V to 5.5 V
50
ns
min
Time from WR to RD, V
DD
= 2.5 V to 3.6 V
1
Guaranteed by design and characterization, not production tested.
2
All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2.
3
See Figure 2.
CS
WR
DATA,
GAIN, BUF
LDAC
1
LDAC
2
CLR
NOTES
1. SYNCHRONOUS LDAC UPDATE MODE
2. ASYNCHRONOUS LDAC UPDATE MODE
A0A2
t
1
t
2
t
3
t
4
t
7
t
9
t
10
t
11
t
12
t
5
t
15
t
8
t
14
t
6
t
13
03331-0-003
CS
A0A2
RD
WR
DATA
t
16
t
18
t
25
t
20
t
22
t
21
t
17
t
26
t
24
t
19
t
23
03331-0-004
Figure 3. Parallel Interface Write Timing Diagram
Figure 4. Parallel Interface Read Timing Diagram
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