AD5372/AD5373 32-Channel, 16/14, Serial Input, Voltage-Output DACs Preliminary Data Sheet (Rev. PrC)
32-Channel, 16/14, Serial Input,
Voltage-Output DACs
Preliminary Technical Data
AD5372/AD5373
Rev. Pr C
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
2005 Analog Devices, Inc. All rights reserved.
FEATURES
32-channel DAC in 56-LFCSP and 64-LQFP
AD5372 Guaranteed monotonic to 16 bits
AD5373 Guaranteed monotonic to 14 bits
Maximum output voltage span of 4 V
REF
(20 V)
Nominal output voltage range of -4 V to +8 V
Multiple, independent output spans available
System calibration function allowing user-programmable
offset and gain
Channel grouping and addressing features
Thermal Monitoring Function
DSP/microcontroller-compatible serial interface
2.5 V to 5.5 V JEDEC-compliant digital levels
Power-on reset
Digital reset (RESET)
Clear function to user-defined SIGGND (CLR pin)
Simultaneous update of DAC outputs (LDAC pin)
APPLICATIONS
Level setting in automatic test equipment (ATE)
Variable optical attenuators (VOA)
Optical switches
Industrial control systems
Instrumentation
FUNCTIONAL BLOCK DIAGRAM
CONTROL
REGISTER
STATE
MACHINE
n
POWER-ON
RESET
SYNC
SDI
SCLK
SDO
BUSY
RESET
CLR
AD5372/
AD5373
SERIAL
INTERFACE
n
VOUT8
VOUT9
VOUT10
VOUT11
VOUT12
VOUT13
VOUT14
VOUT15
SIGGND1
DAC 0
REGISTER
n
n
8
8
TO
MUX 2's
A/B SELECT
REGISTER
MUX
2
X2A REGISTER
X2B REGISTER
OFS1
REGISTER
14
n
DAC 0
OUTPUT BUFFER
AND POWER
DOWN CONTROL
OUTPUT BUFFER
AND POWER
DOWN CONTROL
OFFSET
DAC 1
BUFFER
DAC 7
REGISTER
n
n
MUX
2
X2A REGISTER
X2B REGISTER
DAC 7
GROUP 1
VREF0
SIGGND0
SIGGND2
SIGGND3
VOUT0
VOUT1
VOUT2
VOUT3
VOUT4
VOUT5
VOUT6
VOUT7
VOUT16
TO
VOUT31
GROUP 2 TO GROUP 3
ARE IDENTICAL TO GROUP 1
LDAC
DV
CC
V
DD
V
SS
AGND DNGD
DAC 0
REGISTER
n
n
8
8
TO
MUX 2's
A/B SELECT
REGISTER
MUX
2
X2A REGISTER
X2B REGISTER
OFS0
REGISTER
14
n
DAC 0
OUTPUT BUFFER
AND POWER
DOWN CONTROL
OUTPUT BUFFER
AND POWER
DOWN CONTROL
OFFSET
DAC 0
BUFFER
GROUP 0
DAC 7
REGISTER
n
n
MUX
2
X2A REGISTER
X2B REGISTER
DAC 7
BUFFER
VREF1
5372-0001B
VREF1 SUPPLIES
GROUP 1 TO 3
n = 16 FOR AD5372
n = 14 FOR AD5373
n
n
n
n
n
n
n
A/B
MUX
X1 REGISTER
M REGISTER
C REGISTER
n
n
n
n
n
n
n
A/B
MUX
X1 REGISTER
M REGISTER
C REGISTER
n
n
n
n
n
n
n
A/B
MUX
X1 REGISTER
M REGISTER
C REGISTER
n
n
n
n
n
n
n
A/B
MUX
X1 REGISTER
M REGISTER
C REGISTER
Figure 1.
AD5372/AD5373--Protected by U.S. Patent No. 5,969,657; other patents pending
AD5372/AD5373
Preliminary Technical Data
Rev. Pr C| Page 2 of 24
TABLE OF CONTENTS
Specifications......................................................................................4
AC Characteristics.........................................................................5
Timing Characteristics .................................................................6
Absolute Maximum Ratings.............................................................8
ESD Caution...................................................................................8
Terminology .................................................................................... 11
Functional Description .................................................................. 12
DAC Architecture--General..................................................... 12
Channel Groups.......................................................................... 12
A/ B Reigsters And Gain/Offset Adjustment.......................... 13
Load DAC.................................................................................... 13
Offset DACs ................................................................................ 13
Output Amplifier........................................................................ 13
Transfer Function ....................................................................... 14
Reference Selection .................................................................... 14
Calibration................................................................................... 15
Reset Function ............................................................................ 15
Clear Function ............................................................................ 15
Power-Down Mode .................................................................... 16
Thermal Monitor Function....................................................... 16
Toggle Mode................................................................................ 16
Serial Interface ................................................................................ 17
SPI Write Mode........................................................................... 17
SPI Readback Mode ................................................................... 18
Register Update Rates ................................................................ 18
Channel Addressing And Special Modes ................................ 18
Special Function Mode .............................................................. 19
Power Supply Decoupling ......................................................... 21
Power Supply Sequencing ......................................................... 21
Interfacing Examples...................................................................... 22
Outline Dimensions ....................................................................... 23
Ordering Guide........................................................................... 23
REVISION HISTORY
Pr B1
Modified SPI timing diagrams
Added Reference Selection and Calibration text
Pr. B2
Added Reset Function text
Pr. B3
Added Power Down Mode text
Pr. B4
Added Terminology and Power Supply Sequencing sections
Preliminary Technical Data
AD5372/AD5373
Rev. Pr C | Page 3 of 24
General Description
The AD5372 and AD5373 contain 32, 16-bit or 14-bit DACs in
a single, 56-lead, LFCSP or 64-lead LQFP package. The
AD5372/AD5373 provides buffered voltage outputs with a span
4 times the reference voltage. The gain and offset of each DAC
can be independently trimmed to remove errors. For even
greater flexibility, the device is divided into 4 groups of 8 DACs.
Two offset DACs allow the output range of the groups to be
altered.
The ADAD5372/AD5373 offers guaranteed operation over a
wide supply range with V
SS
from -4.5 V to -16.5 V and V
DD
from+8 V to +16.5 V. The output amplifier headroom
requirement is 1.4 V operating with a load current of 1 mA.
The ADAD5372/AD5373 has a high-speed serial interface,
which is compatible with SPI, QSPITM, MICROWIRETM, and DSP
interface standards and can handle clock speeds of up to 50
MHz.
The DAC outputs are updated on reception of new data into the
DAC registers. All the outputs can be updated simultaneously
by taking the LDAC input low. Each channel has a program-
mable gain and an offset adjust register.
Each DAC output is gained and buffered on-chip with respect
to an external SIGGND input. The DAC outputs can also be
switched to SIGGND via the CLR pin.
Table 1. High Channel Count Bipolar DACs
Model Resolution
Nominal
Output
Span
Output
Channels
Linearity Error
(LSB)
Package Description
Package Option
AD5360BCPZ
16 Bits
4
V
REF
(20 V)
16
4
56-Lead LFCSP
CP-56
AD5360BSTZ
16 Bits
4
V
REF
(20 V)
16
4
52-Lead LQFP
ST-52
AD5361BCPZ
14 Bits
4
V
REF
(20 V)
16
1
56-Lead LFCSP
CP-56
AD5361BSTZ
14 Bits
4
V
REF
(20 V)
16
1
52-Lead LQFP
ST-52
AD5362BCPZ 16
Bits
4
V
REF
(20 V)
8
4
56-Lead LFCSP
CP-56
AD5362BSTZ 16
Bits
4
V
REF
(20 V)
8
4
52-Lead LQFP
ST-52
AD5363BCPZ
14 Bits
4
V
REF
(20 V)
8
1
56-Lead LFCSP
CP-56
AD5363BSTZ
14 Bits
4
V
REF
(20 V)
8
1
52-Lead LQFP
ST-52
AD5370BCPZ
16 Bits
4
V
REF
(12 V)
40
4
64-Lead LFCSP
CP-64
AD5370BSTZ
16 Bits
4
V
REF
(12 V)
40
4
64-Lead LQFP
ST-64
AD5371BCPZ
14 Bits
4
V
REF
(12 V)
40
1
100-Ball CSPBGA
BC-100-2
AD5371BSTZ
14 Bits
4
V
REF
(12 V)
40
1
80-Lead LQFP
ST-80
AD5372BCPZ
16 Bits
4
V
REF
(12 V)
32
4
56-Lead LFCSP
CP-56
AD5372BSTZ
16 Bits
4
V
REF
(12 V)
32
4
64-Lead LQFP
ST-64
AD5373BCPZ
14 Bits
4
V
REF
(12 V)
32
1
56-Lead LFCSP
CP-56
AD5373BSTZ
14 Bits
4
V
REF
(12 V)
32
1
64-Lead LQFP
ST-64
AD5372/AD5373
Preliminary Technical Data
Rev. Pr C| Page 4 of 24
SPECIFICATIONS
DV
CC
= 2.3 V to 5.5 V; V
DD
= 8 V to 16.5 V; V
SS
= -4.5 V to -16.5 V; V
REF
= 3 V; AGND = DGND = SIGGND = 0 V; R
L
= Open Circuit;
Gain (m), Offset(c) and DAC Offset registers at default value; all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 2. Performance Specifications
Parameter AD5372
1
B Version
AD5373
1
B Version
Unit Test
Conditions/Comments
2
ACCURACY
Resolution 16
14
Bits
Relative Accuracy
4
1
LSB max
Differential Nonlinearity
1
1
LSB max
Guaranteed monotonic by design over temperature.
Zero-Scale Error
12
12
mV max
Before Calibration
Full-Scale Error
20
20
mV max
Before Calibration
Gain Error
10
10
mV max
Before Calibration
Zero-Scale Error
2
100
100
V max
After Calibration
Full-Scale Error
2
100
100
V max
After Calibration
Gain Error
2
100
100
V max
After Calibration
VOUT Temperature Coefficient
5
5
ppm FSR/C
typ
Includes linearity, offset, and gain drift.
DC Crosstalk
2
0.5
0.5
mV max
Typically 100 V.
REFERENCE INPUTS (VREF1, VREF2)
2
V
REF
DC Input Impedance
1
1
M min
Typically 100 M.
V
REF
Input Current
10
10
A max
Per input. Typically 30 nA.
V
REF
Range
3/5
3/5
V min/max
2% for specified operation.
SIGGND INPUT (SIGGND0 TO SIGGND4)
2
DC Input Impedance
55
55
k min
Typically 60 k.
Input Range
0.5
0.5
V min/max
OUTPUT CHARACTERISTICS
2
Output Voltage Range
V
SS
+ 1.4
V
SS
+ 1.4
V min
I
LOAD
= 1 mA.
V
DD
- 1.4
V
DD
- `.4
V max
I
LOAD
= 1 mA.
Short Circuit Current
5
5
mA max
Load Current
1
1
mA max
Capacitive Load
2200
2200
pF max
DC Output Impedance
1
1
max
DIGITAL INPUTS
JEDEC compliant.
Input High Voltage
1.7
1.7
V min
IOV
CC
= 2.5 V to 3.6 V.
2.0
2.0
V
min
IOV
CC
= 3.6 V to 5.5 V.
Input Low Voltage
0.8
0.8
V max
IOV
CC
= 2.5 V to 5.5 V.
Input Current (with pull-up/pull-
down)
8
8
A max
CLR and RESET pin only.
Input Current (no pull-up/pull-down)
1
1
A max
All other digital input pins.
Input Capacitance
2
10
10
pF
max
DIGITAL OUTPUTS (SDO)
Output Low Voltage
0.5
0.5
V max
Sinking 200 A.
Output High Voltage (SDO)
DV
CC
- 0.5
DV
CC
- 0.5
V min
Sourcing 200 A.
High Impedance Leakage Current
-5
-5
A max
SDO only.
High Impedance Output Capacitance
2
10
10
pF
typ
Preliminary Technical Data
AD5372/AD5373
Rev. Pr C | Page 5 of 24
Parameter AD5372
1
B Version
AD5373
1
B Version
Unit Test
Conditions/Comments
2
POWER REQUIREMENTS
DV
CC
2.3/5.5
2.3/5.5
V
min/max
V
DD
8/16.5
8/16.5
V
min/max
V
SS
-4.5/-16.5
-4.5/-16.5
V
min/max
Power Supply Sensitivity
2
Full Scale/ V
DD
-75
-75
dB
typ
Full Scale/ V
SS
-75
-75
dB
typ
Full Scale/ V
CC
-90
-90
dB
typ
DI
CC
2
2
mA
max
V
CC
= 5.5 V, V
IH
= V
CC
, V
IL
= GND.
I
DD
14
14
mA max
Outputs unloaded.
I
SS
14
14
mA max
Outputs unloaded.
Power Dissipation
Power Dissipation Unloaded (P)
350
350
mW
Junction Temperature
3
130
130
C
max
T
J
= T
A
+ P
TOTAL
J
.
1
Temperature range for B Version: -40C to +85C. Typical specifications are at 25C.
2
Guaranteed by design and characterization, not production tested.
3
Where
J
represents the package thermal impedance.
AC CHARACTERISTICS
DV
CC
= 2.5 V; V
DD
= 15 V; V
SS
= -15 V; V
REF
= 3 V; AGND = DGND = SIGGND = 0 V; C
L
= 200pF; R
L
= 10 k;
Gain (m), Offset(c) and DAC Offset registers at default value; all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 3. AC Characteristics
Parameter AD5372/
AD5373
Unit Test
Conditions/Comments
DYNAMIC PERFORMANCE
1
Output Voltage Settling Time
20
s typ
Full-scale change
30
s max
DAC latch contents alternately loaded with all 0s and all 1s.
Slew Rate
1
V/s typ
Digital-to-Analog Glitch Energy
20
nV-s typ
Glitch Impulse Peak Amplitude
10
mV max
Channel-to-Channel Isolation
100
dB typ
V
REF
(+) = 2 V p-p, 1 kHz.
DAC-to-DAC Crosstalk
40
nV-s typ
Between DACs in the same group.
10
nV-s typ
Between DACs from different groups.
Digital Crosstalk
0.1
nV-s typ
Digital Feedthrough
1
nV-s typ
Effect of input bus activity on DAC output under test.
Output Noise Spectral Density @ 10 kHz
250
nV/(Hz)
1/2
typ
V
REF
= 0 V.
1
Guaranteed by design and characterization. Not production tested
AD5372/AD5373
Preliminary Technical Data
Rev. Pr C| Page 6 of 24
TIMING CHARACTERISTICS
DV
CC
= 2.3 V to 5.5 V; V
DD
= 8 V to 16.5 V; V
SS
= -4.5 V to -16.5 V; V
REF
= 3 V; AGND = DGND = SIGGND = 0 V;
R
L
= Open Circuit; Gain (m), Offset(c) and DAC Offset registers at default value; all specifications T
MIN
to T
MAX
, unless otherwise noted.
SPI INTERFACE (Figure 4 and Figure 5)
Parameter
1, 2, 3
Limit at T
MIN
, T
MAX
Unit
Description
t
1
20
ns min
SCLK Cycle Time.
t
2
8
ns min
SCLK High Time.
t
3
8
ns min
SCLK Low Time.
t
4
10
ns min
SYNC Falling Edge to SCLK Falling Edge Setup Time.
t
5
15
ns min
Minimum SYNC High Time.
t
6
5
ns min
24th SCLK Falling Edge to SYNC Rising Edge.
t
7
5
ns min
Data Setup Time.
t
8
4.5
ns min
Data Hold Time.
t
9
3
30
ns max
SYNC Rising Edge to BUSY Falling Edge.
t
10
TBD
ns max
BUSY Pulse Width Low (Single-Channel Update.) See Table 7.
t
11
480
ns max
Single-Channel Update Cycle Time
t
12
20
ns min
24th SCLK Falling Edge to LDAC Falling Edge.
t
13
20
ns min
LDAC Pulse Width Low.
t
14
150
ns typ
BUSY Rising Edge to DAC Output Response Time.
t
15
0
ns min
BUSY Rising Edge to LDAC Falling Edge.
t
16
100
ns min
LDAC Falling Edge to DAC Output Response Time.
t
17
20/30
s typ/max
DAC Output Settling Time.
t
18
350
ns max
CLR/RESET Pulse Activation Time.
t
19
10
ns
min
RESET Pulse Width Low.
t
20
120 s
max
RESET Time Indicated by BUSY
Low.
t
21
250
ns
min
Minimum SYNC High Time in Readback Mode.
t
22
5
25
ns max
SCLK Rising Edge to SDO Valid.
1
Guaranteed by design and characterization, not production tested.
2
All input signals are specified with t
r
= t
f
= 2 ns (10% to 90% of V
CC
) and timed from a voltage level of 1.2 V.
3
See Figure 4 and Figure 5.
4
This is measured with the load circuit of Figure 2.
5
This is measured with the load circuit of Figure 3.
TO
OUTPUT
PIN
V
CC
R
L
2.2k
C
L
50pF
V
OL
200A
200A
50pF
C
L
I
OL
I
OL
V
OH
(min) - V
OL
(max)
2
TO
OUTPUT
PIN
Figure 2. Load Circuit for BUSY Timing Diagram
Figure 3. Load Circuit for SDO Timing Diagram
Preliminary Technical Data
AD5372/AD5373
Rev. Pr C | Page 7 of 24
SCLK
SYNC
SDI
BUSY
LDAC
1
VOUT
1
LDAC
2
VOUT
2
VOUT
RESET
VOUT
CLR
1
2
t
1
t
3
t
2
24
t
5
t
4
t
6
t
7
t
8
DB23
DB0
24
t
9
t
10
t
12
t
13
t
14
t
17
t
15
t
13
t
16
t
17
t
18
t
19
t
18
t
20
1
LDAC ACTIVE DURING BUSY
2
LDAC ACTIVE AFTER BUSY
BUSY
5371-0004B
1
t
11
Figure 4.
SPI Write Timing
5371-0005C
SCLK
SYNC
SDI
SDO
24
48
DB23
DB0
DB23
DB23
DB0
DB0
INPUT WORD SPECIFIES
REGISTER TO BE READ
UNDEFINED
NOP CONDITION
SELECTED REGISTER DATA
CLOCKED OUT
t
21
t
22
DB0
LSB FROM PREVIOUS READ
Figure 5.
SPI Read Timing
AD5372/AD5373
Preliminary Technical Data
Rev. Pr C| Page 8 of 24
ABSOLUTE MAXIMUM RATINGS
T
A
= 25C, unless otherwise noted.
Transient currents of up to 100 mA do not cause SCR latch-up.
Table 4. Absolute Maximum Ratings
Parameter Rating
V
DD
to AGND
-0.3 V to +17 V
V
SS
to AGND
-17 V to +0.3 V
DV
CC
to DGND
-0.3 V to +7 V
Digital Inputs to DGND
-0.3 V to V
CC
+ 0.3 V
Digital Outputs to DGND
-0.3 V to V
CC
+ 0.3 V
V
REF
1, V
REF
2 to AGND
-0.3 V to +7 V
VOUT0VOUT39 to AGND
V
SS
- 0.3 V to V
DD
+ 0.3 V
SIGGND to AGND
V
SS
- 0.3 V to V
DD
+ 0.3 V
AGND to DGND
-0.3 V to +0.3 V
Operating Temperature Range (T
A
)
Industrial (B Version)
-40C to +85C
Storage Temperature Range
-65C to +150C
Junction Temperature (T
J
max)
130C
JA
Thermal Impedance
56-LFCSP 24C/w
64-LQFP 45.5C/w
Reflow Soldering
Peak Temperature
230C
Time at Peak Temperature
10 s to 40 s
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only, and functional operation of the device at these or
any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may
affect device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Preliminary Technical Data
AD5372/AD5373
Rev. Pr C | Page 9 of 24
D
V
C
C
D
G
N
D
V
O
U
T
7
V
O
U
T
6
V
O
U
T
1
5
V
O
U
T
1
6
V
O
U
T
1
7
V
O
U
T
1
8
NC
NC
NC
VDD
VOUT5
VOUT4
SIGGND0
VOUT3
VOUT2
VOUT1
VOUT0
VREF0
VOUT23
VOUT22
VOUT21
VOUT20
39
38
37
41
40
VSS
VDD
SIGGND2
VOUT19
36
35
34
33
42
43
44
45
46
47
48
17 18 19 20 21 22 23 24
V
S
S
V
R
E
F
1
N
C
N
C
V
O
U
T
8
V
O
U
T
9
V
O
U
T
1
0
V
O
U
T
1
1
S
I
G
G
N
D
1
V
O
U
T
1
2
V
O
U
T
1
3
V
O
U
T
1
4
1
2
3
4
5
6
7
8
9
10
11
12
64 63 62 61 60 59 58
C
L
R
L
D
A
C
V
O
U
T
2
6
V
O
U
T
2
5
V
O
U
T
2
4
A
G
N
D
D
G
N
D
D
V
C
C
S
D
O
D
I
N
S
C
L
K
S
Y
N
C
PIN 1
IDENTIFIER
AD5372
AD5373
TOP VIEW
(Not to Scale)
RESET
BUSY
VOUT27
SIGGND3
VOUT28
VOUT29
VOUT30
VOUT31
NC
NC
NC
NC
13
14
15
16
25 26 27
31
30
29
28
32
57 56 55 54 53 52 51 50 49
100605
Figure 6.64-Lead LQFP
Pin Configuration
1
2
3
4
5
6
7
8
9
10
11
12
13
14
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
42
41
40
39
38
37
36
35
34
33
32
31
30
29
5
6
5
5
5
4
5
3
5
2
5
1
5
0
4
9
4
8
4
7
4
6
4
5
4
4
4
3
LDAC
CLR
RESET
BUSY
VOUT27
SIGGND3
VOUT28
VOUT29
VOUT30
VOUT31
NC
VDD
VSS
VREF1
NC = NO CONNECT
PIN 1
INDICATOR
AD5372/
AD5373
TOP VIEW
(Not to scale)
V
O
U
T
8
V
O
U
T
9
V
O
U
T
1
0
V
O
U
T
1
1
S
I
G
G
N
D
1
V
O
U
T
1
2
V
O
U
T
1
3
V
O
U
T
1
4
V
O
U
T
1
5
V
O
U
T
1
6
V
O
U
T
1
7
V
O
U
T
1
8
V
O
U
1
T
9
S
I
G
G
N
D
2
VOUT5
VOUT4
SIGGND0
VOUT3
VOUT2
VOUT1
VOUT0
VREF0
VOUT23
VOUT22
VOUT21
VOUT20
VSS
VDD
C
L
R
L
D
A
C
A
G
N
D
D
G
N
D
D
V
C
C
S
D
O
P
E
C
S
D
I
S
C
L
K
S
Y
N
C
D
V
C
C
D
G
N
D
V
O
U
T
7
V
O
U
T
6
5372-0060
Figure 7. 56-Lead LFCSP
Pin Configuration
Table 5. Pin Function Descriptions
Pin Function
DV
CC
Logic Power Supply; 2.5 V to 5.5 V. These pins should be decoupled with 0.1 F ceramic capacitors and 10 F
capacitors.
V
SS
Negative Analog Power Supply; -11.4 V to -16.5 V for specified performance. These pins should be decoupled with
0.1 F ceramic capacitors and 10 F capacitors.
V
DD
Positive Analog Power Supply; +11.4 V to +16.5 V for specified performance. These pins should be decoupled with
0.1 F ceramic capacitors and 10 F capacitors.
AGND
Ground for All Analog Circuitry. All AGND pins should be connected to the AGND plane.
DGND
Ground for All Digital Circuitry. All DGND pins should be connected to the DGND plane.
V
REF
0
Reference Input for DACs 0 to 7. This reference voltage is referred to AGND.
V
REF
1
Reference Input for DACs 8 to 31. This reference voltage is referred to AGND.
VOUT0 to VOUT31
DAC Outputs. Buffered analog outputs for each of the 40 DAC channels. Each analog output is capable of driving an
output load of 10 k to ground. Typical output impedance of these amplifiers is 1 .
SYNC
1
Active Low Input. This is the frame synchronization signal for the serial interface.
SCLK
1
Serial Clock Input. Data is clocked into the shift register on the falling edge of SCLK. This pin operates at clock speeds
up to 50 MHz.
SDI
1
Serial Data Input. Data must be valid on the falling edge of SCLK.
SDO
1
Serial Data Output. CMOS output. SDO can be used for readback. Data is clocked out on SDO on the rising edge of
SCLK and is valid on the falling edge of SCLK.
CLR
Asynchronous Clear Input (level sensitive, active low). See the Clear Function section for more information
LDAC
Load DAC Logic Input (Active Low).See the BUSY AND LDAC FUNCTIONS section for more information.
RESET
Asynchronous Digital Reset Input.
AD5372/AD5373
Preliminary Technical Data
Rev. Pr C| Page 10 of 24
Pin Function
BUSY
Digital Input/Open-Drain Output. See the BUSY AND LDAC FUNCTIONS section for more information
SIGGND0
Reference Ground for DACs 0 to 7. VOUT0 to VOUT7 are referenced to this voltage.
SIGGND1
Reference Ground for DACs 8 to 15. VOUT7 to VOUT15 are referenced to this voltage.
SIGGND1
Reference Ground for DACs 16 to 23. VOUT16 to VOUT23 are referenced to this voltage.
SIGGND3
Reference Ground for DACs 24 and 31. VOUT24 to VOUT31 are referenced to this voltage.
EXPOSED PADDLE
The Lead Free Chip Scale Package (LFCSP) has an exposed paddle on the underside. This should be connected to V
SS
Preliminary Technical Data
AD5372/AD5373
Rev. Pr C | Page 11 of 24
TERMINOLOGY
Relative Accuracy
Relative accuracy, or endpoint linearity, is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after
adjusting for zero-scale error and full-scale error and is
expressed in least significant bits (LSB).
Differential Nonlinearity
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of 1 LSB maximum
ensures monotonicity.
Zero-Scale Error
Zero-scale error is the error in the DAC output voltage when all
0s are loaded into the DAC register.
Zero-scale error is a measure of the difference between VOUT
(actual) and VOUT (ideal) expressed in mV. Zero-scale error is
mainly due to offsets in the output amplifier.
Full-Scale Error
Full-scale error is the error in DAC output voltage when all 1s
are loaded into the DAC register.
Full-scale error is a measure of the difference between VOUT
(actual) and VOUT (ideal) expressed in mV. It does not include
zero-scale error.
Gain Error
Gain error is the difference between full-scale error
and zero-scale error. It is expressed in mV.
Gain Error = Full-Scale Error - Zero-Scale Error
VOUT Temperature Coefficient
This includes output error contributions from linearity, offset,
and gain drift.
DC Output Impedance
DC output impedance is the effective output source resistance.
It is dominated by package lead resistance.
DC Crosstalk
The DAC outputs are buffered by op amps that share common
V
DD
and V
SS
power supplies. If the dc load current changes in
one channel (due to an update), this can result in a further dc
change in one or more channel outputs. This effect is more
significant at high load currents and reduces as the load
currents are reduced. With high impedance loads, the effect is
virtually immeasurable. Multiple V
DD
and V
SS
terminals are
provided to minimize dc crosstalk.
Output Voltage Settling Time
The amount of time it takes for the output of a DAC to settle to
a specified level for a full-scale input change.
Digital-to-Analog Glitch Energy
The amount of energy injected into the analog output at the
major code transition. It is specified as the area of the glitch in
nV-s. It is measured by toggling the DAC register data between
0x1FFF and 0x2000.
Channel-to-Channel Isolation
Channel-to-channel isolation refers to the proportion of input
signal from one DAC's reference input that appears at the
output of another DAC operating from another reference. It is
expressed in dB and measured at midscale.
DAC-to-DAC Crosstalk
DAC-to-DAC crosstalk is the glitch impulse that appears at the
output of one converter due to both the digital change and
subsequent analog output change at another converter. It is
specified in nV-s.
Digital Crosstalk
The glitch impulse transferred to the output of one converter
due to a change in the DAC register code of another converter is
defined as the digital crosstalk and is specified in nV-s.
Digital Feedthrough
When the device is not selected, high frequency logic activity on
the device's digital inputs can be capacitively coupled both
across and through the device to show up as noise on the
VOUT pins. It can also be coupled along the supply and ground
lines. This noise is digital feedthrough.
Output Noise Spectral Density
Output noise spectral density is a measure of internally
generated random noise. Random noise is characterized as a
spectral density (voltage per Hz). It is measured by loading all
DACs to midscale and measuring noise at the output. It is
measured in nV/(Hz)
1/2
AD5372/AD5373
Preliminary Technical Data
Rev. Pr C| Page 12 of 24
FUNCTIONAL DESCRIPTION
DAC ARCHITECTURE--GENERAL
The ADAD5372/AD5373 contains 32 DAC channels and 32
output amplifiers in a single package. The architecture of a
single DAC channel consists of a 16-bit (AD5372) or 14-bit
(AD5373) resistor-string DAC followed by an output buffer
amplifier. The resistor-string section is simply a string of
resistors, each of value R, from V
REF
to AGND. This type of
architecture guarantees DAC monotonicity. The 16-bit
(AD5372) or 14-bit (AD5373) binary digital code loaded to the
DAC register determines at which node on the string the
voltage is tapped off before being fed into the output amplifier.
The output amplifier multiplies the DAC out voltage by 4. The
output span is 12 V with a 3 V reference and 20 V with a 5 V
reference.
CHANNEL GROUPS
The 32 DAC channels of the AD5372/AD5373 are arranged into
four groups of 8 channels. The eight DACs of Group 0 derive
their reference voltage from VREF0. Group 1 to Group 3 derive
their reference voltage from VREF1. Each group has its own
signal ground pin.
Table 6. AD5372(AD5373) Registers
Register Name
Word Length (Bits)
Description
X1A (group)(channel)
16(14)
Input data register A, one for each DAC channel.
X1B (group) (channel)
16(14)
Input data register B, one for each DAC channel.
M (group) (channel)
16(14)
Gain trim registers, one for each DAC channel.
C (group) (channel)
16(14)
Offset trim registers, one for each DAC channel.
X2A (group)(channel)
16(14)
Output data register A, one for each DAC channel. These registers store the final,
calibrated DAC data after gain and offset trimming. They are not readable, nor directly
writable.
X2B (group) (channel)
16(14)
Output data register B, one for each DAC channel. These registers store the final,
calibrated DAC data after gain and offset trimming. They are not readable, nor directly
writable.
DAC (group) (channel)
Data registers from which the DACs take their final input data. The DAC registers are
updated from the X2A or X2B registers. They are not readable, nor directly writable.
OFS0
14
Offset DAC 0 data register, sets offset for Group 0.
OFS1
14
Offset DAC 1 data register, sets offset for Groups 1 to 3.
Control
3
Bit 2 = A/B. 0 = global selection of X1A input data registers. 1 = X1B registers.
Bit 1 = Soft Power Down. 0 = soft power up. 1 = soft power down
Bit 0 = Enable Temp Shutdown. 0 = disable temp shutdown. 1 = enable.
A/B Select 0
8
Each bit in this register determines if a DAC in Group 0 takes its data from register
X2A or X2B (0 = X2A, 1 = X2B)
A/B Select 1
8
Each bit in this register determines if a DAC in Group 1 takes its data from register
X2A or X2B (0 = X2A, 1 = X2B)
A/B Select 2
8
Each bit in this register determines if a DAC in Group 2 takes its data from register
X2A or X2B (0 = X2A, 1 = X2B)
A/B Select 3
8
Each bit in this register determines if a DAC in Group 3 takes its data from register
X2A or X2B (0 = X2A, 1 = X2B)
Preliminary Technical Data
AD5372/AD5373
Rev. Pr C | Page 13 of 24
A/ B REIGSTERS AND GAIN/OFFSET ADJUSTMENT
Each DAC channel has seven data registers. The actual DAC
data word can be written to either the X1A or X1B input
register, depending on the setting of the A/B bit in the Control
Register. If the A/B bit is 0, data will be written to the X1A
register. If the A/B bit is 1, data will be written to the X1B
register. Note that this single bit is a global control and affects
every DAC channel in the device. It is not possible to set up the
device on a per-channel basis so that some writes are to X1A
registers and some writes are to X1B registers.
DAC
DAC
REGISTER
MUX
X2B
REGISTER
X2A
REGISTER
MUX
M
REGISTER
C
REGISTER
X1B
REGISTER
X1A
REGISTER
Figure 8. Data Registers Associated With Each DAC Channel
Each DAC channel also has a gain (M) and offset (C) register,
which allow trimming out of the gain and offset errors of the
entire signal chain. Data from the X1A register is operated on
by a digital multiplier and adder controlled by the contents of
the M and C registers. The calibrated DAC data is then stored in
the X2A register. Similarly, data from the X1B register is
operated on by the multiplier and adder and stored in the X2B
register.
Although a multiplier and adder symbol are shown for each
channel, there is only one multiplier and one adder in the
device, which are shared between all channels. This has
implications for the update speed when several channels are
updated at once, as described later.
Each time data is written to the X1A register, or to the M or C
register with the A/B control bit set to 0, the X2A data is
recalculated and the X2A register is automatically updated.
Similarly, X2B is updated each time data is written to X1B, or to
M or C with A/B set to 1. The X2A and X2B registers are not
readable, nor directly writable by the user.
Data output from the X2A and X2B registers is routed to the
final DAC register by a multiplexer. Whether each individual
DAC takes its data from the X2A or X2B register is controlled
by an 8-bit A/B Select Register associated with each group of 8
DACs. If a bit in this register is 0, the DAC takes its data from
the X2A register; if 1 the DAC takes its data from the X2B
register (bit 0 controls DAC 0 through bit 7 controls DAC 7).
Note that, since there are 32 bits in 4 registers, it is possible to
set up, on a per-channel basis, whether each DAC takes its data
from the X2A or X2B register. A global command is also
provided that sets all bits in the A/B Select Registers to 0 or to 1.
LOAD DAC
All DACs in the AD5372/AD5373 can be updated
simultaneously by taking LDAC low, when each DAC register
will be updated from either its X2A or X2B register, depending
on the setting of the A/B select registers. The DAC register is
not readable, nor directly writable by the user.
OFFSET DACS
In addition to the gain and offset trim for each DAC, there are
two 16-bit (AD5372) or 14-bit (AD5373) Offset DACs, one for
Group 0, and one for Group 1 to Group 3. These allow the
output range of all DACs connected to them to be offset. Thus,
subject to the limitations of headroom, it is possible to set the
output range of Group 0 or Group 1 to Group3 to be unipolar
positive, unipolar negative, or bipolar, either symmetrical or
asymmetrical about zero volts.
OUTPUT AMPLIFIER
As the output amplifiers can swing to 1.4 V below the positive
supply and 1.4 V above the negative supply, this limits how
much the output can be offset for a given reference voltage. For
example, it is not possible to have a unipolar output range of
20V, since the maximum supply voltage is 16.5 V.
DAC
CHANNEL
OFFSET
DAC
CLR
CLR
CLR
SIGGND
SIGGND
OUTPUT
S1
S2
S3
R4
R1
R3
R5
R6
R2
CHECK VALUE OF R1 &R5
R1,R2,R3 = 20k
R4,R5 = 60k
R6 = 10k
2049-0008
10k
Figure 9. Output Amplifier and Offset DAC
Figure 9 shows details of a DAC output amplifier and its
connections to the Offset DAC. On power up, S1 is open,
disconnecting the amplifier from the output. S3 is closed, so the
output is pulled to SIGGND (R1 and R2 are very much greater
than R6). S2 is also closed to prevent the output amplifier being
open-loop. If CLR is low at power-up, the output will remain in
this condition until CLR is taken high. The DAC registers can
be programmed, and the outputs will assume the programmed
values when CLR is taken high. Even if CLR is high at power-
up, the output will remain in the above condition until
V
DD
> 6 V and V
SS
< -4 V and the initialization sequence has
finished. The outputs will then go to their power-on default
value.
AD5372/AD5373
Preliminary Technical Data
Rev. Pr C | Page 14 of 24
TRANSFER FUNCTION
The output voltage of a DAC in the AD5372/AD5373 is
dependent on the value in the input register, the value of the M
and C registers, and the offset from the Offset DAC. The
transfer functions for the AD5372 and AFD5373 are shown
below.
AD5372 Transfer Function
Code applied to DAC from X1A or X1B register:-
DAC_CODE = INPUT_CODE
(m+1)/2
16
+ c - 2
15
DAC output voltage:-
V
OUT
= 4
V
REF
(DAC_CODE OFFSET_CODE )/2
16
+V
SIGGND
Notes
Gain = 4.
For 12 V span V
REF
= 3.0 V.
For 20 V span V
REF
= 5.0 V.
X1A, X1B default code = 21844
m = code in gain register - default code = 2
16
1.
c = code in offset register - default code = 2
14
.
OFFSET_CODE is the code loaded to the offset DAC. It is
multiplied by 4 in the transfer function as this DAC is a 14 bit
device. On power up the default code loaded to the offset DAC
is 5461 (0x1555). With a 3V reference this gives a span of -4 V
to +8 V.
AD5373 Transfer Function
Code applied to DAC from X1A or X1B register:-
DAC_CODE = INPUT_CODE
(m+1)/2
14
+ c - 2
13
DAC output voltage:-
V
OUT
= 4
V
REF
(DAC_CODE OFFSET_CODE )/2
14
+V
SIGGND
Notes
Gain = 4.
For 12 V span V
REF
= 3.0 V.
For 20 V span V
REF
= 5.0 V.
X1A, X1B default code = 5461
m = code in gain register - default code = 2
14
1.
c = code in offset register - default code = 2
13
.
OFFSET_CODE is the code loaded to the offset DAC. It is
multiplied by 4 in the transfer function as this DAC is a 14 bit
device. On power up the default code loaded to the offset DAC
is 5461 (0x1555). With a 3V reference this gives a span of -4 V
to +8 V.
REFERENCE SELECTION
The AD5372/AD5373 has two reference input pins. The voltage
applied to the reference pins determines the output voltage span
on VOUT0 to VOUT31. VREF0 determines the voltage span for
VOUT0 to VOUT7 (Group 0) and VREF1 determines the
voltage span for VOUT8 to VOUT31 (Group 1 to Group 3).
The reference voltage applied to each VREF pin can be
different, if required, allowing the groups to have a different
voltage spans. The output voltage range can be adjusted further
by programming the offset and gain registers for each channel
as well as programming the offset DACs. If the offset and gain
features are not used (i.e. the m and c registers are left at their
default values) the required reference levels can be calculated as
follows:
VREF = (VOUT
max
VOUT
min
)/4
If the offset and gain features of the AD5372/AD5373 are used,
then the required output range is slightly different. The chosen
output range should take into account the system offset and
gain errors that need to be trimmed out. Therefore, the chosen
output range should be larger than the actual, required range.
The required reference levels can be calculated as follows:
1.
Identify the nominal output range on VOUT.
2.
Identify the maximum offset span and the maximum
gain required on the full output signal range.
3.
Calculate the new maximum output range on VOUT
including the expected maximum offset and gain
errors.
4.
Choose the new required VOUT
max
and VOUT
min
,
keeping the VOUT limits centered on the nominal
values. Note that V
DD
and V
SS
must provide sufficient
headroom.
5.
Calculate the value of VREF as follows:
VREF = (VOUTMAX VOUTMIN)/4
Reference Selection Example
Nominal Output Range = 12V (-4V to +8V)
Offset Error = 70mV
Gain Error = 3%
SIGGND = AGND = 0V
1)
Gain Error = 3%
=> Maximum Positive Gain Error = +3%
=> Output Range incl. Gain Error = 12 + 0.03(12)=12.36V
2)
Offset Error = 70mV
=> Maximum Offset Error Span = 2(70mV)=0.14V
=> Output Range including Gain Error and Offset Error =
12.36V + 0.14V = 12.5V
3)
VREF Calculation
Actual Output Range = 12.5V, that is -4.25V to +8.25V
(centered);
VREF = (8.25V + 4.25V)/4 = 3.125V
If the solution yields an inconvenient reference level, the user
can adopt one of the following approaches:
1.
Use a resistor divider to divide down a convenient,
higher reference level to the required level.
Preliminary Technical Data
AD5372/AD5373
Rev. Pr C | Page 15 of 24
2.
Select a convenient reference level above VREF and
modify the Gain and Offset registers to digitally
downsize the reference. In this way the user can use
almost any convenient reference level but may reduce
the performance by overcompaction of the transfer
function.
3.
Use a combination of these two approaches
CALIBRATION
The user can perform a system calibration by overwriting the
default values in the m and c registers for any individual DAC
channels as follows:
Calculate the nominal offset and gain coefficients for the
new output range (see previous example)
Calculate the new m and c values for each channel based on
the specified offset and gain errors
Calibration Example
AD5373 Nominal Offset Coefficient = 8192
AD5373 Nominal Gain Coefficient = 12/12.5 16383 = 15728
Example 1: AD5373 Gain Error = 3%, Offset Error = 70mV
1) Gain Error (3%) Calibration: 15728 1.03 = 16200
=> Load Code "0b0011 1111 0100 1000" to m register
2) Offset Error (70mV) Calibration:
LSB Size = 12.5/16384 = 763 V;
Offset Coefficient for 70mV Offset = 70/0.763 = 92 LSBs
=> Load Code "0b1000 0000 0101 1100" to c register
For the AD5372 the 16-bit nominal gain and offset values
should be used.
RESET FUNCTION
When the RESET pin is taken low, the DAC buffers are
disconnected and the DAC outputs VOUT0 to VOUT31 are
tied to their associated SIGGND signals via a 10 k resistor. On
the rising edge of RESET the AD5372/AD5373 state machine
initiates a reset sequence to reset the X, M and C registers to
their default values. This sequence typically takes 300s and the
user should not write to the part during this time. When the
reset sequence is complete, and provided that CLR is high, the
DAC output will be at a potential specified by the default
register settings which will be equivalent to SIGGGND. The
DAC outputs will remain at SIGGND until the X, M or C
registers are updated and LDAC is taken low.
CLEAR FUNCTION
CLR is an active low input which should be high for normal
operation. The CLR pin has in internal 500k pull-down
resistor. When CLR is low, the input to each of the DAC output
buffer stages, VOUT0 to VOUT31, is switched to the externally
set potential on the relevant SIGGND pin. While CLR is low, all
LDAC pulses are ignored. When CLR is taken high again, the
DAC outputs remain cleared until LDAC is taken low. The
contents of input registers and DAC registers 0 to 31 are not
affected by taking CLR low. To prevent glitches appearing on
the outputs CLR should be brought low whenever the output
span is adjusted by writing to the offset DAC.
BUSY AND LDAC FUNCTIONS
The value of an X2 (A or B) register is calculated each time the
user writes new data to the corresponding X1, C, or M registers.
During the calculation of X2, the BUSY output goes low. While
BUSY is low, the user can continue writing new data to the X1,
M, or C registers, but no DAC output updates can take place.
The BUSY pin is bidirectional and has a 50 k internal pullup
resistor. Where multiple AD5372 or AD5373 devices may be
used in one system the BUSY pins can be tied together. This is
useful where it is required that no DAC in any device is updated
until all other DACs are ready. When each device has finished
updating the X2 (A or B) registers it will release the BUSY pin.
If another device hasn't finished updating its X2 registers it will
hold BUSY low, thus delaying the effect of LDAC going low.
The DAC outputs are updated by taking the LDAC input low. If
LDAC goes low while BUSY is active, the LDAC event is stored
and the DAC outputs update immediately after BUSY goes
high. A user can also hold the LDAC input permanently low. In
this case, the DAC outputs update immediately after BUSY
goes high.
As described later, the ADAD5372/AD5373 has flexible
addressing that allows writing of data to a single channel, all
channels in a group, the same channel in groups 0 to 3 or
groups 1 to 4, or all channels in the device. This means that 1, 4,
8 or 32 DAC register values may need to be calculated and
updated. As there is only one multiplier shared between 32
channels, this task must be done sequentially, so the length of
the BUSY pulse will vary according to the number of channels
being updated.
Table 7. BUSY Pulse Widths
Action
BUSY Pulse Width
(s max)
Loading Input, C, or M to 1 channel
1.25
Loading Input, C, or M to 4 channels
2.75
Loading Input, C, or M to 8 channels
4.75
Loading Input, C, or M to 32 channels
16.75
BUSY Pulse Width = ((Number of Channels +1) 500ns) +250ns
The AD5372/AD5373 contains an extra feature whereby a DAC
register is not updated unless its X2A or X2B register has been
AD5372/AD5373
Preliminary Technical Data
Rev. Pr C | Page 16 of 24
written to since the last time LDAC was brought low. Normally,
when LDAC is brought low, the DAC registers are filled with
the contents of the X2A or X2B registers, depending on the
setting of the A/B Select Registers. However the
AD5372/AD5373 updates the DAC register only if the X2 data
has changed, thereby removing unnecessary digital crosstalk.
POWER-DOWN MODE
The AD5372/AD5373 can be powered down by setting Bit 0 in
the control register. This will turn off the DACs thus reducing
the current consumption. The DAC outputs will be connected
to their respective SIGGND potentials. The power-down mode
doesn't change the contents of the registers and the DACs will
return to their previous voltage when the power-down bit is
cleared.
THERMAL MONITOR FUNCTION
The AD5372/AD5373 can be programmed to power down the
DACs if the temperature on the die exceeds 130C. Setting Bit 1
in the control register (see Table 15) will enable this function. If
the die temperature exceeds 130C the AD5372/AD5373 will
enter a temperature power-down mode, which is equivalent to
setting the power-down bit in the control register. To indicate
that the AD5372/AD5373 has entered temperature power-down
mode Bit 4 of the control register is set. The AD5372/AD5373
will remain in temperature shutdown mode, even if the die
temperature falls, until Bit 1 in the control register is cleared.
TOGGLE MODE
The AD5372/AD5373 has two X2 registers per channel, X2A
and X2B, which can be used to switch the DAC output between
two levels with ease. This approach greatly reduces the overhead
required by a micro-processor which would otherwise have to
write to each channel individually. When the user writes to
either the X1A ,X2A, M or C registers the calculation engine
will take a certain amount of time to calculate the appropriate
X2A or X2B values. If the application only requires that the
DAC output switch between two levels, such as a data generator,
any method which reduces the amount of calculation time
encountered is advantageous. For the data generator example
the user need only set the high and low levels for each channel
once, by writing to the X1A and X1B registers. The values of
X2A and X2B will be calculated and stored in their respective
registers. The calculation delay therefore only happens during
the setup phase, i.e. when programming the initial values. To
toggle a DAC output between the two levels it is only required
to write to the relevant A/B Select Register to set the MUX2
register bit. Furthermore, since there are 8 MUX2 control bits
per register it is possible to update eight channels with a single
write. Table 17 shows the bits that correspond to each DAC
output.
Preliminary Technical Data
AD5372/AD5373
Rev. Pr C | Page 17 of 24
SERIAL INTERFACE
The AD5372/AD5373 contains a high-speed SPI serial interface
operating at clock frequencies up to 50 MHz. To minimize both
the power consumption of the device and on-chip digital noise,
the interface powers up fully only when the device is being
written to, that is, on the falling edge of SYNC. The serial
interface is 2.5 V LVTTL compatible when operating from a 2.7
V to 3.6 V DV
CC
supply. It is controlled by four pins, as follows.
SYNC
Frame synchronization input.
SDI
Serial data input pin.
SCLK
Clocks data in and out of the device.
SDO
Serial data output pin for data readback.
SPI WRITE MODE
The AD5372AD5373 allows writing of data via the serial
interface to every register directly accessible to the serial
interface, which is all registers except the X2A and X2B
registers and the DAC registers. The X2A and X2B registers are
update when writing to the X1A, X1B, M and C registers, and
the DAC registers are updated by LDAC. The serial word (see
Table 8 or Table 9) is 24 bits long. 16 or 14 of these bits are data
bits, six bits are address bits, and two bits are mode bits that
determine what is done with the data. Two bits are reserved on
the AD5373.
The serial interface works with both a continuous and a burst
(gated) serial clock. Serial data applied to SDI is clocked into
the AD5372AD5373 by clock pulses applied to SCLK. The first
falling edge of SYNC starts the write cycle. At least 24 falling
clock edges must be applied to SCLK to clock in 24 bits of data,
before SYNC is taken high again. If SYNC is taken high before
the 24th falling clock edge, the write operation will be aborted.
If a continuous clock is used, SYNC must be taken high before
the 25th falling clock edge. This inhibits the clock within the
AD5372/AD5373. If more than 24 falling clock edges are
applied before SYNC is taken high again, the input data will be
corrupted. If an externally gated clock of exactly 24 pulses is
used, SYNC may be taken high any time after the 24th falling
clock edge.
The input register addressed is updated on the rising edge of
SYNC. In order for another serial transfer to take place, SYNC
must be taken low again
Table 8. AD5372 Serial Word Bit Assignation
I23 I22 I21 I20 I19 I18 I17 I16 I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 I0
M1 M0 A5 A4 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Table 9. AD5373 Serial Word Bit Assignation
I23 I22 I21 I20 I19 I18 I17 I16 I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1* I0*
M1 M0 A5 A4 A3 A2 A1 A0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0
*
Reserved bits. Set to 0 when writing. Bits are read back as 0
AD5372/AD5373
Preliminary Technical Data
Rev. Pr C | Page 18 of 24
SPI READBACK MODE
The ADAD5372/AD5373 allows data readback via the serial
interface from every register directly accessible to the serial
interface, which is all registers except the DAC data registers. In
order to read back a register, it is first necessary to tell the
ADAD5372/AD5373 which register is to be read. This is
achieved by writing to the device a word whose first two bits are
the special function code 00. The remaining bits then
determine if the operation is a readback, and the register which
is to be read back, or if it is a write to of the special function
registers such as the control register.
After the special function write has been performed, if it is a
readback command then data from the selected register will be
clocked out of the SDO pin during the next SPI operation. The
SDO pin is normally three-state but becomes driven as soon as
a read command has been issued. The pin will remain driven
until the registers data has been clocked out. See Figure 5 for
the read timing diagram.
REGISTER UPDATE RATES
As mentioned previously the value of the X2 (A or B) register is
calculated each time the user writes new data to the
corresponding X1, C or M registers. The calculation is
performed by a three stage process. The first two stages take
500ns each and the third stage takes 250ns. When the writes to
one of the X1, C or M registers is complete the calculation
process begins. If the write operation involves the update of a
single DAC channel the user is free to write to another register
provided that the write operation doesn't finish until the first
stage calculation is complete, i.e. 500ns after the completion of
the first write operation. If a group of channels is being updated
by a single write operation the first stage calculation will be
repeated for each channel, taking 500ns per channel. In this
case the user should not complete the next write operation until
this time has elapsed.
CHANNEL ADDRESSING AND SPECIAL MODES
If the mode bits are not 00, then the data word D13 to D0 is
written to the device. Address bits A5 to A0 determine which
channel or channels is/are written to, while the mode bits
determine to which register (X1A, X1B, C or M) the data is
written, as shown in Table 8 and Table 9. If data is to be written
to the X1A or X1B register, the setting of the A/B bit in the
Control Register determines which (0
X1A, 1
X1B).
Table 10. Group Addressing
A5 A4 A3 Group
Selected
0
0
0
All groups, all DACs
0 0 1 0
0 1 0 1
0 1 1 2
1 0 0 3
1 0 1 4
1
1
0
1, 2, 3, 4, 5
1
1
1
2, 3, 4, 5
Table 11.
Channel Addressing
A2 A1 A0 Channel
Selected
0 0 0 0
0 0 1 1
0 1 0 2
0 1 1 3
1 0 0 4
1 0 1 5
1 1 0 6
1 1 1 7
Table 12.
Mode Bits
M1 M0 Action
1
1
Write DAC data (x) register
1
0
Write DAC offset (m) register
0
1
Write DAC gain (m) register
0 0 Special function, used in combination with other
bits of word
The AD5372/AD5373 has very flexible addressing that allows
writing of data to a single channel, all channels in a group, the
same channel in groups 0 to 3 or groups 1 to 3, or all channels
in the device Table 10 shows all these address modes.
Preliminary Technical Data
AD5372/AD5373
Rev. Pr C | Page 19 of 24
Table 13. Group and Channel Addressing
This table shows which groups(s) and which channel(s) is/are addressed for every combination of address bits A5 to A0.
ADDRESS BITS A5 TO A3
000 001 010
011
100 101 110
111
000
All groups,
all channels
Group 0,
channel 0
Group 1,
channel 0
Group 2,
channel 0
Group 3,
channel 0
Reserved Groups
0,1,2,3
channel 0
Groups 1,2,3
channel 0
001
Group 0, all
channels
Group 0,
channel 1
Group 1,
channel 1
Group 2,
channel 1
Group 3,
channel 1
Reserved Groups
0,1,2,3
channel 1
Groups 1,2,3
channel 1
010
Group 1, all
channels
Group 0,
channel 2
Group 1,
channel 2
Group 2,
channel 2
Group 3,
channel 2
Reserved Groups
0,1,2,3
channel 2
Groups 1,2,3
channel 2
011
Group 2, all
channels
Group 0,
channel 3
Group 1,
channel 3
Group 2,
channel 3
Group 3,
channel 3
Reserved Groups
0,1,2,3
channel 3
Groups 1,2,3
channel 3
100
Group 3, all
channels
Group 0,
channel 4
Group 1,
channel 4
Group 2,
channel 4
Group 3,
channel 4
Reserved Groups
0,1,2,3
channel 4
Groups 1,2,3
channel 4
101
Reserved Group
0,
channel 5
Group 1,
channel 5
Group 2,
channel 5
Group 3,
channel 5
Reserved Groups
0,1,2,3
channel 5
Groups 1,2,3
channel 5
110
Reserved Group
0,
channel 6
Group 1,
channel 6
Group 2,
channel 6
Group 3,
channel 6
Reserved Groups
0,1,2,3
channel 6
Groups 1,2,3
channel 6
ADDRESS
BITS A2 TO
A0
111
Reserved Group
0,
channel 7
Group 1,
channel 7
Group 2,
channel 7
Group 3,
channel 7
Reserved Groups
0,1,2,3
channel 7
Groups 1,2,3
channel 7
SPECIAL FUNCTION MODE
If the mode bits are 00, then the special function mode is
selected, as shown in Table 14. Bits I21 to I16 of the serial data
word select the special function, while the remaining bits are
data required for execution of the special function, for example
the channel address for data readback.
The codes for the special functions are shown in Table 15. Table
16 shows the addresses for data readback.
Table 14. Special Function Mode
I23 I22 I21 I20 I19 I18 I17 I16 I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 I0
0 0 S5 S4 S3 S2 S1 S0 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
AD5372/AD5373
Preliminary Technical Data
Rev. Pr C | Page 20 of 24
Table 15.
Special Function Codes
SPECIAL FUNCTION CODE
DATA
S5 S4 S3 S2 S1 S0 F15-F0
ACTION
0 0 0 0 0 0 0000
0000
0000
0000
NOP
0
0
0
0
0
1
XXXX XXXX XXXX X[F2:F0]
Write control register
F2 = 1
Select B reg for input; F2 = 0
Select A reg for input
F1 = 1
En temp shutdown; F1 = 0
Disable temp shutdown
F0 = 1
Soft power down; F0 = 0
soft power up
0
0
0
0
1
0
XX[F13:F0]
Write data in F13:F0 to OFS0 register
0
0
0
0
1
1
XX[F13:F0]
Write data in F13:F0 to OFS1 register
0 0 0 1 0 0 XX[F13:F0]
Reserved
0 0 0 1 0 1
See Table 14
Select register for readback
0
0
0
1
1
0
XXXX XXXX[F7:F0]
Write data in F7:F0 to A/B Select Register 0
0
0
0
1
1
1
XXXX XXXX[F7:F0]
Write data in F7:F0 to A/B Select Register 1
0
0
1
0
0
0
XXXX XXXX[F7:F0]
Write data in F7:F0 to A/B Select Register 2
0
0
1
0
0
1
XXXX XXXX[F7:F0]
Write data in F7:F0 to A/B Select Register 3
0 0 1 0 1 0 XXXX
XXXX[F7:F0]
Reserved
0
0
1
0
1
1
XXXX XXXX[F7:F0]
Block write A/B Select Registers
F7:F0 = 0, write all 0's (all channels use X2A register)
F7:F0 = 1, wrote all 1's (all channels use X2B register)
Table 16. Address Codes for Data Readback
F15 F14 F13 F12 F11 F10 F9 F8 F7 REGISTER
READ
0 0 0
X1A
Register
0 0 1
X1B
Register
0 1 0
C
Register
0 1 1
Bits F12 to F7 select channel to be read
back, from Channel 0 = 000000 to
Channel 31 = 011111
M Register
1 0 0 0 0 0 0 0 1 Control
Register
1 0 0 0 0 0 0 1 0 OFS0
Data
Register
1 0 0 0 0 0 0 1 1 OFS1
Data
Register
1 0 0 0 0 0 1 0 0 Reserved
1 0 0 0 0 0 1 1 0 A/B
Select
Register
0
1 0 0 0 0 0 1 1 1 A/B
Select
Register
1
1 0 0 0 0 1 0 0 0 A/B
Select
Register
2
1 0 0 0 0 1 0 0 1 A/B
Select
Register
3
1 0 0 0 0 1 0 1 0 Reserved
Note: F6 to F0 are don't care for data readback function.
Preliminary Technical Data
AD5372/AD5373
Rev. Pr C | Page 21 of 24
Table 17. DACs Select by A/B Select Registers
Bits
A/B Select
Register
F7 F6 F5 F4 F3 F2 F1 F0
0
VOUT7 VOUT6 VOUT5 VOUT4 VOUT3 VOUT2 VOUT1 VOUT0
1
VOUT15 VOUT14 VOUT13 VOUT12 VOUT11 VOUT10 VOUT9 VOUT8
2
VOU23 VOUT22 VOUT21 VOUT20 VOUT19 VOUT18 VOUT17 VOUT16
3
VOUT31 VOUT30 VOUT29 VOUT28 VOUT27 VOUT26 VOUT25 VOUT24
POWER SUPPLY DECOUPLING
In any circuit where accuracy is important, careful considera-
tion of the power supply and ground return layout helps to
ensure the rated performance. The printed circuit board on
which the AD5372/AD5373 is mounted should be designed so
that the analog and digital sections are separated and confined
to certain areas of the board. If the AD5372/AD5373 is in a
system where multiple devices require an AGND-to-DGND
connection, the connection should be made at one point only.
The star ground point should be established as close as possible
to the device. For supplies with multiple pins (V
SS
, V
DD
, V
CC
), it
is recommended to tie these pins together and to decouple each
supply once.
The AD5372/AD5373 should have ample supply decoupling of
10 F in parallel with 0.1 F on each supply located as close to
the package as possible, ideally right up against the device. The
10 F capacitors are the tantalum bead type. The 0.1 F capaci-
tor should have low effective series resistance (ESR) and
effective series inductance (ESI), such as the common ceramic
types that provide a low impedance path to ground at high
frequencies, to handle transient currents due to internal logic
switching.
Digital lines running under the device should be avoided,
because these couple noise onto the device. The analog ground
plane should be allowed to run under the AD5372/AD5373 to
avoid noise coupling. The power supply lines of the
AD5372/AD5373 should use as large a trace as possible to
provide low impedance paths and reduce the effects of glitches
on the power supply line. Fast switching digital signals should
be shielded with digital ground to avoid radiating noise to other
parts of the board, and should never be run near the reference
inputs. It is essential to mini mize noise on all V
REF
lines.
Avoid crossover of digital and analog signals. Traces on
opposite sides of the board should run at right angles to each
other. This reduces the effects of feedthrough through the
board. A microstrip technique is by far the best, but not always
possible with a double-sided board. In this technique, the
component side of the board is dedicated to ground plane,
while signal traces are placed on the solder side.
As is the case for all thin packages, care must be taken to avoid
flexing the package and to avoid a point load on the surface of
this package during the assembly process.
POWER SUPPLY SEQUENCING
When the supplies are connected to the AD5372/AD5373 it is
important that the AGND and DGND pins are connected to the
relevant ground plane before the positive or negative supplies
are applied. In most applications this is not an issue as the
ground pins for the power supplies will be connected to the
ground pins of the AD5372/AD5373 via ground planes. Where
the AD5372/AD5373 is to be used in a hot-swap card care
should be taken to ensure that the ground pins are connected to
the supply grounds before the positive or negative supplies are
connected. This is required to prevent currents flowing in
directions other than towards an analog or digital ground.
AD5372/AD5373
Preliminary Technical Data
Rev. Pr C | Page 22 of 24
INTERFACING EXAMPLES
The SPI interface of the AD5372/AD5373 is designed to allow
the parts to be easily connected to industry standard DSPs and
micro-controllers. Figure 10 shows how the AD5372/AD5373
could be connected to the Analog Devices BlackfinTM DSP. The
Blackfin has an integrated SPI port which can be connected
directly to the SPI pins of the AD5372/AD5373 and
programmable I/O pins which can be used to set or read the
state of the digital input or output pins associated with the
interface.
SYNC
SCLK
SDI
SDO
CLR
LDAC
RESET
BUSY
SPISELx
SCK
MOSI
MISO
PF8
PF9
PF10
PF7
AD537x
ADSP-BF531
537x-0101
Figure 10. Interfacing to a Blackfin DSP
The Analog Devices ADSP-21065L is a floating point DSP with
two serial ports (SPORTS). Figure 11 shows how one SPORT
can be used to control the AD5372/AD5373. In this example
the Transmit Frame Synchronization (TFS) pin is connected to
the Receive Frame Synchronization (RFS) pin. Similarly the
transmit and receive clocks (TCLK and RCLK) are also
connected together. The user can write to the AD5372/AD5373
by writing to the transmit register. A read operation can be
accomplished by first writing to the AD5372/AD5373 to tell the
part that a read operation is required. A second write operation
with a NOP instruction will cause the data to be read from the
AD5372/AD5373. The DSPs receive interrupt can be used to
indicate when the read operation is complete.
SYNC
SCLK
SDI
SDO
CLR
LDAC
RESET
BUSY
TFSx
RFSx
TCLKx
RCLKx
DTxA
DRxA
FLAG2
FLAG1
FLAG0
FLAG3
AD537x
537x-0101
ADSP-21065L
Figure 11. Interfacing to an ADSP-21065L DSP
Preliminary Technical Data
AD5372/AD5373
Rev. Pr C | Page 23 of 24
OUTLINE DIMENSIONS
TOP VIEW
(PINS DOWN)
1
16
17
33
32
48
49
64
0.27
0.22
0.17
0.50
BSC
10.00
BSC SQ
1.60
MAX
SEATING
PLANE
0.75
0.60
0.45
VIEW A
12.00
BSC SQ
0.20
0.09
1.45
1.40
1.35
0.08 MAX
COPLANARITY
VIEW A
ROTATED 90 CCW
SEATING
PLANE
10
6
2
7
3.5
0
0.15
0.05
PIN 1
COMPLIANT TO JEDEC STANDARDS MS-026BCD
Figure 12. 64-Lead Low Profile Quad Flat Package [LQFP]
(ST-64-2)
Dimensions shown in millimeters
PIN 1
INDICATOR
TOP
VIEW
7.75
BSC SQ
8.00
BSC SQ
1
56
14
15
43
42
28
29
6.25
6.10 SQ
5.95
0.50
0.40
0.30
0.30
0.23
0.18
0.50 BSC
0.20 REF
12 MAX
0.80 MAX
0.65 TYP
1.00
0.85
0.80
6.50
REF
SEATING
PLANE
0.60 MAX
0.60 MAX
PIN 1
INDICATOR
COPLANARITY
0.08
0.05 MAX
0.02 NOM
0.25 MIN
EXPOSED
PAD
(BOTTOM VIEW)
COMPLIANT TO JEDEC STANDARDS MO-220-VLLD-2
Figure 13. 56-Lead Free Chip Scale Package [LFCSP]
(CP-56)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
AD5372BSTZ
-40C to +85C
64-Lead LQFP
ST-64
AD5372BCPZ
-40C to +85C
56-Lead LFCSP
CP-56
AD5373BSTZ
-40C to +85C
64-Lead LQFP
ST-64
AD5373BCPZ
-40C to +85C
56-Lead LFCSP
CP-56
AD5372/AD5373
Preliminary Technical Data
Rev. Pr C | Page 24 of 24
NOTES
PR05815-0-10/05(PrC)
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