REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
AD538
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
Analog Devices, Inc., 1999
Real-Time Analog
Computational Unit (ACU)
FUNCTIONAL BLOCK DIAGRAM
25k
25k
LOG
RATIO
100
25k
25k
ANTILOG
LOG
OUTPUT
100
AD538
INTERNAL
VOLTAGE
REFERENCE
I
V
O
I
Z
V
Z
B
+10V
V
S
+V
S
+2V
I
Y
A
D
I
X
V
X
C
PWR
GND
SIGNAL
GND
V
Y
1
18
17
16
15
14
13
12
11
10
2
3
4
5
6
7
8
9
FEATURES
V
OUT
= V
Y
V
Z
V
X
m
Transfer Function
Wide Dynamic Range (Denominator) 1000:1
Simultaneous Multiplication and Division
Resistor-Programmable Powers and Roots
No External Trims Required
Low Input Offsets <100 V
Low Error 0.25% of Reading (100:1 Range)
+2 V and +10 V On-Chip References
Monolithic Construction
APPLICATIONS
One- or Two-Quadrant Mult/Div
Log Ratio Computation
Squaring/Square Rooting
Trigonometric Function Approximations
Linearization Via Curve Fitting
Precision AGC
Power Functions
PRODUCT DESCRIPTION
The AD538 is a monolithic real-time computational circuit that
provides precision analog multiplication, division and exponen-
tiation. The combination of low input and output offset voltages
and excellent linearity results in accurate computation over an
unusually wide input dynamic range. Laser wafer trimming makes
multiplication and division with errors as low as 0.25% of read-
ing possible, while typical output offsets of 100
V or less add to
the overall off-the-shelf performance level. Real-time analog
signal processing is further enhanced by the device's 400 kHz
bandwidth.
The AD538's overall transfer function is V
O
= V
Y
(V
Z
/ V
X
)
m
.
Programming a particular function is via pin strapping. No
external components are required for one-quadrant (positive
input) multiplication and division. Two-quadrant (bipolar
numerator) division is possible with the use of external level
shifting and scaling resistors. The desired scale factor for both
multiplication and division can be set using the on-chip +2 V or
+10 V references, or controlled externally to provide simulta-
neous multiplication and division. Exponentiation with an m
value from 0.2 to 5 can be implemented with the addition of
one or two external resistors.
Direct log ratio computation is possible by using only the log
ratio and output sections of the chip. Access to the multiple
summing junctions adds further to the AD538's flexibility.
Finally, a wide power supply range of
4.5 V to
18 V allows
operation from standard
5 V,
12 V and
15 V supplies.
The AD538 is available in two accuracy grades (A and B) over
the industrial (25
C to +85
C) temperature range and one
grade (S) over the military (55
C to +125
C) temperature
range. The device is packaged in an 18-lead TO-118 hermetic
side-brazed ceramic DIP. A-grade chips are also available.
PRODUCT HIGHLIGHTS
1. Real-time analog multiplication, division and exponentiation.
2. High accuracy analog division with a wide input dynamic
range.
3. On-chip +2 V or +10 V scaling reference voltages.
4. Both voltage and current (summing) input modes.
5. Monolithic construction with lower cost and higher reliability
than hybrid and modular circuits.
2
REV. C
AD538SPECIFICATIONS
AD538AD
AD538BD
AD538SD
Parameters
Conditions
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Units
MULTIPLIER DIVIDER
PERFORMANCE
Nominal Transfer
Function
10 V
V
X
, V
Y
, V
Z
0
V
O
= V
Y
V
Z
V
X
m
V
O
= Vy
V
Z
V
X
m
V
O
= V
Y
V
Z
V
X
m
400
A
I
X
, I
Y,
I
Z
0
V
O
= 25 k
I
Y
I
Z
I
X
m
V
O
= 25 k
I
Y
I
Z
I
X
m
V
O
= 25 k
I
Y
I
Z
I
X
m
Total Error Terms
100 mV
V
X
10 V
0.5
1
0.25
0.5
0.5
1
% of Reading +
100:1 Input Range
1
100 mV
V
Y
10 V
200
500
100
250
200
500
V
100 mV
V
Z
10 V
V
Z
10 V
X
, m = 1.0
T
A
= T
MIN
to T
MAX
1
2
0.5
1
1.25
2.5
% of Reading +
450
750
350
500
750
1000
V
Wide Dynamic Range
2
10 mV
V
X
10 V
1
2
0.5
1
1
2
% of Reading +
1 mV
V
Y
10 V
200
500
100
250
200
500
V +
0 mV
V
Z
10 V
100
250
750
150
200
250
V
(V
Y
+ V
Z
)/V
X
V
Z
10 V
X
, m = 1.0
T
A
= T
MIN
to T
MAX
1
3
1
2
2
4
% of Reading +
450
750
350
500
750
1000
V +
450
750
350
500
750
1000
V
(V
Y
+ V
Z
)/V
X
Exponent (m) Range
T
A
= T
MIN
to T
MAX
0.2
5
0.2
5
0.2
5
OUTPUT
CHARACTERISTICS
Offset Voltage
V
Y
= 0, V
C
= 600 mV
200
500
100
250
200
500
V
T
A
= T
MIN
to T
MAX
450
750
350
500
750
1000
V
Output Voltage Swing
R
L
= 2 k
11
+11
11
+11
11
+11
V
Output Current
5
10
5
10
5
10
mA
FREQUENCY RESPONSE
Slew Rate
1.4
1.4
1.4
V/
s
Small Signal Bandwidth
100 mV
10 V
Y
, V
Z
,
400
400
400
kHz
V
X
10 V
VOLTAGE REFERENCE
Accuracy
V
REF
= 10 V or 2 V
25
50
15
25
25
50
mV
Additional Error
T
A
= T
MIN
or T
MAX
20
30
20
30
30
50
mV
Output Current
V
REF
= 10 V to 2 V
1
2.5
1
2.5
1
2.5
mA
Power Supply Rejection
+2 V = V
REF
4.5 V
V
S
18 V
300
600
300
600
300
600
V/V
+10 V = V
REF
13 V
V
S
18 V
200
500
200
500
200
500
V/V
POWER SUPPLY
Rated
R
L
= 2 k
15
15
15
V
Operating Range
3
4.5
18
4.5
18
4.5
18
V
PSRR
4.5 V < V
S
<
18 V
0.5
0.1
0.05
0.1
0.5
0.1
%/V
V
X
= V
Y
= V
Z
= 1 V
V
OUT
= 1 V
Quiescent Current
4.5
7
4.5
7
4.5
7
mA
TEMPERATURE RANGE
Rated
25
+85
25
+85
55
+125
C
Storage
65
+150
65
+150
65
+150
C
PACKAGE OPTIONS
Ceramic (D-18)
AD538AD
AD538BD
AD538SD
AD538SD/883B
Chips
AD538ACHIPS
NOTES
1
Over the 100 mV to 10 V operating range total error is the sum of a percent of reading term and an output offset. With this input dynamic range the input offset
contribution to total error is negligible compared to the percent of reading error. Thus, it is specified indirectly as a part of the percent of reading error.
2
The most accurate representation of total error with low level inputs is the summation of a percent of reading term, an output offset and an input offset multiplied by
the incremental gain (V
Y
+ V
Z
) V
X
.
3
When using supplies below
13 V, the 10 V reference pin must be connected to the 2 V pin in order for the AD538 to operate correctly.
Specifications subject to change without notice.
Specifications shown in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min
and max specifications are guaranteed, although only those shown in boldface are tested on all production units.
(V
S
= 15 V, T
A
= +25 C unless otherwise noted)
AD538
3
REV. C
RE-EXAMINATION OF MULTIPLIER/DIVIDER
ACCURACY
Traditionally, the "accuracy" (actually the errors) of analog
multipliers and dividers have been specified in terms of percent
of full scale. Thus specified, a 1% multiplier error with a 10 V
full-scale output would mean a worst case error of +100 mV at
"any" level within its designated output range. While this type
of error specification is easy to test evaluate, and interpret, it can
leave the user guessing as to how useful the multiplier actually is
at low output levels, those approaching the specified error limit
(in this case) 100 mV.
The AD538's error sources do not follow the percent of full-
scale approach to specification, thus it more optimally fits the
needs of the very wide dynamic range applications for which it is
best suited. Rather than as a percent of full scale, the AD538's
error as a multiplier or divider for a 100:1 (100 mV to 10 V)
input range is specified as the sum of two error components: a
percent of reading (ideal output) term plus a fixed output offset.
Following this format the AD538AD, operating as a multiplier
or divider with inputs down to 100 mV, has a maximum error of
1% of reading
500
V. Some sample total error calculations
for both grades over the 100:1 input range are illustrated in the
chart below. This error specification format is a familiar one to
designers and users of digital voltmeters where error is specified
as a percent of reading
a certain number of digits on the meter
readout.
For operation as a multiplier or divider over a wider dynamic
range (>100:1), the AD538 has a more detailed error specifica-
tion that is the sum of three components: a percent of reading
term, an output offset term and an input offset term for the
V
Y
/V
X
log ratio section. A sample application of this specifica-
tion, taken from Table I, for the AD538AD with V
Y
= 1 V, V
Z
=
100 mV and V
X
= 10 mV would yield a maximum error of
2.0% of reading
500
V
(1 V + 100 mV)/10 mV
250
V
or
2.0% of reading
500
V
27.5 mV. This example illus-
trates that with very low level inputs the AD538's incremental
gain (V
Y
+ V
Z
)/V
X
has increased to make the input offset contri-
bution to error substantial.
Table I. Sample Error Calculation Chart (Worst Case)
V
Y
V
Z
V
X
Ideal
Total Offset
% of Reading
Total Error
Total Error Summation
Input
Input
Input
Output
Error Term
Error Term
Summation
as a % of the Ideal
(in V)
(in V)
(in V)
(in V)
(in mV)
(in mV)
(in mV)
Output
100:1
10
10
10
10
0.5
(AD)
100 (AD)
100.5 (AD)
1.0
(AD)
INPUT
0.25
(BD)
50
(BD)
50.25 (BD)
0.5
(BD)
RANGE
Total Error =
10
0.1
0.1
10
0.5
(AD)
100 (AD)
100.5 (AD)
1.0
(AD)
% rdg
0.25
(BD)
50
(BD)
50.25 (BD)
0.5
(BD)
Output V
OS
1
1
1
1
0.5
(AD)
10
(AD)
10.5
(AD)
1.05 (AD)
0.25
(BD)
5
(BD)
5.25
(BD)
0.5
(BD)
0.1
0.1
0.1
0.1
0.5
(AD)
1
(AD)
1.5
(AD)
1.5
(AD)
0.25
(BD)
0.5 (BD)
0.75
(BD)
0.75 (BD)
WIDE
1
0.10
0.01
10
28
(AD)
200 (AD)
228
(AD)
2.28 (AD)
DYNAMIC
16.75 (BD)
100 (BD)
116.75 (BD)
1.17 (BD)
RANGE
Total Error =
10
0.05
2
0.25
1.76
(AD)
5
(AD)
6.76
(AD)
2.7
(AD)
% rdg
1
(BD)
2.5 (BD)
3.5
(BD)
1.4
(BD)
Output V
OS
Input V
OS
5
0.01
0.01
5
125.75 (AD)
100 (AD)
225.75 (AD)
4.52 (AD)
(V
Y
+ V
Z
)/V
X
75.4
(BD)
50
(BD)
125.4 (BD)
2.51 (BD)
10
0.01
0.1
1
25.53 (AD)
20
(AD)
45.53 (AD)
4.55 (AD)
15.27 (BD)
10
(BD)
25.27 (BD)
2.53 (BD)
AD538
4
REV. C
ORDERING GUIDE
Temperature
Package
Package
Model
Range
Description
Option
AD538AD
25
C to +85
C
Side-Brazed Ceramic DIP
D-18
AD538BD
25
C to +85
C
Side-Brazed Ceramic DIP
D-18
AD538ACHIPS
25
C to +85
C
Chips
AD538SD
55
C to +125
C
Side-Brazed Ceramic DIP
D-18
AD538SD/883B
55
C to +125
C
Side-Brazed Ceramic DIP
D-18
ABSOLUTE MAXIMUM RATINGS
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18 V
Internal Power Dissipation . . . . . . . . . . . . . . . . . . . . 250 mW
Output Short Circuit-to-Ground . . . . . . . . . . . . . . . Indefinite
Input Voltages V
X
, V
Y
, V
Z
. . . . . . . . . . . . . (+V
S
1 V), 1 V
Input Currents I
X
, I
Y
, I
Z
, I
O
. . . . . . . . . . . . . . . . . . . . . . 1 mA
Operating Temperature Range . . . . . . . . . . . 25
C to +85
C
Storage Temperature Range . . . . . . . . . . . . 65
C to +150
C
Lead Temperature, Storage . . . . . . . . . . . . . . 60 sec, +300
C
Thermal Resistance
JC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
C/W
JA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
C/W
PIN CONFIGURATION
1
2
18
17
5
6
7
14
13
12
3
4
16
15
8
11
9
10
I
Z
V
Z
A
D
+2V
+V
S
V
S
PWR GND
C
B
+10V
I
X
V
O
I
Y
I
V
Y
SIGNAL GND
V
X
AD538
TOP VIEW
(Not to Scale)
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD538 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
AD538
5
REV. C
TOTAL % OF READING ERROR
TEMPERATURE C
55 40
20
0
20
40
60
80
100
125
5.0
4.0
3.0
2.0
1.0
0
1000
800
600
400
200
0
OFFSET
% OF READING
OUTPUT STAGE OFFSET
V
Figure 1. Multiplier Error vs. Temperature
(100 mV < V
X
, V
Y
, V
Z
10 V)
TEMPERATURE C
TOTAL % OF READING ERROR
OUTPUT STAGE OFFSET
V
55 40
20
0
20
40
60
80
100
125
5.0
4.0
3.0
2.0
1.0
0
1000
800
600
400
200
0
OFFSET
% OF READING
Figure 2. Divider Error vs. Temperature
(100 mV < V
X
, V
Y
, V
Z
10 V)
INPUT FREQUENCY Hz
1000
100
100
10
1
1k
10k
100k
1M
V
X
= 10V
V
Y
= 0V
V
Z
= 5V +5V SIN t VOLTS
V
O
IN mV PEAK-TO-PEAK
Figure 3. V
Z
Feedthrough vs. Frequency
Typical Performance Characteristics
DENOMINATOR VOLTAGE, V
X
V dc
1M
0.01
100k
10k
0.1
1
10
400k
40k
V
Y
= 10V dc
V
Z
= V
X
+0.05 V
X
SIN t
SMALL SIGNAL BANDWITH Hz
Figure 4. Small Signal Bandwidth vs. Denominator
Voltage (One-Quadrant Mult/Div)
TOTAL % OF READING ERROR
OUTPUT STAGE OFFSET
V
TEMPERATURE C
55 40
20
0
20
40
60
80
100
125
5.0
4.0
3.0
2.0
1.0
0
1000
800
600
400
200
0
6.0
% OF READING
OFFSET
1200
Figure 5. Multiplier Error vs. Temperature
(10 mV < V
X
, V
Y
, V
Z
100 mV)
TEMPERATURE C
55 40
20
0
20
40
60
80
100
125
5.0
4.0
3.0
2.0
1.0
0
1000
800
600
400
200
0
% OF READING
OFFSET
TOTAL % OF READING ERROR
OUTPUT STAGE OFFSET
V
Figure 6. Divider Error vs. Temperature
(10 mV < V
X
, V
Y
, V
Z
100 mV)
AD538
6
REV. C
25k
25k
LOG
RATIO
100
25k
25k
ANTILOG
LOG
OUTPUT
100
AD538
INTERNAL
VOLTAGE
REFERENCE
I
V
O
I
Z
V
Z
B
+10V
V
S
+V
S
+2V
I
Y
A
D
I
X
V
X
C
PWR
GND
SIGNAL
GND
V
Y
1
18
17
16
15
14
13
12
11
10
2
3
4
5
6
7
8
9
Figure 9. Functional Block Diagram
FUNCTIONAL DESCRIPTION
As shown in Figures 9 and 10, the V
Z
and V
X
inputs connect
directly to the AD538's input log ratio amplifiers. This subsec-
tion provides an output voltage proportional to the natural log
of input voltage V
Z
, minus the natural log of input voltage V
X
.
The output of the log ratio subsection at B can be expressed by
the transfer function:
V
B
=
kT
q
ln
V
Z
V
X
where k = 1.3806
10
23
J/K,
q = 1.60219
10
19
C,
T is in Kelvins.
The log ratio configuration may be used alone, if correctly tem-
perature compensated and scaled to the desired output level
(see Applications section).
Under normal operation, the log-ratio output will be directly
connected to a second functional block at input C, the antilog
subsection. This section performs the antilog according to the
transfer function:
V
O
=
V
Y
e
V
C
q
kT
As with the log-ratio circuit included in the AD538, the user
may use the antilog subsection by itself. When both subsections
are combined, the output at B is tied to C, the transfer function
of the AD538 computational unit is:
V
O
=
V
Y
e
kT
q
q
kT
ln
V
Z
V
X
; V
B
=
V
C
which reduces to:
V
V
V
V
O
Y
Z
X
=
Finally, by increasing the gain, or attenuating the output of the
log ratio subsection via resistor programming, it is possible to
raise the quantity V
Z
/V
X
to the m
th
power. Without external
programming, m is unity. Thus the overall AD538 transfer
function equals:
V
O
=
V
Y
V
Z
V
X
m
where 0.2 < m < 5.
When the AD538 is used as an analog divider, the V
Y
input can
be used to multiply the ratio V
Z
/ V
X
by a convenient scale factor.
The actual multiplication by the V
Y
input signal is accomplished
by adding the log of the V
Y
input signal to the signal at C, which
is already in the log domain.
INPUT FREQUENCY Hz
150
100
10
1.0
0.1
1k
10k
100k
1M
100
V
X
= 10V
V
Y
= 5V +5V SIN t VOLTS
V
Z
= 0V
V
O
IN mV PEAK-TO-PEAK
Figure 7. V
Y
Feedthrough vs. Frequency
DC OUTPUT VOLTAGE Volts
100
0.01
VOLTAGE NOISE, e
n
V
Hz
10
1
0.10
0.01
0.1
1
10
FOR THE FREQUENCY RANGE OF 10Hz
TO 100kHz THE TOTAL RMS OUTPUT
NOISE, e
o
, FOR A GIVEN BANDWIDTH
Bw, IS CALCULATED e
o
= e
n
Bw
V
X
= 10V
V
X
= 0.01V
Figure 8. 1 kHz Output Noise Spectral Density vs. DC Output
Voltage
AD538
7
REV. C
STABILITY PRECAUTIONS
At higher frequencies, the multistaged signal path of the AD538,
as illustrated in Figure 10, can result in large phase shifts. If a
condition of high incremental gain exists along that path (e.g.,
V
O
= V
Y
V
Z
/ V
X
= 10 V
10 mV/10 mV = 10 V so that
V
O
/
V
X
= 1000), then small amounts of capacitive feedback
from V
O
to the current inputs I
Z
or I
X
can result in instability.
Appropriate care should be exercised in board layout to pre-
vent capacitive feedback mechanisms under these conditions.
LOG
e
I
Y
V
Y
Ln Y
LOG
e
I
Z
V
Z
Ln Z
LOG
e
I
X
V
X
Ln X
0.2 M 5
BUFFER
+
+
+
Ln Z Ln X
M(Ln Z Ln X)
M(Ln Z Ln X) +Ln Y
V
O
= V
Y
V
Z
V
X
M
ANTILOG
e
Figure 10. Model Circuit
USING THE VOLTAGE REFERENCES
A stable bandgap voltage reference for scaling is included in the
AD538. It is laser-trimmed to provide a selectable voltage out-
put of +10 V buffered (Pin 4), +2 V unbuffered (Pin 5) or any
voltages between +2 V and +10.2 V buffered as shown in Figure
11. The output impedance at Pin 5 is approximately 5 k
. Note
that any loading of this pin will produce an error in the +10 V
reference voltage. External loads on the +2 V output should be
greater than 500 k
to maintain errors less than 1%.
25k
25k
LOG
RATIO
100
25k
25k
ANTILOG
LOG
OUTPUT
100
AD538
INTERNAL
VOLTAGE
REFERENCE
I
V
O
I
Z
V
Z
B
REF OUT
V
S
+V
S
+2V
I
Y
A
D
I
X
V
X
C
PWR
GND
SIGNAL
GND
V
Y
1
18
17
16
15
14
13
12
11
10
2
3
4
5
6
7
8
9
50k
11.5k
+2V TO +10.2V
BUFFERED
Figure 11. +2 V to +10.2 V Adjustable Reference
In situations not requiring both reference levels, the +2 V output
can be converted to a buffered output by tying Pins 4 and 5
together. If both references are required simultaneously, the
+10 V output should be used directly and the +2 V output
should be externally buffered.
ONE-QUADRANT MULTIPLICATION/DIVISION
Figure 12 shows how the AD538 may be easily configured as a
precision one-quadrant multiplier/divider. The transfer function
V
OUT
= V
Y
(V
Z
/V
X
) allows "three" independent input variables,
a calculation not available with a conventional multiplier. In
addition, the 1000:1 (i.e., 10 mV to 10 V) input dynamic range
of the AD538 greatly exceeds that of analog multipliers comput-
ing one-quadrant multiplication and division.
25k
25k
LOG
RATIO
100
25k
25k
ANTILOG
LOG
OUTPUT
100
AD538
INTERNAL
VOLTAGE
REFERENCE
I
V
O
I
Z
V
Z
B
+10V
+2V
I
Y
A
D
I
X
V
X
C
PWR
GND
SIGNAL
GND
V
Y
1
18
17
16
15
14
13
12
11
10
2
3
4
5
6
7
8
9
V
Z
INPUT
+15V
15V
OUTPUT
V
X
INPUT
V
Y
INPUT
IN4148
V
OUT
= V
Y
(
)
V
Z
V
X
Figure 12. One-Quadrant Combination Multiplier/Divider
By simply connecting the input V
X
(Pin 15) to the +10 V refer-
ence (Pin 4), and tying the log-ratio output at B to the antilog
input at C, the AD538 can be configured as a one-quadrant
analog multiplier with 10-volt scaling. If 2-volt scaling is desired,
V
X
can be tied to the +2 V reference.
When the input V
X
is tied to the +10 V reference terminal, the
multiplier transfer function becomes:
V
O
=
V
Y
V
Z
10 V
As a multiplier, this circuit provides a typical bandwidth of
400 kHz with values of V
X
, V
Y
or V
Z
varying over a 100:1 range
(i.e., 100 mV to 10 V). The maximum error with a 100 mV to
10 V range for the two input variables will typically be +0.5% of
reading. Using the optional Z offset trim scheme, as shown in
Figure 13, this error can be reduced to +0.25% of reading.
By using the +10 V reference as the V
Y
input, the circuit of
Figure 12 is configured as a one-quadrant divider with a fixed
scale factor. As with the one-quadrant multiplier, the inputs
accept only single (positive) polarity signals. The output of the
one-quadrant divider with a +10 V scale factor is:
V
O
=
10V
V
Z
V
X
The typical bandwidth of this circuit is 370 kHz with 1 V to
10 V denominator input levels. At lower amplitudes, the band-
width gradually decreases to approximately 200 kHz at the
2 mV input level.
AD538
8
REV. C
LOG RATIO OPERATION
Figure 14 shows the AD538 configured for computing the log of
the ratio of two input voltages (or currents). The output signal
from B is connected to the summing junction of the output ampli-
fier via two series resistors. The 90.9
metal film resistor effec-
tively degrades the temperature coefficient of the
3500 ppm/
C
resistor to produce a 1.09 k
+3300 ppm/
C equivalent value.
In this configuration, the V
Y
input must be tied to some voltage
less than zero (1.2 V in this case) removing this input from the
transfer function.
The 5 k
potentiometer controls the circuit's scale factor ad-
justment providing a +1 V per decade adjustment. The output
offset potentiometer should be set to provide a zero output with
V
X
= V
Z
= 1 V. The input V
Z
adjustment should be set for an
output of 3 V with V
Z
= l mV and V
X
= 1 V.
25k
25k
LOG
RATIO
100
25k
25k
ANTILOG
LOG
OUTPUT
100
AD538
INTERNAL
VOLTAGE
REFERENCE
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
I
V
O
I
Z
V
Z
B
+10V
+2V
I
Y
A
D
I
X
V
X
C
PWR
GND
SIGNAL
GND
V
Y
+15V
15V
IN4148
V
O
= 1V LOG
10
( )
V
Z
V
X
OUTPUT
2k
1%
5k
SCALE
FACTOR
ADJUST
AD589
1.2V
V
S
OPTIONAL
INPUT V
OS
ADJUSTMENT
V
X
INPUT
1M
10M
90.9
1%
1k
+3500
ppm/ C
+V
S
V
S
10M
10k
OPTIONAL
OUTPUT V
OS
ADJUSTMENT
68k
5%
48.7
Figure 14. Log Ratio Circuit
The log ratio circuit shown achieves
0.5% accuracy in the log
domain for input voltages within three decades of input range:
10 mV to 10 V. This error is not defined as a percent of full-
scale output, but as a percent of input. For example, using a
1 V/decade scale factor, a 1% error in the positive direction at
the INPUT of the log ratio amplifier translates into a 4.3 mV
deviation from the ideal OUTPUT (i.e., 1 V
log
10
(1.01) =
4.3214 mV). An input error 1% in the negative direction is
slightly different, giving an output deviation of 4.3648 mV.
TWO-QUADRANT DIVISION
The two-quadrant linear divider circuit illustrated in Figure 13
uses the same basic connections as the one-quadrant version.
However, in this circuit the numerator has been offset in the
positive direction by adding the denominator input voltage to it.
The offsetting scheme changes the divider's transfer function
from:
V
O
=
10V
V
Z
V
X
to:
V
O
=
10V
V
Z
+
AV
X
(
)
V
X
=
10 V 1 A
+
V
Z
V
X
=
10 A
+
10 V
V
Z
V
X
where
A
=
35 k
25 k
As long as the magnitude of the denominator input is equal to
or greater than the magnitude of the numerator input, the cir-
cuit will accept bipolar numerator voltages. However, under the
conditions of a 0 V numerator input, the output would incor-
rectly equal +14 V. The offset can be removed by connecting
the +10 V reference through resistors R1 and R2 to the output
section's summing node I at Pin 9 thus providing a gain of 1.4
at the center of the trimming potentiometer. The pot R2 adjusts
out or corrects this offset, leaving the desired transfer function
of 10 V (V
Z
/ V
X
).
25k
25k
LOG
RATIO
100
25k
25k
ANTILOG
LOG
OUTPUT
100
AD538
INTERNAL
VOLTAGE
REFERENCE
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
I
V
O
I
Z
V
Z
B
+10V
+2V
I
Y
A
D
I
X
V
X
C
PWR
GND
SIGNAL
GND
V
Y
+15V
15V
IN4148
V
OUT
= 10
(
)
V
Z
V
X
FOR
V
X
V
Z
OUTPUT
R1
12.4k
R2
10k
ZERO
ADJUST
AD589
1M
V
OS
ADJ
68k
5%
3.9M
35k
NUMERATOR
V
Z
10M
1.2V
V
S
OPTIONAL
Z OFFSET TRIM
DENOMINATOR
V
X
35k
Figure 13. Two-Quadrant Division with 10 V Scaling
AD538
9
REV. C
ANALOG COMPUTATION OF POWERS AND ROOTS
It is often necessary to raise the quotient of two input signals to
a power or take a root. This could be squaring, cubing, square-
rooting or exponentiation to some noninteger power. Examples
include power series generation. With the AD538, only one or
two external resistors are required to set ANY desired power,
over the range of 0.2 to 5. Raising the basic quantity V
Z
/V
X
to a
power greater than one requires that the gain of the AD538's log
ratio subtractor be increased, via an external resistor between
pins A and D. Similarly, a voltage divider that attenuates the log
ratio output between points B and C will program the power to
a value less than one.
3
12
18
17
2
10
15
8
V
Y
( )
m
V
Z
V
REF
R
A
V
O
V
Z
V
Y
V
REF
V
X
B
C
A
D
R
A
= 196
M 1
R
B
= R
C
200
POWERS
m R
A
2 196
3 97.6
4 64.9
5 48.7
3
12
2
10
15
8
V
Y
( )
m
V
Z
V
REF
V
O
V
Z
V
Y
V
REF
V
X
B
C
R
B
R
C
ROOTS
m R
B
R
C
1/2 100 100
1/3 100 49.9
1/4 150 49.9
1/5 162 40.2
R
B
R
C
= 1
1
M
Figure 15. Basic Configurations and Transfer Functions
for the AD538
+15V
15V
D1
IN4148
V
OUT
= 1V
V
IN
1V
*
*
R
C
100
R
B
100
V
OUT
7
1
8
6
4
2
3
+V
S
IN4148
IN4148
AD OP-07
OR AD611
(V
OS
TAP
TO V
S
)
V
S
20k
5k
20k
OPTIONAL
ABSOLUTE VALUE SECTION
10k
V
IN
+2V
1k
1k
100
SCALE FACTOR
TRIM
RATIO MATCH 1% METAL FILM
RESISTORS FOR BEST ACCURACY
*
25k
25k
LOG
RATIO
100
25k
25k
ANTILOG
LOG
OUTPUT
100
AD538
INTERNAL
VOLTAGE
REFERENCE
I
V
O
I
Z
V
Z
B
+10V
I
Y
A
D
I
X
V
X
C
PWR
GND
SIGNAL
GND
V
Y
1
18
17
16
15
14
13
12
11
10
2
3
4
5
6
7
8
9
+2V
V
OS
20k
Figure 16. Square Root Circuit
SQUARE ROOT OPERATION
The explicit square root circuit of Figure 16 illustrates a precise
method for performing a real-time square root computation. For
added flexibility and accuracy, this circuit has a scale factor
adjustment.
The actual square rooting operation is performed in this circuit
by raising the quantity V
Z
/ V
X
to the one-half power via the
resistor divider network consisting of resistors R
B
and R
C
. For
maximum linearity, the two resistors should be 1% (or better)
ratio-matched metal film types.
One volt scaling is achieved by dividing-down the 2 V reference
and applying approximately 1 V to both the V
Y
and V
X
inputs.
In this circuit, the V
X
input is intentionally set low, to about
0.95 V, so that the V
Y
input can be adjusted high, permitting a
5% scale factor trim. Using this trim scheme, the output volt-
age will be within
3 mV
0.2% of the ideal value over a 10 V
to 1 mV input range (80 dB). For a decreased input dynamic
range of 10 mV to 10 V (60 dB) the error is even less; here the
output will be within
2 mV
0.2% of the ideal value. The
bandwidth of the AD538 square root circuit is approximately
280 kHz with a 1 V p-p sine wave with a +2 V dc offset.
This basic circuit may also be used to compute the cube, fourth
or fifth roots of an input waveform. All that is required for a
given root is that the correct ratio of resistors, R
C
and R
B
, be
selected such that their sum is between 150
and 200
.
The optional absolute value circuit shown preceding the AD538
allows the use of bipolar input voltages. Only one op amp is
required for the absolute value function because the I
Z
input of
the AD538 functions as a summing junction. If it is necessary to
preserve the sign of the input voltage, the polarity of the op amp
output may be sensed and used after the computation to switch
the sign bit of a D.V.M. chip.
AD538
10
REV. C
TRANSDUCER LINEARIZATION
Many electronic transducers used in scientific, commercial or
industrial equipment monitor the physical properties of a device
and/or its environment. Sensing (and perhaps compensating for)
changes in pressure, temperature, moisture or other physical
phenomenon can be an expensive undertaking, particularly
where high accuracy and very low nonlinearity are important. In
conventional analog systems accuracy may be easily increased
by offset and scale factor trims, however, nonlinearity is usually
the absolute limitation of the sensing device.
With the ability to easily program a complex analog function,
the AD538 can effectively compensate for the nonlinearities of
an inexpensive transducer. The AD538 can be connected be-
tween the transducer preamplifier output and the next stage of
monitoring or transmitting circuitry. The recommended proce-
dure for linearizing a particular transducer is first to find the
closest function which best approximates the nonlinearity of the
device and then, to select the appropriate exponent resistor
value(s).
ARC-TANGENT APPROXIMATION
The circuit of Figure 17 is typical of those AD538 applications
where the quantity V
Z
/V
X
is raised to powers greater than one.
In an approximate arc-tangent function, the AD538 will accu-
rately compute the angle that is defined by X and Y displace-
ments represented by input voltages V
X
and V
Z
. With accuracy
to within one degree (for input voltages between 100
V and
10 volts), the AD538 arc-tangent circuit is more precise than
conventional analog circuits and is faster than most digital tech-
niques. For a direct arc-tangent computation that requires fewer
external components, refer to the AD639 data sheet. The circuit
shown is set up for the transfer function:
V
V
V
V
V
REF
Z
X
=
-
(
) ( )
( )
1 21
.
where:
=
Tan
-
1
Z
X
The (V
REF
V
) function is implemented in this circuit by
adding together the output, V
, and an externally applied refer-
ence voltage, V
REF
, via an external AD547 op amp. The 1
F
capacitor connected around the AD547's 100 k
feedback
resistor frequency compensates the loop (formed by the ampli-
fier between V
and V
Y
).
25k
25k
LOG
RATIO
100
25k
25k
ANTILOG
LOG
OUTPUT
100
AD538
INTERNAL
VOLTAGE
REFERENCE
V = [V
REF
V ]
(
)
= TAN
1
( )
V
Z
V
X
Z
X
1.21
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
I
V
O
I
Z
V
Z
B
+10V
+2V
I
Y
A
D
I
X
V
X
C
PWR
GND
SIGNAL
GND
V
Y
V
S
IN4148
RATIO MATCH 1% METAL
FILM RESISTORS FOR BEST
ACCURACY
*
+V
S
1 F
1 F
+15V
15V
V
V
Z
AD547JH
R2
*
100k
+15V
15V
0.1 F
100k
1 F
118k
R1
*
100k
10k
FULL-SCALE
ADJUST
R
A
931 , 1%
V
X
Figure 17. The Arc-Tangent Function
The V
B
/V
A
quantity is calculated in the same manner as in the
one-quadrant divider circuit, except that the resulting quotient
is raised to the 1.21 power. Resistor R
A
(nominally 931
) sets
the power or m factor.
For the highest arc-tangent accuracy the external resistors R1
and R2 should be ratio matched; however, the offset trim
scheme shown in other circuits is not required since nonlinearity
effects are the predominant source of error. Also note that insta-
bility will occur as the output approaches 90
because, by defini-
tion, the arc-tangent function is infinite and therefore, the AD538's
gain will be extremely high.
AD538
11
REV. C
Side-Brazed Ceramic DIP
(D-18)
18
1
9
10
0.30 (7.62)
0.28 (7.12)
PIN 1
SEATING
PLANE
0.02 (0.508)
0.015 (0.381)
0.17 (4.32)
MAX
0.175 (4.45)
0.125 (3.18)
0.06 (1.53)
0.04 (1.02)
0.91 (23.12)
0.89 (22.61)
0.105 (2.67)
0.095 (2.42)
0.306 (7.78)
0.294 (7.47)
0.012 (0.305)
0.008 (0.203)
0.12 (3.05)
0.06 (1.53)
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
PRINTED IN U.S.A.
C959d012/99 (rev. C)
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