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Dual 12-Bit, High Bandwidth, Multiplying DAC
with 4-Quadrant Resistors and Serial Interface
AD5415
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
2004 Analog Devices, Inc. All rights reserved.
FEATURES
On-chip 4-quadrant resistors allow flexible output ranges
10 MHz multiplying bandwidth
50 MHz serial interface
2.5 V to 5.5 V supply operation
10 V reference input
Extended temperature range: -40C to +125C
24-lead TSSOP package
Guaranteed monotonic
Power-on reset
Daisy-chain mode
Readback function
0.5 A typical current consumption
APPLICATIONS
Portable battery-powered applications
Waveform generators
Analog processing
Instrumentation applications
Programmable amplifiers and attenuators
Digitally controlled calibration
Programmable filters and oscillators
Composite video
Ultrasound
Gain, offset, and voltage trimming
GENERAL DESCRIPTION
The AD5415
1
is a CMOS 12-bit, dual-channel, current output
digital-to-analog converter. This device operates from a 2.5 V to
5.5 V power supply, making it suited to battery-powered appli-
cations as well as many other applications.
The applied external reference input voltage (V
REF
) determines
the full-scale output current. An integrated feedback resistor
(R
FB
) provides temperature tracking and full-scale voltage
output when combined with an external current-to-voltage
precision amplifier. In addition, this device contains all the
4-quadrant resistors necessary for bipolar operation and other
configuration modes.
This DAC utilizes a double-buffered 3-wire serial interface that
is compatible with SPI, QSPITM, MICROWIRETM, and most DSP
interface standards. In addition, a serial data out pin (SDO)
allows for daisy-chaining when multiple packages are used.
Data readback allows the user to read the contents of the DAC
register via the SDO pin. On power-up, the internal shift
register and latches are filled with zeros, and the DAC outputs
are at zero scale. As a result of manufacture on a CMOS submi-
cron process, this part offers excellent 4-quadrant multiplication
characteristics, with large-signal multiplying bandwidths of
10 MHz.
1
US Patent Number 5,689,257.
FUNCTIONAL BLOCK DIAGRAM
POWER-ON
RESET
INPUT
REGISTER
DAC
REGISTER
12-BIT
R-2R DAC B
INPUT
REGISTER
DAC
REGISTER
12-BIT
R-2R DAC A
SHIFT
REGISTER
V
DD
SCLK
SDIN
GND
SDO
SYNC
LDAC
R3
2R
R2
2R
R1
2R
R
FB
2R
R1
2R
R
FB
2R
R3
2R
R2
2R
AD5415
R3A
R2_3A
R2A
V
REF
A R1A
R3B
R2_3B
R2B
V
REF
B R1B
R
FB
A
I
OUT
1A
I
OUT
2A
I
OUT
1B
I
OUT
2B
R
FB
B
CLR
04461-0-001
Figure 1.
AD5415
Rev. 0 | Page 2 of 28
TABLE OF CONTENTS
Specifications..................................................................................... 3
Timing Characteristics ................................................................ 5
Absolute Maximum Ratings............................................................ 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Terminology ...................................................................................... 9
Typical Performance Characteristics ........................................... 10
General Description ....................................................................... 15
DAC Section................................................................................ 15
Unipolar Mode............................................................................ 15
Bipolar Operation....................................................................... 16
Stability ........................................................................................ 16
Single-Supply Applications............................................................ 17
Voltage Switching Mode of Operation .................................... 17
Positive Output Voltage ............................................................. 17
Adding Gain................................................................................ 17
Divider or Programmable Gain Element ................................ 17
Reference Selection .................................................................... 18
Amplifier Selection .................................................................... 18
Serial Interface ................................................................................ 20
Low Power Serial Interface ....................................................... 20
Control Register ......................................................................... 20
SYNC Function........................................................................... 21
Daisy-Chain Mode ..................................................................... 21
Standalone Mode........................................................................ 21
LDAC Function .......................................................................... 21
Microprocessor Interfacing....................................................... 22
PCB Layout and Power Supply Decoupling................................ 24
Evaluation Board for the DAC ................................................. 24
Power Supplies for the Evaluation Board................................ 24
Outline Dimensions ....................................................................... 28
Ordering Guide .......................................................................... 28
REVISION HISTORY
7/04--Revision 0: Initial Version
AD5415
Rev. 0 | Page 3 of 28
SPECIFICATIONS
Temperature range for Y Version: -40C to +125C.
V
DD
= 2.5 V to 5.5 V, V
REF
= 10 V, I
OUT
2A, I
OUT
2B = 0 V; all specifications T
MIN
to T
MAX
, unless otherwise noted.
DC performance measured with OP1177, ac performance with AD8038, unless otherwise noted.
Table 1.
Parameter
Min
Typ
Max
Unit
Conditions
STATIC PERFORMANCE
Resolution
12
Bits
Relative Accuracy
1
LSB
Differential Nonlinearity
-1/+2
LSB
Guaranteed monotonic
Gain Error
25
mV
Gain Error Temperature Coefficient
1
5
ppm FSR/C
Bipolar Zero Code Error
25
mV
Output Leakage Current
1
nA
Data = 0x0000, T
A
= 25C, I
OUT
1
10
nA
Data = 0x0000, I
OUT
1
REFERENCE INPUT
1
Typical Resistor TC = -50 ppm/C
Reference Input Range
10
V
V
REF
A, V
REF
B Input Resistance
8
10
12
k
DAC input resistance
V
REF
A to V
REF
B Input Resistance
Mismatch
1.6
2.5
%
Typ = 25C, Max = 125C
R
1
, R
FB
Resistance
16
20
24
k
R
2
, R
3
Resistance
16
20
24
k
R
2
to R
3
Resistance Mismatch
0.06
0.18
%
Typ = 25C, Max = 125C
DIGITAL INPUTS/OUTPUT
1
Input High Voltage, V
IH
1.7
V
V
DD
= 2.5 V to 5.5 V
Input Low Voltage, V
IL
0.8
V
V
DD
= 2.7 V to 5.5 V
0.7
V
V
DD
= 2.5 V to 2.7 V
Input Leakage Current, I
IL
1
A
Input Capacitance
10
pF
V
DD
= 4.5 V to 5.5 V
Output Low Voltage, V
OL
0.4
V
I
SINK
= 200 A
Output High Voltage, V
OH
V
DD
- 1
V
I
SOURCE
= 200 A
V
DD
= 2.5 V to 3.6 V
Output Low Voltage, V
OL
0.4
V
I
SINK
= 200 A
Output High Voltage, V
OH
V
DD
- 0.5
V
I
SOURCE
= 200 A
DYNAMIC PERFORMANCE
1
Reference Multiplying Bandwidth
10
MHz
V
REF
= 5 V p-p, DAC loaded all 1s
Output Voltage Settling Time
90
160
ns
Measured to 4 mV of FS; R
LOAD
= 100 , C
LOAD
=
0s, 15 pF, DAC latch alternately loaded with 0s
and 1s
Digital Delay
20
40
ns
Digital-to-Analog Glitch Impulse
3
nV-s
1 LSB change around major carry, V
REF
= 0 V
Multiplying Feedthrough Error
-75
dB
DAC latch loaded with all 0s, reference = 10 kHz
Output Capacitance
2
pF
DAC latches loaded with all 0s
4
pF
DAC latches loaded with all 1s
Digital Feedthrough
5
nV-s
Feedthrough to DAC output with CS high and
alternate loading of all 0s and all 1s
Total Harmonic Distortion
-75
dB
V
REF
= 5 V p-p, all 1s loaded, f = 1 kHz
-75
dB
V
REF
= 5 V, sine wave generated from digital code
Output Noise Spectral Density
25
nV/Hz
@ 1 kHz
AD5415
Rev. 0 | Page 4 of 28
Parameter
Min
Typ
Max
Unit
Conditions
SFDR Performance (Wideband)
Clock = 10 MHz
500 kHz f
OUT
55
dB
100 kHz f
OUT
63
dB
50 kHz f
OUT
65
dB
Clock = 25 MHz
500 kHz f
OUT
50
dB
100 kHz f
OUT
60
dB
50 kHz f
OUT
62
dB
SFDR Performance (Narrow-Band)
Clock = 10 MHz
500 kHz f
OUT
73
dB
100 kHz f
OUT
80
dB
50k Hz f
OUT
87
dB
Clock = 25 MHz
500 kHz f
OUT
70
dB
100 kHz f
OUT
75
dB
50k Hz f
OUT
80
dB
Intermodulation Distortion
Clock = 10 MHz
f
1
= 400 kHz, f
2
= 500 kHz
65
dB
f
1
= 40 kHz, f
2
= 50 kHz
72
dB
Clock = 25 MHz
f
1
= 400 kHz, f
2
= 500 kHz
51
dB
f
1
= 40 kHz, f
2
= 50 kHz
65
dB
POWER REQUIREMENTS
Power Supply Range
2.5
5.5
V
I
DD
10
A
Logic inputs = 0 V or V
DD
Power Supply Sensitivity
1
0.001
%/%
V
DD
= 5%
1
Guaranteed by design and characterization, not subject to production test.
AD5415
Rev. 0 | Page 5 of 28
TIMING CHARACTERISTICS
Temperature range for Y Version: -40C to +125C. See Figure 2 and Figure 3.
Guaranteed by design and characterization, not subject to production test.
All input signals are specified with tr = tf = 1 ns (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2.
V
DD
= 2.5 V to 5.5 V, V
REF
= 5 V, I
OUT
2 = 0 V. All specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 2.
Parameter
Limit at T
MIN
, T
MAX
Unit
Conditions/Comments
1
f
SCLK
50
MHz max
Maximum clock frequency
t
1
20
ns min
SCLK cycle time
t
2
8
ns min
SCLK high time
t
3
8
ns min
SCLK low time
t
4
13
ns min
SYNC falling edge to SCLK falling edge setup time
t
5
5
ns min
Data setup time
t
6
4
ns min
Data hold time
t
7
5
ns min
SYNC rising edge to SCLK falling edge
t
8
30
ns min
Minimum SYNC high time
t
9
0
ns min
SCLK falling edge to LDAC falling edge
t
10
12
ns min
LDAC pulse width
t
11
10
ns min
SCLK falling edge to LDAC rising edge
t
12
2
25
ns min
SCLK active edge to SDO valid, strong SDO driver
60
ns min
SCLK active edge to SDO valid, weak SDO driver
1
Falling or rising edge as determined by the control bits of serial word. Strong or weak SDO driver selected via the control register.
2
Daisy-chain and readback modes cannot operate at maximum clock frequency. SDO timing specifications measured with a load circuit, as shown in
.
Figure 4
t
1
t
2
t
3
t
7
t
8
t
4
t
5
t
6
t
9
t
10
t
11
DB15
DB0
SCLK
DIN
LDAC
1
LDAC
2
SYNC
NOTES
1
ASYNCHRONOUS LDAC UPDATE MODE
2
SYNCHRONOUS LDAC UPDATE MODE
ALTERNATIVELY, DATA CAN BE CLOCKED INTO INPUT SHIFT REGISTER ON RISING EDGE OF SCLK AS
DETERMINED BY CONTROL BITS. TIMING AS ABOVE, WITH SCLK INVERTED.
04461-0-002
Figure 2. Standalone Mode Timing Diagram
Document Outline
- FEATURES
- APPLICATIONS
- GENERAL DESCRIPTION
- FUNCTIONAL BLOCK DIAGRAM
-
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