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REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
a
AD5532B
*
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
Analog Devices, Inc., 2002
32-Channel, 14-Bit DAC with Precision
Infinite Sample-and-Hold Mode
FUNCTIONAL BLOCK DIAGRAM
SYNC / CS
WR
CAL
A4A0
SCLK
OFFSET_SEL
AD5532B
DV
CC
V
IN
D
IN
D
OUT
ADDRESS INPUT REGISTER
AV
CC
REF IN REF OUT
OFFS IN
INTERFACE
CONTROL
LOGIC
OFFS OUT
V
OUT
31
V
OUT
0
TRACK / RESET
BUSY
DAC GND
AGND
DGND
SER /
PAR
V
DD
V
SS
DAC
DAC
ADC
MUX
DAC
MODE
14-BIT
BUS
FEATURES
High Integration:
32-Channel DAC in 12 mm 12 mm CSPBGA
Guaranteed Monotonic to 14 Bits
Infinite Sample-and-Hold Capability to 0.018% Accuracy
Infinite Sample-and-Hold Total Unadjusted Error 2.5 mV
Adjustable Voltage Output Range
Readback Capability
DSP/Microcontroller Compatible Serial Interface
Output Impedance 0.5
Output Voltage Span 10 V
Temperature Range 40 C to +85 C
APPLICATIONS
Automatic Test Equipment
Optical Networks
Level Setting
Instrumentation
Industrial Control Systems
Data Acquisition
Low Cost I/O
GENERAL DESCRIPTION
The AD5532B is a 32-channel, voltage output, 14-bit DAC with
an additional precision infinite sample-and-hold mode. The
selected DAC register is written to via the 3-wire serial inter-
face and V
OUT
for this DAC is then updated to reflect the new
contents of the DAC register. DAC selection is accomplished via
address bits A0A4. The output voltage range is determined by
the offset voltage at the OFFS_IN pin and the gain of the
output amplifier. It is restricted to a range from V
SS
+ 2 V to
V
DD
2 V because of the headroom of the output amplifier.
The device is operated with AV
CC
= +5 V
5%, DV
CC
= +2.7 V
to +5.25 V, V
SS
= 4.75 V to 16.5 V, and V
DD
= +8 V to +16.5 V
and requires a stable 3 V reference on REF_IN as well as an
offset voltage on OFFS_IN.
PRODUCT HIGHLIGHTS
1. 32-channel, 14-bit DAC in one package, guaranteed
monotonic.
2. The AD5532B is available in a 74-lead CSPBGA with a body
size of 12 mm
12 mm.
3. In infinite sample-and-hold mode, a total unadjusted error of
2.5 mV is achieved by laser-trimming on-chip resistors.
*Protected by U.S. Patent No. 5,969,657; other patents pending.
REV. A
2
(V
DD
= +8 V to +16.5 V, V
SS
= 4.75 V to 16.5 V; AV
CC
= +4.75 V to +5.25 V;
DV
CC
= +2.7 V to +5.25 V; AGND = DGND = DAC_GND = 0 V; REF_IN = 3 V;
OFFS_IN = OV; Output Range from V
SS
+ 2 V to V
DD
2 V. All outputs unloaded. All specifications T
MIN
to T
MAX
, unless otherwise noted.)
AD5532BSPECIFICATIONS
AD5532B-1
Parameter
1
B Version
2
Unit
Conditions/ Comments
DAC DC PERFORMANCE
Resolution
14
Bits
Integral Nonlinearity (INL)
0.39
% of FSR max
0.15% typ
Differential Nonlinearity (DNL)
1
LSB max
0.5 LSB typ Monotonic
Offset
90/170/250
mV min/typ/max
See Figure 6.
Gain
3.52
typ
Full-Scale Error
1/+0.5
% of FSR max
ISHA DC PERFORMANCE
V
IN
to V
OUT
Nonlinearity
3
0.006
% typ
After Offset and Gain Adjustment
0.018
% max
Total Unadjusted Error (TUE)
2.5
mV typ
See TPC 6.
12
mV max
Offset Error
1
mV typ
10
mV max
Gain
3.51/3.52/3.53
min/typ/max
ISHA ANALOG INPUT (V
IN
)
Input Voltage Range
0 to 3
V
Nominal Input Range
Input Lower Dead Band
70
mV max
50 mV typ. Referred to V
IN
.
See Figure 7.
Input Upper Dead Band
40
mV max
12 mV typ. Referred to V
IN
.
See Figure 7.
Input Current
1
A max
100 nA typ. V
IN
acquired
on one channel.
Input Capacitance
4
20
pF typ
ANALOG INPUT (OFFS_IN)
Input Current
1
A max
100 nA typ
Input Voltage Range
0/4
V min/max
Output Range Restricted from
V
SS
+ 2 V to V
DD
2 V
VOLTAGE REFERENCE
REF_IN
Nominal Input Voltage
3.0
V typ
Input Voltage Range
4
2.85/3.15
V min/max
Input Current
1
A max
<1 nA typ
REF_OUT
Output Voltage
3
V typ
Output Impedance
4
280
k
typ
Reference Temperature Coefficient
4
60
ppm/
C typ
ANALOG OUTPUTS (V
OUT
031)
Output Temperature Coefficient
4, 5
10
ppm/
C typ
DC Output Impedance
4
0.5
typ
Output Range
V
SS
+ 2/V
DD
2
V min/max
100
A Output Load
Resistive Load
4, 6
5
k
min
Capacitive Load
4, 6
100
pF max
Short-Circuit Current
4
7
mA typ
DC Power-Supply Rejection Ratio
4
70
dB
V
DD
= +15 V
5%
70
dB
V
SS
=
15 V
5%
DC Crosstalk
4
250
V max
Outputs Loaded
ANALOG OUTPUT (OFFS_OUT)
Output Temperature Coefficient
4, 5
10
ppm/
C typ
DC Output Impedance
4
1.3
k
typ
Output Range
50 to REF_IN 12
mV typ
Output Current
10
A max
Source Current
Capacitive Load
100
pF max
REV. A
3
AD5532B
AD5532B-1
Parameter
1
B Version
2
Unit
Conditions/Comments
DIGITAL INPUTS
7
Input Current
10
A max
5 A typ
Input Low Voltage
0.8
V max
DV
CC
= 5 V
5%
0.4
V max
DV
CC
= 3 V
10%
Input High Voltage
2.4
V min
DV
CC
= 5 V
5%
2.0
V min
DV
CC
= 3 V
10%
Input Hysteresis (SCLK and
CS Only)
200
mV typ
Input Capacitance
10
pF max
DIGITAL OUTPUTS (
BUSY, D
OUT
)
7
Output Low Voltage, DV
CC
= 5 V
0.4
V max
Sinking 200
A
Output High Voltage, DV
CC
= 5 V
4.0
V min
Sourcing 200
A
Output Low Voltage, DV
CC
= 3 V
0.4
V max
Sinking 200
A
Output High Voltage, DV
CC
= 3 V
2.4
V min
Sourcing 200
A
High Impedance Leakage Current
1
A max
D
OUT
Only
High Impedance Output Capacitance
15
pF typ
D
OUT
Only
POWER REQUIREMENTS
Power Supply Voltages
V
DD
8/16.5
V min/max
V
SS
4.75/16.5
V min/max
AV
CC
4.75/5.25
V min/max
DV
CC
2.7/5.25
V min/max
Power Supply Currents
8
I
DD
15
mA max
10 mA typ. All channels full-scale.
I
SS
15
mA max
10 mA typ. All channels full-scale.
AICC
33
mA max
26 mA typ
DICC
1.5
mA max
1 mA typ
Power Dissipation
8
280
mW typ
V
DD
= +10 V, V
SS
= 5 V
NOTES
1
See Terminology section.
2
B Version: Industrial temperature range 40
C to +85C; typical at +25C.
3
Input range 100 mV to 2.96 V.
4
Guaranteed by design and characterization, not production tested.
5
AD780 as reference for the AD5532B.
6
Ensure that you do not exceed T
J
(max). See Absolute Maximum Ratings section.
7
Guaranteed by design and characterization, not production tested.
8
Output unloaded.
Specifications subject to change without notice.
REV. A
4
AD5532B-1
Parameter
1
B Version
2
Unit
Conditions/Comments
DAC AC CHARACTERISTICS
3
Output Voltage Settling Time
22
s max
500 pF, 5 k
Load Full-Scale Change
OFFS_IN Settling Time
10
s max
500 pF, 5 k
Load; 0 V to 3 V Step
Digital-to-Analog Glitch Impulse
1
nV-s
typ
1 LSB Change Around Major Carry
Digital Crosstalk
5
nV-s
typ
Analog Crosstalk
1
nV-s
typ
Digital Feedthrough
0.2
nV-s
typ
Output Noise Spectral Density @ 1 kHz
400
nV/
Hz typ
ISHA AC CHARACTERISTICS
Output Voltage Settling Time
3
3
s max
Outputs Unloaded
Acquisition Time
16
s max
AC Crosstalk
3
5
nV-s
typ
NOTES
1
See Terminology section.
2
B Version: Industrial temperature range 40
C to +85C; typical at +25C.
3
Guaranteed by design and characterization, not production tested.
Specifications subject to change
without notice.
TIMING CHARACTERISTICS
PARALLEL INTERFACE
Limit at T
MIN
, T
MAX
Parameter
1, 2
(B Version)
Unit
Conditions/Comments
t
1
0
ns min
CS to WR Setup Time
t
2
0
ns min
CS to WR Hold Time
t
3
50
ns min
CS Pulsewidth Low
t
4
50
ns min
WR Pulsewidth Low
t
5
20
ns min
A4A0, CAL, OFFS_SEL to
WR Setup Time
t
6
7
ns min
A4A0, CAL, OFFS_SEL to
WR Hold Time
NOTES
1
See Parallel Interface Timing Diagram.
2
Guaranteed by design and characterization, not production tested.
Specifications subject to change without notice.
SERIAL INTERFACE
Limit at T
MIN
, T
MAX
Parameter
1, 2
(B Version)
Unit
Conditions/Comments
f
CLKIN
3
14
MHz max
SCLK Frequency
t
1
28
ns min
SCLK High Pulsewidth
t
2
28
ns min
SCLK Low Pulsewidth
t
3
15
ns min
SYNC Falling Edge to SCLK Falling Edge Setup Time
t
4
50
ns min
SYNC Low Time
t
5
15
ns min
D
IN
Setup Time
t
6
5
ns min
D
IN
Hold Time
t
7
5
ns min
SYNC Falling Edge to SCLK Rising Edge Setup Time for Readback
t
8
4
20
ns max
SCLK Rising Edge to D
OUT
Valid
t
9
4
60
ns max
SCLK Falling Edge to D
OUT
High Impedance
t
10
400
ns min
10th SCLK Falling Edge to
SYNC Falling Edge for Readback
t
11
400
ns min
24th SCLK Falling Edge to
SYNC Falling Edge for DAC Mode Write
t
12
5
7
ns min
SCLK Falling Edge to
SYNC Falling Edge for Readback
NOTES
1
See Serial Interface Timing Diagrams.
2
Guaranteed by design and characterization, not production tested.
3
In ISHA mode the maximum SCLK frequency is 20 MHz and the minimum pulsewidth is 20 ns.
4
These numbers are measured with the load circuit of Figure 2.
5
SYNC should be taken low while SCLK is low for readback.
Specifications subject to change without notice.
AD5532B
(V
DD
= +8 V to +16.5 V, V
SS
= 4.75 V to 16.5 V; AV
CC
= +4.75 V to +5.25 V; DV
CC
= +2.7 V to +5.25 V;
AGND = DGND = DAC_GND = 0 V; REF_IN = 3 V; OFF_IN = OV; All specifications T
MIN
to T
MAX
, unless otherwise noted.)
AC CHARACTERISTICS
REV. A
AD5532B
5
SERIAL INTERFACE TIMING DIAGRAMS
1
2
3
4
5
6
7
8
9
10
t
1
t
2
t
3
t
4
t
5
t
6
MSB
LSB
SCLK
SYNC
D
IN
Figure 3. 10-Bit Write (ISHA Mode and Both Readback Modes)
1
2
3
4
5
t
1
t
2
t
3
t
4
LSB
t
5
t
6
21
22
23
24
MSB
SCLK
SYNC
D
IN
t
11
1
Figure 4. 24-Bit Write (DAC Mode)
2
1
3
4
5
6
7
8
9
10
11
12
13
14
MSB
LSB
SCLK
SYNC
D
OUT
10
t
12
t
10
t
1
t
2
t
4
t
8
t
9
t
7
Figure 5. 14-Bit Read (Both Readback Modes)
PARALLEL INTERFACE TIMING DIAGRAM
CS
WR
A4A0, CAL,
OFFS SEL
Figure 1. Parallel Write (ISHA Mode Only)
I
OL
200 A
I
OH
200 A
C
L
50pF
TO
OUTPUT
PIN
1.6V
Figure 2. Load Circuit for D
OUT
Timing Specifications
Document Outline
- FEATURES
- APPLICATIONS
- GENERAL DESCRIPTION
- PRODUCT HIGHLIGHTS
- FUNCTIONAL BLOCK DIAGRAM
- SPECIFICATIONS
- AC CHARACTERISTICS
- TIMING CHARACTERISTICS
- PARALLEL INTERFACE TIMING DIAGRAM
- SERIAL INTERFACE TIMING DIAGRAMS
- ABSOLUTE MAXIMUM RATINGS
- ORDERING GUIDE
- PIN CONFIGURATION
- PIN FUNCTION DESCRIPTIONS
- TERMINOLOGY
- DAC MODE
- Integral Nonlinearity (INL)
- Differential Nonlinearity (DNL)
- Offset
- Full-Scale Error
- Output Settling Time
- OFFS_IN Settling Time
- Digital-to-Analog Glitch Impulse
- Digital Crosstalk
- Analog Crosstalk
- Digital Feedthrough
- Output Noise Spectral Density
- Output Temperature Coefficient
- DC Power Supply Rejection Ratio
- DC Crosstalk
- ISHA MODE
- Total Unadjusted Error (TUE)
- VIN to VOUT Nonlinearity
- Offset Error
- Gain Error
- AC Crosstalk
- Output Settling Time
- Acquisition Time
- Typical Performance Characteristics
- FUNCTIONAL DESCRIPTION
- Output Buffer StageGain and Offset
- Offset Voltage Channel
- Reset Function
- ISHA Mode
- Analog Input (ISHA Mode)
- TRACK Function (ISHA Mode)
- MODES OF OPERATION
- 1. ISHA Mode
- 2. DAC Mode
- 3. Acquire and Readback Mode
- 4. Readback Mode
- INTERFACES
- Serial Interface
- Parallel Interface (ISHA Mode Only)
- MICROPROCESSOR INTERFACING
- AD5532B to ADSP-21xx Interface
- AD5532B to MC68HC11
- AD5532B to PIC16C6x/PIC16C7x
- AD5532B to 8051
- APPLICATION CIRCUITS
- AD5532B in a Typical ATE System
- Typical Application Circuit (DAC MODE)
- Typical Application Circuit (ISHA Mode)
- POWER SUPPLY DECOUPLING
- OUTLINE DIMENSIONS
- Revision History
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