AD5624/AD5664 2.7 V to 5.5 V, 600 A, Rail-to-Rail Output, Quad 12-/16-Bit nanoDAC Data Sheet (Rev. 0)
2.7 V to 5.5 V, 450 A, Rail-to-Rail Output,
Quad, 12-/16-Bit nanoDACs
AD5624/AD5664
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
2006 Analog Devices, Inc. All rights reserved.
FEATURES
Low power, quad nanoDACs
AD5664: 16 bits
AD5624: 12 bits
Relative accuracy: 12 LSBs max
Guaranteed monotonic by design
10-lead MSOP and 3 mm 3 mm LFCSP_WD
2.7 V to 5.5 V power supply
Power-on reset to zero
Per channel power-down
Serial interface, up to 50 MHz
APPLICATIONS
Process control
Data acquisition systems
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
FUNCTIONAL BLOCK DIAGRAM
INTERFACE
LOGIC
SCLK
SYNC
DIN
INPUT
REGISTER
DAC
REGISTER
V
DD
GND
POWER-ON
RESET
STRING
DAC A
BUFFER
V
REF
V
OUT
A
INPUT
REGISTER
DAC
REGISTER
STRING
DAC B
BUFFER
V
OUT
B
INPUT
REGISTER
DAC
REGISTER
STRING
DAC C
BUFFER
V
OUT
C
INPUT
REGISTER
DAC
REGISTER
STRING
DAC D
BUFFER
V
OUT
D
AD5624/AD5664
POWER-DOWN
LOGIC
05
943
-
0
01
Figure 1.
Table 1. Related Devices
Part No.
Description
AD5624R/AD5644R/AD5664R
2.7 V to 5.5 V quad, 12-, 14-,
16-bit DACs with internal
reference
GENERAL DESCRIPTION
The AD5624/AD5664, members of the nanoDAC family, are
low power, quad, 12-, 16-bit buffered voltage-out DACs that
operate from a single 2.7 V to 5.5 V supply and are guaranteed
monotonic by design.
The AD5624/AD5664 require an external reference voltage to
set the output range of the DAC. The part incorporates a power-
on reset circuit that ensures the DAC output powers up to 0 V
and remains there until a valid write takes place. The parts
contain a power-down feature that reduces the current
consumption of the device to 480 nA at 5 V and provides
software-selectable output loads while in power-down mode.
The low power consumption of these parts in normal operation
makes them ideally suited to portable battery-operated
equipment. The power consumption is 2.25 mW at 5 V, going
down to 2.4 W in power-down mode.
The AD5624/AD5664 on-chip precision output amplifier allows
rail-to-rail output swing to be achieved.
The AD5624/AD5664 use a versatile 3-wire serial interface that
operates at clock rates up to 50 MHz, and are compatible with
standard SPI, QSPITM, MICROWIRETM, and DSP interface
standards.
PRODUCT HIGHLIGHTS
1.
Relative accuracy: 12 LSBs maximum.
2.
Available in 10-lead MSOP and 10-lead, 3 mm 3 mm,
LFCSP_WD.
3.
Low power, typically consumes 1.32 mW at 3 V and
2.25 mW at 5 V.
4.
Maximum settling time of 4.5 s (AD5624) and 7 s
(AD5664).
AD5624/AD5664
Rev. 0 | Page 2 of 24
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Specifications..................................................................................... 3
AC Characteristics........................................................................ 4
Timing Characteristics ................................................................ 5
Timing Diagram ........................................................................... 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. 8
Terminology .................................................................................... 13
Theory of Operation ...................................................................... 15
D/A Section................................................................................. 15
Resistor String ............................................................................. 15
Output Amplifier........................................................................ 15
Serial Interface ............................................................................ 15
Input Shift Register .................................................................... 16
SYNC Interrupt .......................................................................... 16
Power-On Reset.......................................................................... 16
Software Reset............................................................................. 17
Power-Down Modes .................................................................. 17
LDAC Function .......................................................................... 18
Microprocessor Interfacing....................................................... 19
Applications..................................................................................... 20
Choosing a Reference for the AD5624/AD5664.................... 20
Using a Reference as a Power Supply for the
AD5624/AD5664........................................................................ 20
Bipolar Operation Using the AD5624/AD5664..................... 21
Using AD5624/AD5664 with a Galvanically Isolated
Interface ....................................................................................... 21
Power Supply Bypassing and Grounding................................ 21
Outline Dimensions ....................................................................... 22
Ordering Guide .......................................................................... 22
REVISION HISTORY
6/06--Revision 0: Initial Version
AD5624/AD5664
Rev. 0 | Page 3 of 24
SPECIFICATIONS
V
DD
= +2.7 V to +5.5 V; R
L
= 2 k to GND; C
L
= 200 pF to GND; V
REF
= V
DD
; all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 2.
A
Grade
1
B Grade
1
Parameter
Min
Typ
Max
Min
Typ
Max
Unit
Conditions/Comments
STATIC PERFORMANCE
2
AD5664
Resolution 16
16
Bits
Relative Accuracy
8
16
6
12
LSB
Differential Nonlinearity
1
1
LSB
Guaranteed monotonic by
design
AD5624
Resolution
12
Bits
Relative Accuracy
0.5
1
LSB
Differential Nonlinearity
0.25
LSB
Guaranteed monotonic by
design
Zero-Code Error
2
10
2
10
mV
All zeroes loaded to DAC
register
Offset Error
1
10
1
10
mV
Full-Scale Error
-0.1
1
-0.1
1
% of FSR
All ones loaded to DAC register
Gain Error
1.5
1.5
% of FSR
Zero-Code Error Drift
2
2
V/C
Gain Temperature
Coefficient
2.5
2.5
ppm
of FSR/C
DC Power Supply Rejection
Ratio
-100
-100
dB
DAC code = midscale ; V
DD
10%
DC Crosstalk
10
10
V
Due to full-scale output
change
R
L
= 2 k to GND or V
DD
10
10
V/mA
Due to load current change
5
5
V
Due to powering down (per
channel)
OUTPUT CHARACTERISTICS
3
Output Voltage Range
0
V
DD
0
V
DD
V
Capacitive Load Stability
2
2
nF
R
L
=
10
10
nF
R
L
= 2 k
DC Output Impedance
0.5
0.5
Short-Circuit Current
30
30
mA
V
DD
= 5 V
Power-Up Time
4
4
s
Coming out of power-down
mode; V
DD
= 5 V
REFERENCE INPUTS
Reference Current
170
200
170
200
A
V
REF
= V
DD
= 5.5 V
Reference Input Range
0.75
V
DD
0.75
V
DD
V
Reference Input Impedance
26
26
k
LOGIC INPUTS
3
Input Current
2
2
A
All digital inputs
V
INL
, Input Low Voltage
0.8
0.8
V
V
DD
= 5 V, 3 V
V
INH
, Input High Voltage
2
2
V
V
DD
= 5 V, 3 V
Pin Capacitance
3
3
pF
AD5624/AD5664
Rev. 0 | Page 4 of 24
A
Grade
1
B Grade
1
Parameter
Min
Typ
Max
Min
Typ
Max
Unit
Conditions/Comments
POWER REQUIREMENTS
V
DD
2.7
5.5
2.7
5.5
V
I
DD
(Normal Mode)
4
V
IH
= V
DD
, V
IL
= GND
V
DD
= 4.5 V to 5.5 V
0.45
0.9
0.45
0.9
mA
V
DD
= 2.7 V to 3.6 V
0.44
0.85
0.44
0.85
mA
I
DD
(All Power-Down
Modes)
5
V
IH
= V
DD
, V
IL
= GND
V
DD
= 4.5 V to 5.5 V
0.48
1
0.48
1
A
V
DD
= 2.7 V to 3.6 V
0.2
1
0.2
1
A
1
Temperature range: A grade and B grade: -40C to +105C.
2
Linearity calculated using a reduced code range: AD5664 (Code 512 to Code 65,024); AD5624 (Code 32 to Code 4064); output unloaded.
3
Guaranteed by design and characterization, not production tested.
4
Interface inactive. All DACs active. DAC outputs unloaded.
5
All DACs powered down.
AC CHARACTERISTICS
V
DD
= 2.7 V to 5.5 V; R
L
= 2 k to GND; C
L
= 200 pF to GND; V
REF
= V
DD
; all specifications T
MIN
to T
MAX
, unless otherwise noted.
1
Table 3.
Parameter
2 , 3
Min
Typ
Max
Unit
Conditions/Comments
Output Voltage Settling Time
AD5664
4
7
s
to scale settling to 2 LSB
AD5624
3
4.5
s
to scale settling to 0.5 LSB
Slew Rate
1.8
V/s
Digital-to-Analog Glitch Impulse
10
nV-s
1 LSB change around major carry
Digital Feedthrough
0.1
nV-s
Reference Feedthrough
-90
dBs
V
REF
= 2 V 0.1 V p-p, frequency 10 Hz to 20 MHz
Digital Crosstalk
0.1
nV-s
Analog Crosstalk
1
nV-s
DAC-to-DAC Crosstalk
1
nV-s
Multiplying Bandwidth
340
kHz
V
REF
= 2 V 0.1 V p-p
Total Harmonic Distortion
-80
dB
V
REF
= 2 V 0.1 V p-p, frequency = 10 kHz
Output Noise Spectral Density
120
nV/Hz
DAC code = midscale, 1 kHz
100
nV/Hz
DAC code = midscale, 10 kHz
Output Noise
15
V p-p
0.1 Hz to 10 Hz
1
Guaranteed by design and characterization, not production tested.
2
Temperature range: -40C to +105C; typical at 25C.
3
See the Terminology section.
AD5624/AD5664
Rev. 0 | Page 5 of 24
TIMING CHARACTERISTICS
All input signals are specified with t
R
= t
F
= 1 ns/V (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2 (see Figure 2).
V
DD
= 2.7 V to 5.5 V; all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 4.
Limit
at
T
MIN
, T
MAX
Parameter
1
V
DD
= 2.7 V to 5.5 V
Unit
Conditions/Comments
t
1
2
20
ns min
SCLK cycle time
t
2
9
ns min
SCLK high time
t
3
9
ns min
SCLK low time
t
4
13 ns
min
SYNC to SCLK falling edge setup time
t
5
5
ns min
Data setup time
t
6
5
ns min
Data hold time
t
7
0 ns
min
SCLK falling edge to SYNC rising edge
t
8
15 ns
min
Minimum SYNC high time
t
9
13 ns
min
SYNC rising edge to SCLK fall ignore
t
10
0 ns
min
SCLK falling edge to SYNC fall ignore
1
Guaranteed by design and characterization, not production tested.
2
Maximum SCLK frequency is 50 MHz at V
DD
= 2.7 V to 5.5 V.
TIMING DIAGRAM
DB0
DB23
t
10
SCLK
SYNC
DIN
t
1
t
9
t
7
t
2
t
3
t
6
t
5
t
4
t
8
05
94
3-
00
2
Figure 2. Serial Write Operation
Document Outline
PDF 
ZIP