Octal, 12-14-16 Bit Dac with 10ppm/C Max
On-Chip Reference in 14-Lead TSSOP
Preliminary Technical Data
AD5628/AD5648/AD5668
FEATURES
Low Power Smallest Pin compatible Octal DACs
AD5668: 16 Bits
AD5648: 14 Bits
AD5628: 12 Bits
12-Bit Accuracy Guaranteed
14/16-Lead TSSOP Package
On-chip 1.25/2.5V, 10ppm/C Reference
Power-Down to 200 nA @ 5V, 50 nA @ 3V
3V/5V Power Supply
Guaranteed Monotonic by Design
Power-On-Reset to Zero/Midscale
Three Power-Down Functions
Hardware /LDAC and /CLR functions
Rail-to-Rail Operation
Temperature Range -40C to +125C
APPLICATIONS
ProcessControl
Data Acquisition Systems
Portable Battery Powered Instruments
Digital Gain and Offset Adjustment
Programmable Voltage and Current Sources
Programmable Attenuators
INTERFACE
LOGIC
I
NPUT
REGISTER
I
NPUT
REGISTER
I
NPUT
REGIS-
TER
I
NPUT
REGISTER
I
NPUT
REGISTER
I
NPUT
REGISTER
I
NPUT
REGISTER
I
NPUT
REGISTER
D
AC
REGISTER
D
AC
REGISTER
D
AC
REGISTER
D
AC
REGISTER
DAC
REGISTER
D
AC
REGISTER
DAC
REGISTER
DAC
REGISTER
STRING
DAC C
STRING
DAC A
STRING
DAC B
STRING
DAC D
STRING
DAC E
STRING
DAC F
STRING
DAC G
STRING
DAC H
BUFFER
BUFFER
BUFFER
BUFFER
BUFFER
BUFFER
BUFFER
BUFFER
DIN
LDAC
POWER-DOWN
LOGIC
GND
VOUTB
VOUTC
VOUTD
VOUTE
VOUTG
VOUTH
VOUTF
VDD
POWER-ON
RESET
LDAC*
VOUTA
V
REF
SYNC
SCLK
AD5628/AD5648/AD5668
CLR*
*RU-16 PACKAGE ONLY
1.25/2.5V
Ref
Figure 1. Functional Block Diagram
GENERAL DESCRIPTION
The AD5628/48/68 family of devices are low power, octal, 12-
14-16-bit buffered voltage-out DACs. All devices operate from
a single +2.7V to +5.5V, and are guaranteed monotonic by
design.
The AD5628/48/68 have an on-chip reference with an internal
gain of two. The AD56x8-1 has a 1.25V 10ppm/C max
reference and the AD56x8-2,-3 have a 2.5V 10ppm/C max
reference. The on-board reference is off at power-up allowing
the use of an external reference. The internal reference is
turned on by writing to the DAC. The part incorporates a
power-on-reset circuit that ensures that the DAC output
powers up to zero volts (AD56x8-1,-2/) or midscale (AD5668-
3) and remains there until a valid write takes place. The part
contains a power-down feature that reduces the current
consumption of the device to 200nA at 5V and provides
software selectable output loads while in power-down mode for
any or all DACs channels.
The outputs of all DACs may be updated simultaneously using
the /LDAC function, with the added functionality of selecting
through software any number of DAC channels to synchronize.
There is also an asynchronous active low /CLR that clears all
DACs to a software selectable code - 0 V, midscale or fullscale .
The AD5628/48/68 utilizes a versatile three-wire serial
interface that operates at clock rates up to 50 MHz and is
compatible with standard SPITM, QSPITM, MICROWIRETM and
DSP interface standards. Its on-chip precision output amplifier
allows rail-to-rail output swing to be achieved.
PRODUCT HIGHLIGHTS
1.
Octal 12/14/16-Bit DAC; 12-Bit Accuracy Guaranteed.
2.
On-chip 1.25/2.5V, 10ppm/C max Reference.
3.
Available in 14/16-lead TSSOP package.
4.
Power-On-Reset to Zero volts or Midscale.
5.
Power-down capability. When powered down, the
DAC typically consumes 50nA at 3V and 200nA at 5V.
Rev. PrA
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
2004 Analog Devices, Inc. All rights reserved.
AD5628/AD5648/AD5668
Preliminary Technical Data
Rev.PrA | Page 2 of 24
TABLE OF CONTENTS
Features .......................................................................................... 1
Applications................................................................................... 1
General Description..................................................................... 1
Product Highlights ....................................................................... 1
AD5628/AD5648/AD5668Specifications ................................... 3
Timing Characteristics..................................................................... 9
Pin Configuration and Function Descriptions........................... 10
Absolute Maximum Ratings.......................................................... 11
ESD Caution................................................................................ 11
Terminology ................................................................................ 11
AD5628/AD5648/AD5668Typical Performance
Characteristics ................................................................................ 13
General Description................................................................... 16
Serial Interface ............................................................................ 16
Microprocessor Interfacing............................................................
Applications .....................................................................................
Outline Dimensions ....................................................................... 23
Ordering Guide ...............................................................................
REVISION HISTORY
Revision 0: Initial Version
Preliminary Technical Data
AD5628/AD5648/AD5668
Rev. PrA| Page 3 of 24
AD5628/AD5648/AD5668SPECIFICATIONS
(V
DD
= +4.5 V to +5.5 V; R
L
= 2 k to GND; C
L
= 200 pF to GND; External REFIN = V
DD
; all specifications T
MIN
to T
MAX
unless otherwise
noted)
Table 1.
A Grade
B Grade
Parameter
Min
Typ
Max
Min
Typ
Max
Unit
B Version
1
,
2
Conditions/Comments
STATIC PERFORMANCE
3,4
AD5628
Resolution
12
12
Bits
Relative Accuracy
0.5
6
0.5
1
LSB
See Figure 4
Differential Nonlinearity
1
1
LSB
Guaranteed Monotonic by Design. See
Figure 5.
AD5648
Resolution
14
14
Bits
Relative Accuracy
2
8
2
4
LSB
See Figure 4
Differential Nonlinearity
1
1
LSB
Guaranteed Monotonic by Design. See
Figure 5.
AD5668
Resolution
16
16
Bits
Relative Accuracy
32
16
LSB
See Figure 4
Differential Nonlinearity
1
1
LSB
Guaranteed Monotonic by Design. See
Figure 5.
Load Regulation
2
2
LSB/mA
VDD=Vref=5V, Midscale
Iout=0mA to
15mA sourcing/sinking
Zero Code Error
+1
+9
+1
+9
mV
All Zeroes Loaded to DAC Register. See
Figure 8.
Zero Code Error Drift
3
20
20
V/C
Full-Scale Error
-0.15
-1.25
-0.15
-1.25
% of FSR
All Ones Loaded to DAC Register. See
Figure 8.
Gain Error
1.5
1.5
% of FSR
Gain Temperature
Coefficient
5
5
ppm
of
FSR/C
Offset Error
1
9
1
9
mV
Offset Temperature
Coefficient
1.7
1.7
V/C
DC Power Supply Rejection
Ratio
6
80
80
dB
V
DD
10%
DC Crosstalk
6
(Ext Ref)
10
10
V
R
L
= 2 k. to GND or V
DD
4.5
4.5
V/mA
Due to Load current change
10
10
V
Due to Powering Down (per channel)
DC Crosstalk
6
(Int Ref)
20
20
V
R
L
= 2 k. to GND or V
DD
4.5
4.5
V/mA
Due to Load current change
20
20
V
Due to Powering Down (per channel)
1
Temperature ranges are as follows: B Version: -40C to +125C, typical at 25C.
2
Linearity calculated using a reduced code range of 485 to 64714. Output unloaded.
3
DC specifications tested with the outputs unloaded unless stated otherwise.
4
Linearity is tested using a reduced code range: AD5628 (Code 48 to Code 4047), AD5648 (Code / to Code /), and AD5668 (Code 485 to 64714).
6
Guaranteed by design and characterization; not production tested.
8
Interface inactive. All DACs active. DAC outputs unloaded.
9
All eight DACs powered down.
Specifications subject to change without notice.
AD5628/AD5648/AD5668
Preliminary Technical Data
Rev.PrA | Page 4 of 24
A Grade
B Grade
Parameter
Min
Typ
Max
Min
Typ
Max
Unit
B Version
1
,
2
Conditions/Comments
OUTPUT
CHARACTERISTICS
6
Output Voltage Range
0
V
DD
0
V
DD
V
Capacitive Load Stability
2
2
pF
R
L
=
10
10
pF
R
L
=2 k
DC Output Impedance
0.5
0.5
Short Circuit Current
30
30
mA
V
DD
=+5V
Power-Up Time
4
4
s
Coming out of Power-Down Mode.
V
DD
=+5V
REFERENCE INPUTS
3
Reference Input voltage
V
DD
V
DD
V
1% for specified performance
Reference Current
35
45
35
45
A
V
REF
= V
DD
= +5.5V (per DAC channel)
Reference Input Range
0
V
DD
0
V
DD
Reference
Input
Impedance
14.6
14.6
k
Per DAC channel
REFERENCE
OUTPUT
Output Voltage
AD5628/AD5648/AD5668x-
2/3
2.495 2.5
2.505 2.495 2.5
2.505 V
Reference TC
10
10
ppm/C
Reference Output
Impedance
2
2
k
LOGIC INPUTS
3
Input Current
1
1
A
V
INL
, Input Low Voltage
0.8
0.8
V
V
DD
=+5 V
V
INH
, Input High Voltage
2
2
V
V
DD
=+5 V
Pin Capacitance
3
3
pF
POWER
REQUIREMENTS
V
DD
4.5
5.5
4.5
5.5
V
All Digital Inputs at 0 or V
DD
I
DD
(Normal Mode)
8
DAC Active and Excluding Load Current
V
DD
=4.5 V to +5.5 V
2
4
2
4
mA
V
IH
=V
DD
and V
IL
=GND
I
DD
(All Power-Down
Modes)
9
V
DD
=4.5 V to +5.5 V
0.2
1
0.2
1
A
V
IH
=V
DD
and V
IL
=GND
POWER
EFFICIENCY
I
OUT
/I
DD
89
89
% I
LOAD
=2 mA, V
DD
=+5 V
Preliminary Technical Data
AD5628/AD5648/AD5668
Rev. PrA| Page 5 of 24
AC CHARACTERISTICS
1
(V
DD
= +4.5 V to +5.5 V; R
L
= 2 k to GND; C
L
= 200 pF to GND; External REFIN = V
DD
; all
specifications T
MIN
to T
MAX
unless otherwise noted)
NOTES
1
Guaranteed by design and characterization; not production tested.
2
See the Terminology section.
3
Temperature range (Y Version): 40
C to +125C; typical at +25C.
Specifications subject to change without notice.
Parameter
2
Min
Typ
Max
Unit
B Version
1
Conditions/Comments
Output Voltage Settling Time
AD5628
6
8
s
to scale settling to 2LSB
AD5648
7
9
s
to scale settling to 2LSB
AD5668
8
10
s
to scale settling to 2LSB
Settling Time for 1LSB Step
Slew Rate
1.5
V/s
Digital-to-Analog Glitch Impulse
5
nV-s
1 LSB Change Around Major Carry. See Figure 21.
Channel to-Channel Isolation
100
dB
Digital Feedthrough
0.1
nV-s
Digital Crosstalk
0.5
nV-s
Analog Crosstalk
1
nV-s
DAC-to-DAC Crosstalk
3
nV-s
Multiplying Bandwidth
200
kHz
VREF = 2V 0.1 V p-p.
Total Harmonic Distortion
-80
dB
VREF = 2V 0.1 V p-p. Frequency = 10kHz
Output Noise Spectral Density
120
nV/Hz
DAC code=8400
H
, 1kHz
100
nV/Hz
DAC code=8400
H
, 10kHz
Output Noise
15
Vp-p
0.1Hz to 10Hz;
AD5628/AD5648/AD5668
Preliminary Technical Data
Rev.PrA | Page 6 of 24
AD5628/AD5648/AD5668SPECIFICATIONS
(V
DD
= +2.7 V to +3.6 V; R
L
= 2 k to GND; C
L
= 200 pF to GND; External REFIN = V
DD
; all specifications T
MIN
to T
MAX
unless otherwise
noted)
Table 2.
A Grade
B Grade
Parameter
Min
Typ
Max
Min
Typ
Max
Unit
B Version
1
,
1
Conditions/Comments
STATIC PERFORMANCE
3,4
AD5628
Resolution
12
12
Bits
Relative Accuracy
0.5
6
0.5
1
LSB
See Figure 4
Differential Nonlinearity
1
1
LSB
Guaranteed Monotonic by Design.
See Figure 5.
AD5648
Resolution
14
14
Bits
Relative Accuracy
2
8
2
4
LSB
See Figure 4
Differential Nonlinearity
1
1
LSB
Guaranteed Monotonic by Design.
See Figure 5.
AD5668
Resolution
16
16
Bits
Relative Accuracy
32
16
LSB
See Figure 4
Differential Nonlinearity
1
1
LSB
Guaranteed Monotonic by Design.
See Figure 5.
Load
Regulation
4
4
LSB/mA
VDD=Vref=3V, Midscale
Iout=0mA to 7.5mA
sourcing/sinking
Zero Code Error
+1
+9
+1
+9
mV
All Zeroes Loaded to DAC Register.
See Figure 8.
Zero Code Error Drift
1
20
20
V/C
Full-Scale Error
-0.15
-1.25
-0.15
-1.25
% of FSR
All Ones Loaded to DAC Register.
See Figure 8.
Gain Error
0.7
0.7
% of FSR
Gain Temperature
Coefficient
5
5
ppm
of
FSR/C
Offset Error
1
9
1
9
mV
Offset Temperature
Coefficient
1.7
1.7
V/C
DC Power Supply Rejection
Ratio
6
80
80
dB
V
DD
10%
DC Crosstalk
6
(Ext Ref)
10
10
V
R
L
= 2 k. to GND or V
DD
4.5
4.5
V/mA
Due to Load current change
10
10
V
Due to Powering Down (per
channel)
DC Crosstalk
6
(Int Ref)
20
20
V
R
L
= 2 k. to GND or V
DD
4.5
4.5
V/mA
Due to Load current change
20
20
V
Due to Powering Down (per
channel)
OUTPUT
CHARACTERISTICS
6
Output Voltage Range
0
V
DD
0
V
DD
V
Capacitive Load Stability
2
2
pF
R
L
=
Preliminary Technical Data
AD5628/AD5648/AD5668
Rev. PrA| Page 7 of 24
10
10
pF
R
L
=2 k
DC Output Impedance
0.5
0.5
Short Circuit Current
30
30
mA
V
DD
=+3V
Power-Up Time
5
5
s
Coming Out of Power-Down Mode.
V
DD
=+3V
REFERENCE INPUTS
3
Reference Input voltage
V
DD
V
DD
V
1% for specified performance
Reference
Current
20
20
20
20
A
V
REF
= V
DD
= +3.6V (per DAC
channel)
Reference Input Range
0
V
DD
0
V
DD
Reference
Input
Impedance
14.6
14.6
k
Per DAC channel
REFERENCE
OUTPUT
Output Voltage
AD5628/AD5648/AD5668x-
1
1.248 1.25 1.252 1.248 1.25 1.252 V
Reference TC
10
10
ppm/C
Reference Output
Impedance
2
2
k
LOGIC INPUTS
3
Input Current
1
1
A
V
INL
, Input Low Voltage
0.8
0.8
V
V
DD
=+3 V
V
INH
, Input High Voltage
2
2
V
V
DD
=+3 V
Pin Capacitance
3
3
pF
POWER
REQUIREMENTS
V
DD
2.7
3.6
2.7
3.6
V
All Digital Inputs at 0 or V
DD
I
DD
(Normal Mode)
8
DAC Active and Excluding Load
Current
V
DD
=2.7 V to +3.6 V
2
4
2
4
mA
V
IH
=V
DD
and V
IL
=GND
I
DD
(All Power-Down
Modes)
9
V
DD
=2.7 V to +3.6 V
0.2
1
0.2
1
A
V
IH
=V
DD
and V
IL
=GND
POWER
EFFICIENCY
I
OUT
/I
DD
89
89
% I
LOAD
=2 mA, V
DD
=+5 V
AC CHARACTERISTICS
1
(V
DD
= +2.7 V to +3.6 V; R
L
= 2 k to GND; C
L
= 200 pF to GND; External REFIN = V
DD
; all specifications T
MIN
to T
MAX
unless otherwise
noted)
Parameter
2
Min
Typ
Max
Unit
B Version
1
Conditions/Comments
Output Voltage Settling Time
AD5628
6
8
s
to scale settling to 2LSB
AD5648
7
9
s
to scale settling to 2LSB
AD5668
8
10
s
to scale settling to 2LSB
Settling Time for 1LSB Step
Slew Rate
1.5
V/s
Digital-to-Analog Glitch Impulse
10
nV-s
1 LSB Change Around Major Carry. See Figure 21.
Channel to-Channel Isolation
100
dB
Digital Feedthrough
0.5
nV-s
AD5628/AD5648/AD5668
Preliminary Technical Data
Rev.PrA | Page 8 of 24
Digital Crosstalk
0.5
nV-s
Analog Crosstalk
1
nV-s
DAC-to-DAC Crosstalk
3
nV-s
Multiplying Bandwidth
200
kHz
VREF = 2V 0.1 V p-p.
Total Harmonic Distortion
-80
dB
VREF = 2V 0.1 V p-p. Frequency = 10kHz
Output Noise Spectral Density
120
nV/Hz
DAC code=8400
H
, 1kHz
100
nV/Hz
DAC code=8400
H
, 10kHz
Output Noise
15
Vp-p
0.1Hz to 10Hz;
NOTES
1
Guaranteed by design and characterization; not production tested.
2
See the Terminology section.
3
Temperature range (Y Version): 40
C to +125C; typical at +25C.
Specifications subject to change without notice.
Preliminary Technical Data
AD5628/AD5648/AD5668
Rev. PrA| Page 9 of 24
TIMING CHARACTERISTICS
All input signals are specified with tr = tf = 1 ns/V (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2.
See Figure 2.
(V
DD
= +2.7 V to +5.5 V; all specifications T
MIN
to T
MAX
unless otherwise noted)
Limit at T
MIN
, T
MAX
Parameter
V
DD
= 2.7 V to 3.6 V
V
DD
= 3.6 V to 5.5 V
Unit
Conditions/Comments
t
1
1
20
20
ns min
SCLK Cycle Time
t
2
11
9
ns min
SCLK High Time
t
3
9
9
ns min
SCLK Low Time
t
4
13
13
ns min
SYNC to SCLK Falling Edge Setup Time
t
5
4
4
ns min
Data Setup Time
t
6
4
4
ns min
Data Hold Time
t
7
0
0
ns min
SCLK Falling Edge to SYNC Rising Edge
t
8
25
20
ns min
Minimum SYNC High Time
t
9
13
13
ns min
SYNC Rising Edge to SCLK Fall Ignore
t
10
0
0
ns min
SCLK Falling Edge to SYNC Fall Ignore
t
11
20
20
ns min
LDAC Pulsewidth Low
t
12
20
20
ns min
SCLK Falling Edge to LDAC Rising Edge
t
13
20
20
ns min
/CLR Pulse Width Low
t
14
0
0
ns min
SCLK Falling Edge to LDAC Falling Edge
t
15
tbd
tbd
ns min
/CLR Pulse Activation Time (AD5380?)
t
4
t
3
SCLK
SYNC
DIN
t
1
t
2
t
5
t
6
t
7
t
8
DB31
DB0
t
9
t
10
t11
t12
LDAC1
LDAC2
t14
NOTES
1. ASYNCHRONOUS LDAC UPDATE MODE.
2. SYNCHRONOUS LDAC UPDATE MODE.
t13
CLR
Figure 2. Serial Write Operation
1
3Maximum SCLK frequency is 50 MHz at V
DD
= +2.7 V to +5.5 V
AD5628/AD5648/AD5668
Preliminary Technical Data
Rev.PrA | Page 10 of 24
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
SYNC
VOUTA
1
2
14
13
5
6
7
10
9
8
3
4
12
11
TOP VIEW
(Not to Scale)
AD5628
AD5648
AD5668
DIN
GND
V
DD
SCLK
VOUTB
VOUTD
VOUTC
VOUTE
VOUTF
VOUTG
VOUTH
VREF
LDAC
SYNC
VOUTA
1
2
16
15
5
6
7
12
11
10
3
4
14
13
8
9
TOP VIEW
(Not to Scale)
AD5628
AD5648
AD5668
DIN
GND
V
DD
SCLK
VOUTB
VOUTD
VOUTC
VOUTE
VOUTF
VOUTG
VOUTH
CLR
VREF
Figure 3. 14-Lead TSSOP (RU-14)
Figure 4. 16-Lead TSSOP (RU-16)
Table 2. Pin Function Descriptions
Pin No.
Mnemonic
Function
1
/LDAC
Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data.
This allows simultaneous update of all DAC outputs. Alternatively, this pin can be tied permanently
low.
2
/SYNC
Active Low-Control Input. This is the frame synchronization signal for the input data. When SYNC
goes low, it powers on the SCLK and DIN buffers and enables the input shift register. Data is
transferred in on the falling edges of the following 32 clocks. If SYNC is taken high before the 32nd
falling edge, the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the
device.
3
VDD
Power Supply Input. These parts can be operated from 2.5 V to 5.5 V, and the supply should be
decoupled with a 10 F capacitor in parallel with a 0.1 F capacitor to GND.
4
VOUTA
Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
13
VOUTB
Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
5
VOUTC
Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.
12
VOUTD
Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.
8 VREF
Reference
Input/Output
Pin
9 /CLR
Active Low Control Input that Loads Software selectable code Zero, midscale, fullscale - to All Input and
DAC Registers. Therefore, the outputs also go to selected code. Default clears the output to 0V.
6
VOUTE
Analog Output Voltage from DAC E. The output amplifier has rail-to-rail operation.
11
VOUTF
Analog Output Voltage from DAC F. The output amplifier has rail-to-rail operation.
7
VOUTG
Analog Output Voltage from DAC G. The output amplifier has rail-to-rail operation.
10
VOUTH
Analog Output Voltage from DAC H. The output amplifier has rail-to-rail operation.
14
GND
Ground Reference Point for All Circuitry on the Part.
15 DIN
Serial Data Input. This device has a 32-bit shift register. Data is clocked into the register on the falling
edge of the serial clock input.
16 SCLK
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock
input. Data can be transferred at rates up to 50 MHz.
Preliminary Technical Data
AD5628/AD5648/AD5668
Rev. PrA| Page 11 of 24
ABSOLUTE MAXIMUM RATINGS
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
(T
A
= +25C unless otherwise noted)
Parameter Rating
V
DD
to GND
-0.3 V to +7 V
Digital Input Voltage to GND
-0.3 V to V
DD
+ 0.3 V
V
OUT
to GND
-0.3 V to V
DD
+ 0.3 V
Operating Temperature Range
Industrial (B Version)
-40C to +105C
Storage Temperature Range
-65C to +150C
Junction Temperature (T
J
Max)
+150C
TSSOP Package
Power Dissipation
(T
J
Max-T
A
)/
JA
JA
Thermal Impedance
150.4C/W
Lead Temperature, Soldering
Vapor Phase (60 sec)
+215C
Infrared (15 sec)
+220C
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
TERMINOLOGY
Relative Accuracy
For the DAC, relative accuracy or Integral Nonlinearity (INL) is a
measure of the maximum deviation, in LSBs, from a straight line
passing through the endpoints of the DAC transfer function. A
typical INL vs. code plot can be seen in Figure 2.
Differential Nonlinearity
Differential Nonlinearity (DNL) is the difference between the
measured change and the ideal 1 LSB change between any two
adjacent codes. A specified differential nonlinearity of 1 LSB
maximum ensures monotonicity. This DAC is guaranteed
monotonic by design. A typical DNL vs. code plot can be seen in
Figure 3.
Offset Error
Offset error is a measure of the difference between VOUT
(actual) and VOUT (ideal) expressed in mV in the linear
region of the transfer function. Offset error is measured on
the AD5668 with Code ??? loaded into the DAC register.
This is a measure of the offset error of the DAC and the output
amplifier (see Figures 2 and 3). It can be negative or positive, and is
expressed in mV.
Zero-Code Error
Zero-code error is a measure of the output error when zero code
(0000Hex) is loaded to the DAC register. Ideally the output should
be 0 V. The zero-code error is always positive in the AD56x8
because the output of the DAC cannot go below 0 V. It is due to a
combination of the offset errors in the DAC and output amplifier.
Zero-code error is expressed in mV. A plot of zero-code error vs.
temperature can be seen in Figure 6.
Gain Error
This is a measure of the span error of the DAC. It is the deviation
in slope of the DAC transfer characteristic from ideal expressed as
a percent of the full-scale range.
Zero-Code Error Drift
This is a measure of the change in zero-code error with a change in
temperature. It is expressed in V/C.
Gain Error Drift
This is a measure of the change in gain error with changes in
temperature. It is expressed in (ppm of full-scale range)/C.
Full-Scale Error
Full-scale error is a measure of the output error when full-scale
code (FFFF Hex) is loaded to the DAC register. Ideally the output
should be VDD 1 LSB. Full-scale error is expressed in
percent of
full-scale range. A plot of full-scale error vs.
temperature can be
seen in Figure 6.
Total Unadjusted Error
Total Unadjusted Error (TUE) is a measure of the output error
AD5628/AD5648/AD5668
Preliminary Technical Data
Rev.PrA | Page 12 of 24
taking the various offset and gain errors into account. A typical
TUE vs. code plot can be seen in Figure 4.
Digital-to-Analog Glitch Impulse
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nV secs and
is measured when the digital input code is changed by 1 LSB at the
major carry transition (7FFF Hex to 8000 Hex). See Figure 19.
DC Power Supply Rejection Ratio (PSRR)
This indicates how the output of the DAC is affected by changes in
the supply voltage. PSRR is the ratio of the change in VOUT
to a change in VDD for full-scale output of the DAC. It is
measured in dB. VREF is held at 2 V and VDD is varied 10%.
DC Crosstalk
This is the dc change in the output level of one DAC in response to
a change in the output of another DAC. It is measured with a full-
scale output change on one DAC while monitoring another DAC
kept at midscale. It is expressed in V.
Reference Feedthrough
This is the ratio of the amplitude of the signal at the DAC output to
the reference input when the DAC output is not being updated
(i.e., LDAC is high). It is expressed in dB.
Channel-to-Channel Isolation
This is the ratio of the amplitude of the signal at the output of one
DAC to a sine wave on the reference input of another DAC. It is
measured in dB.
Major-Code Transition Glitch Energy
Major-code transition glitch energy is the energy of the impulse
injected into the analog output when the code in the DAC register
changes state. It is normally specified as the area of the glitch in
nV-s and is measured when the digital code is changed by 1 LSB at
the major carry transition (011 . . . 11 to 100 . . . 00 or 100 . . . 00 to
011 . . . 11).
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into the
analog output of a DAC from the digital input pins of the device,
but is measured when the DAC is not being written to (SYNC held
high). It is specified in nV-s and is measured with a fullscale
change on the digital input pins, i.e., from all 0s to all 1s and vice
versa.
Digital Crosstalk
This is the glitch impulse transferred to the output of one DAC at
midscale in response to a full-scale code change (all 0s to all 1s and
vice versa) in the input register of another DAC. It is measured in
standalone mode and is expressed in nV-s.
Analog Crosstalk
This is the glitch impulse transferred to the output of one DAC due
to a change in the output of another DAC. It is measured by
loading one of the input registers with a full-scale code change (all
0s to all 1s and vice versa) while keeping LDAC high. Then pulse
LDAC low and monitor the output of the DAC whose digital code
was not changed. The area of the glitch is expressed in nV-s.
DAC-to-DAC Crosstalk
This is the glitch impulse transferred to the output of one DAC due
to a digital code change and subsequent output change of another
DAC. This includes both digital and analog crosstalk. It is
measured by loading one of the DACs with a full-scale code change
(all 0s to all 1s and vice versa) with LDAC low and monitoring the
output of another DAC. The energy of the glitch is expressed in
nV-s.
Multiplying Bandwidth
The amplifiers within the DAC have a finite bandwidth. The
multiplying bandwidth is a measure of this. A sine wave on the
reference (with full-scale code loaded to the DAC) appears on the
output. The multiplying bandwidth is the frequency at which the
output amplitude falls to 3 dB below the input.
Total Harmonic Distortion
This is the difference between an ideal sine wave and its attenuated
version using the DAC. The sine wave is used as the reference for
the DAC, and the THD is a measure of the harmonics present on
the DAC output. It is measured in dB.
Preliminary Technical Data
AD5628/AD5648/AD5668
Rev. PrA| Page 13 of 24
AD5628/AD5648/AD5668TYPICAL PERFORMANCE CHARACTERISTICS
Figure 4. Typical INL Plot
Figure 5. Typical DNL Plot
Figure 6. Typical Total Unadjusted Error Plot
Figure 7. INL Error and DNL Error vs. Temperature
Figure 8. Zero-Scale Error and Full-Scale Error vs. Temperature
Figure 9. I
DD
Histogram with V
DD
=3V and V
DD
=5V
AD5628/AD5648/AD5668
Preliminary Technical Data
Rev.PrA | Page 14 of 24
Figure 10. Source and Sink Current Capability with V
DD
=3V
Figure 11. Source and Sink Current Capability with V
DD
=5 V
Figure 12. Supply Current vs. Code
Figure 13. Supply Current vs. Temperature
Figure 14. Supply Current vs. Supply Voltage
Figure 15. Power-Down Current vs. Supply Voltage
Preliminary Technical Data
AD5628/AD5648/AD5668
Rev. PrA| Page 15 of 24
Figure 16. Supply Current vs. Logic Input Voltage
Figure 17. Full-Scale Settling Time
Figure 18. Half-Scale Settling Time
Figure 19. Power-On Reset to 0V
Figure 20. Exiting Power-Down (800 Hex Loaded)
Figure 21. Digital-to-Analog Glitch Impulse
AD5628/AD5648/AD5668
Preliminary Technical Data
Rev.PrA | Page 16 of 24
GENERAL DESCRIPTION
D/A Section
The AD5628/AD5648/AD5668 DACs are fabricated on a
CMOS process. The architecture consists of a string DAC
followed by an output buffer amplifier. The parts include an
internal 1.25/2.5V, 10ppm/C reference with an internal gain of
two. Figure 22 shows a block diagram of the DAC architecture.
V
OUT
OUTPUT
AMPLIFIER
(Gain=2)
V
DD
GND
RESISTOR
STRING
REF (+)
REF ()
DAC REGISTER
Figure 22. DAC Architecture
Since the input coding to the DAC is straight binary, the ideal
output voltage is given by:
=
N
D
ext
Vref
V
OUT
^
2
)
(
=
N
D
Vref
V
OUT
^
2
(int)
2
where D = decimal equivalent of the binary code that is loaded
to the DAC register;
0 - 4095 for AD5628 (12 bit)
0 - 16383 for AD5648 (14 bit)
0 - 65535 for AD5668 (16 bit)
N = the DAC resolution
Figure 23. Resistor String
Resistor String
The resistor string section is shown in Figure 23. It is simply a
string of resistors, each of value R. The code loaded to the DAC
register determines at which node on the string the voltage is
tapped off to be fed into the output amplifier. The voltage is
tapped off by closing one of the switches connecting the string
to the amplifier. Because it is a string of resistors, it is
guaranteed monotonic.
Output Amplifier
The output buffer amplifier is capable of generating rail-to-rail
voltages on its output which gives an output range of 0 V to
V
DD
. It is capable of driving a load of 2 k in parallel with 1000
pF to GND. The source and sink capabilities of the output
amplifier can be seen in Figure 10 and Figure 11. The slew rate
is 1.5 V/s with a half-scale settling time of 8 s with the output
unloaded.
SERIAL INTERFACE
The AD5628/AD5648/AD5668 has a three-wire serial interface
(SYNC, SCLK and DIN), which is compatible with SPI, QSPI
and MICROWIRE interface standards as well as most DSPs. See
Figure 2 for a timing diagram of a typical write sequence.
The write sequence begins by bringing the SYNC line low. Data
from the DIN line is clocked into the 32-bit shift register on the
falling edge of SCLK. The serial clock frequency can be as high
as 50 MHz, making the AD5628/AD5648/AD5668 compatible
with high speed DSPs. On the 32nd falling clock edge, the last
data bit is clocked in and the programmed function is executed
Preliminary Technical Data
AD5628/AD5648/AD5668
Rev. PrA| Page 17 of 24
(i.e., a change in DAC register contents and/or a change in the
mode of operation). At this stage, the SYNC line may be kept
low or be brought high. In either case, it must be brought high
for a minimum of 50 ns before the next write sequence so that a
falling edge of SYNC can initiate the next write sequence. Since
the SYNC buffer draws more current when V
IN
= 2V than it
does when V
IN
= 0.8 V, SYNC should be idled low between
write sequences for even lower power operation of the part. As
is mentioned above, however, it must be brought high again just
before the next write sequence.
Input Shift Register
The input shift register is 32 bits wide (see Figure 24). The first
four bits are "don't cares." The next four bits are the Command
bits C3-C0, (see Table 1) followed by the 4-bit DAC address
A3-A0, (see Table 2) and finally the 16/14/12-bit data word.
The data word comprises the 16- 14- 12- bit input code
followed by 4, 6 or 8 don't care bits, the AD5668, AD5648 and
AD5628 respectively. See figure 24, 25, 26. These data bits are
transferred to the DAC register on the 32nd falling edge of
SCLK.
ADDRESS BITS
COMMAND BITS
C3
C2
C1
C0
A3
A2
A1
A0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
X
X
X
X
DB0 (LSB)
Figure 24 AD5668. Input Register Contents
ADDRESS BITS
COMMAND BITS
C3
C2
C1
C0
A3
A2
A1
A0
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
X
X
X
X
X
X
DB0 (LSB)
Figure 25. AD5648. Input Register Contents
ADDRESS BITS
COMMAND BITS
C3
C2
C1
C0
A3
A2
A1
A0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
X
X
X
X
X
X
X
X
DB0 (LSB)
Figure 26. AD5628 Input Register Contents
AD5628/AD5648/AD5668
Preliminary Technical Data
Rev.PrA | Page 18 of 24
Table 1. Command Definition
Table2. Address Command
SYNC Interrupt
In a normal write sequence, the SYNC line is kept low for 32 falling edges of SCLK and the DAC is updated on the 32nd falling edge and
rising edge of SYNC . However, if SYNC is brought high before the 32nd falling edge this acts as an interrupt to the write sequence. The
shift register is reset and the write sequence is seen as invalid. Neither an update of the DAC register contents or a change in the operating
mode occurs--see Figure 27.
DB31
DB0
SCLK
SYNC
DIN
DB31
DB0
VALID WRITE SEQUENCE, OUTPUT UPDATES
INVALID WRITE SEQUENCE:
SYNC HIGH BEFORE 32ND FALLING EDGE
ON THE 32ND FALLING EDGE
Figure 27. SYNC Interrupt Facility
Command
C3 C2 C1 C0
0
0
0
0
Write to Input Register n
0
0
0
1
Update DAC Register n
0
0
1
0
Write to Input Register n,
Update All
0
0
1
1
Write to and Update DAC
channel n
0 1 0 0 Power
Down
DAC
(Power-up)
0
1
0
1
Load Clear Code Register
0 1 1 0 Load
LDAC
Register
(LDAC overwrite)
0 1 1 1 Reset
(Power-on-Reset)
1 0 0 0 REF
Setup
Register
1 0 0 1 Reserved
* * * * Reserved
1 1 1 1 Reserved
ADDRESS (n)
A3
A2 A1 A0
0
0 0 0 DAC
A
0
0 0 1 DAC
B
0
0 1 0 DAC
C
0
0 1 1 DAC
D
0
1 0 0 DAC
E
0
1 0 1 DAC
F
0
1 1 0 DAC
G
0
1 1 1 DAC
H
1
1 1 1 All
DACs
Preliminary Technical Data
AD5628/AD5648/AD5668
Rev. PrA| Page 19 of 24
Reference Setup External to Internal
The on-board reference is turned off at power-up by default. This allows the use of an external reference. The AD5628/48/68 have an on-
chip reference with an internal gain of two. The AD56x8-1 has a 1.25V 10ppm/C max reference and the AD56x8-2,-3 have a 2.5V
10ppm/C max reference. The on-board reference can be turned on/off through a software executable REF Setup function, see Table 3.
Command 1000 is reserved for this REF Setup function, see Table 1. The reference mode is software-programmable by setting a bit
(DB0) in the REF Setup register.
Table 4 shows how the state of the bits corresponds to the mode of operation of the device.
REF Setup Register
(DB0)
Action
0 Ref
Off
(Default)
1 Ref
On
Table 3. Reference Set-up Register
MSB
LSB
DB31
DB28
DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB1-
DB19
DB0
x 1 0 0 0 x x x x x
1/0
Don't
Cares
COMMAND BITS (C3-C0)
ADDRESS BITS (A3 A0) Don't
Cares
REF Setup
Register
Table 4 32-Bit Input Shift Register Contents for Reference Setup Function
Power-On-Reset
The AD5628/AD5648/AD5668 family contains a power-on-reset circuit that controls the output voltage during power-up. The
AD5628/AD5648/AD5668x-1/2 DAC output powers up to zero volts and the AD5668-3 DAC output powers up to midscale. The output
remains there until a valid write sequence is made to the DAC. This is useful in applications where it is important to know the state of the
output of the DAC while it is in the process of powering up.
There is also a software executable Reset function that will reset the DAC to the Power-on -Reset code. Command 0111 is reserved for
this Reset function, see Table 1.
Power-Down Modes
The AD5628/AD5648/AD5668 contains four separate modes of operation. Command 0100 is reserved for the Power-Down function,
see Table 1. These modes are software-programmable by setting two bits (DB9 and DB8) in the control register.
Table 5 shows how the state of the bits corresponds to the mode of operation of the device. Any or all DACs, (DacH to DacA) may be
powered down to the selected mode by setting the corresponding 8 bits (DB7 to DB0) to a "1". See Table 6 for contents of the Input
Shift Register during power down/up operation.
When both bits are set to 0, the part works normally with its normal power consumption of 250 A at 5 V. However, for the three power-
AD5628/AD5648/AD5668
Preliminary Technical Data
Rev.PrA | Page 20 of 24
down modes, the supply current falls to 200 nA at 5 V (50 nA at 3 V). Not only does the supply current fall but the output stage is also
internally switched from the output of the amplifier to a resistor network of known values. This has the advantage that the output
impedance of the part is known while the part is in power-down mode. There are three different options. The output is connected
internally to GND through a 1 k resistor, a 100 k resistor or it is left open-circuited (Tri-State). The output stage is illustrated in
figure 24.
The bias generator of selected DAC(s), the output amplifier, the resistor string and other associated linear circuitry are all shut down
when the power-down mode is activated. However, the contents of the DAC register are unaffected when in power-down. The time to exit
power-down is typically (2.5 s for V
DD
= 5 V and 5 s for V
DD
= 3 V). See Figure 20 for a plot.
Any combination of DACs can be powered up by setting PD1 and PD0 to "0" (normal operation). Output powers-up to value in input
register (/LDAC Low) or to value in DAC register before Power-Down (/LDAC High).
DB9
DB8
Operating Mode
0
0
Normal Operation
Power Down Modes
0
1
1 k to GND
1
0
100 k to GND
1
1
Tri State
Table 5. Modes of Operation for the AD5628/AD5648/AD5668
MSB
LSB
DB31
DB28
DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB10--
DB19
DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
x 0 1 0 0 x x x x x
PD1
PD0
DacH
DacG DacF DacE DacD DacC DacB DacA
Don't
Cares
COMMAND BITS (C2-C0)
ADDRESS BITS (A3 A0)
Don't cares
Don't
Cares
Power
Down Mode
Power Down/Up Channel Selection Set Bit to a "1" to select
Table 6. 32-Bit Input Shift Register Contents for Power Down/Up Function
Preliminary Technical Data
AD5628/AD5648/AD5668
Rev. PrA| Page 21 of 24
Clear Code Register
The AD5628/AD5648/AD5668 gives the option of clearing any one or all DAC channels to 0, midscale or fullscale code. Command 0101
is reserved for the Clear Code function. See Table1. These clear code values are software-programmable by setting two bits (DB1 and
DB0) in the control register.
Table shows how the state of the bits corresponds to the clear code values of the device. Upon execution of the hardware /CLR pin
(active LOW), the DAC output is cleared to the clear code register value (default setting is zero). See Table 8 for contents of the Input
Shift Register during the Clear Code Register operation. The part will exit Clear code mode on the 32
nd
falling edge of the next write to
the part.
Clear Code Register
CR1
CR0
Clears to code
0 0 0000h
0 1 8000h
1 0 FFFFh
1 1 No
operation
Table 7. Clear Code Register
MSB
LSB
DB31
DB28
DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB2-
DB19
DB1
DB0
X 0 1 0 1 1/0 1/0 1/0 1/0 x 1/0
1/0
Don't
Cares
COMMAND BITS (C2-C0)
ADDRESS BITS (A3 A0)
Don't
Cares
Clear Code
Register (CR1-
CR0)
Table 8. 32-Bit Input Shift Register Contents Clear Code Function
LDAC Function
The outputs of all DACs may be updated simultaneously using the hardware /LDAC pin.
Synchronous LDAC:
The DAC registers are updated after new data is read in on the falling edge of the 32nd SCLK pulse. LDAC can be
permanently low or pulsed as in Figure 1.
Asynchronous LDAC:
The outputs are not updated at the same time that the input registers are written to. When LDAC goes low, the
DAC registers are updated with the contents of the input register.
The outputs of all DACs may be updated simultaneously using the /LDAC function, with the added functionality of selecting through
software any number of DAC channels to synchronize.
Writing to the DAC using command 0110, the hardware /LDAC pin can be overwritten by setting the bits of the 8-bit /LDAC register
(DB7-DB0) . SeeTable 9 for the /LDAC mode of operation. The default for each channel is "0" ie /LDAC pin works normally. Setting the
bits to a "1" means the DAC channel will be updated regardless of the state of the /LDAC pin. This gives the added benefit of allowing
any combination of channels to be synchronously updated. See Table 10 for contents of the Input Shift Register during the /LDAC
overwrite mode of operation.
AD5628/AD5648/AD5668
Preliminary Technical Data
Rev.PrA | Page 22 of 24
Load DAC OVERWRITE
/LDACBITS (DB7-
DB0)
/LDAC PIN
/LDAC Operation
0 1/0
Determined by
/LDAC pin
1
x Don't Care
DAC channels will
update, overwriting
the /LDAC pin
Table 9. LDAC Overwrite Definition
MSB
LSB
DB31
DB28
DB27
DB2
6
DB2
5
DB2
4
DB2
3
DB2
2
DB2
1
DB2
0
DB8
DB19
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
x 0 1 1 0 x x x x x DacH
DacG
DacF DacE DacD DacC DacB DacA
Don't
Cares
COMMAND BITS (C2-C0)
ADDRESS BITS (A3 A0)
Don't cares
Don't
Cares
Setting /LDAC bit to "1" overwrites /LDAC pin
Table 10. 32-Bit Input Shift Register Contents for /LDAC Overwrite Function
Power Supply Bypassing and Grounding
When accuracy is important in a circuit it is helpful to carefully
consider the power supply and ground return layout on the
board. The printed circuit board containing the
AD5628/AD5648/AD5668 should have separate analog and
digital sections, each having its own area of the board. If the
AD5628/AD5648/AD5668 is in a system where other devices
require an AGND to DGND connection, the connection should
be made at one point only. This ground point should be as close
as possible to the AD5628/AD5648/AD5668.
The power supply to the AD5628/AD5648/AD5668 should be
bypassed with 10 F and 0.1 F capacitors. The capacitors
should be physically as close as possible to the device with the
0.1 F capacitor ideally right up against the device. The 10 F
capacitors are the tantalum bead type. It is important that the
0.1 F capacitor has low Effective Series Resistance (ESR) and
Effective Series Inductance (ESI), e.g., common ceramic types
of capacitors. This 0.1 F capacitor provides a low impedance
path to ground for high frequencies caused by transient
currents due to internal logic switching.
The power supply line itself should have as large a trace as
possible to provide a low impedance path and reduce glitch
effects on the supply line. Clocks and other fast switching
digital signals should be shielded from other parts of the board
by digital ground. Avoid crossover of digital and analog signals
if possible. When traces cross on opposite sides of the board,
ensure that they run at right angles to each other to reduce
feedthrough effects through the board. The best board layout
technique is the microstrip technique where the component
side of the board is dedicated to the ground plane only and the
signal traces are placed on the solder side. However, this is not
always possible with a two-layer board.
Preliminary Technical Data
AD5628/AD5648/AD5668
Rev. PrA| Page 23 of 24
OUTLINE DIMENSIONS
14
8
7
1
0.201 (5.10)
0.193 (4.90)
0.256 (6.50)
0.246 (6.25)
0.177 (4.50)
0.169 (4.30)
PIN 1
SEATING
PLANE
0.006 (0.15)
0.002 (0.05)
0.0118 (0.30)
0.0075 (0.19)
0.0256
(0.65)
BSC
0.0433
(1.10)
MAX
0.0079 (0.20)
0.0035 (0.090)
0.028 (0.70)
0.020 (0.50)
8
0
Figure 28. 14-Thin Shrink Small Outline Package [TSSOP]
(RU-14)
Dimensions shown in millimeters
16
9
8
1
0.201 (5.10)
0.193 (4.90)
0.256 (6.50)
0.246 (6.25)
0.177 (4.50)
0.169 (4.30)
PIN
1
SEATING
PLANE
0.006 (0.15)
0.002 (0.05)
0.0118 (0.30)
0.0075 (0.19)
0.0256
(0.65)
BSC
0.0433
(1.10)
MAX
0.0079 (0.20)
0.0035 (0.090)
0.028 (0.70)
0.020 (0.50)
8
0
Figure 29. 16-Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
ORDERING GUIDE
Model Bit
Power-On-Reset
Internal
Reference
Package
Option1
AD5628BRUZ-1 12
Zero
1.25V RU-14
AD5628BRUZ-2 12
Zero
2.5V RU-16
AD5628ARUZ-2 12
Zero
2.5V RU-16
AD5648BRUZ-1 14
Zero
1.25V RU-14
AD5648BRUZ-2 14
Zero
2.5V RU-16
AD5648ARUZ-2 14
Zero
2.5V RU-16
AD5668BRUZ-1 16
Zero
1.25V RU-14
AD5628/AD5648/AD5668
Preliminary Technical Data
Rev.PrA | Page 24 of 24
AD5668BRUZ-2 16
Zero
2.5V RU-16
AD5668BRUZ-3 16
Midscale
2.5V RU-16
AD5668ARUZ-2 16
Zero
2.5V RU-16
AD5668ARUZ-3 16
Midscale
2.5V RU-16
1 Thin Shrink Small Outline Package (TSSOP)
2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered
trademarks are the property of their respective companies.
Printed in the U.S.A.
PR05302-0-12/04(PrA)
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