Single, 12-/14-/16-Bit nanoDACTM with
5 ppm/C On-Chip Reference in SOT-23
AD5620/AD5640/AD5660
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
2005 Analog Devices, Inc. All rights reserved.
FEATURES
Low power, single nanoDACs
AD5660: 16 bits
AD5640: 14 bits
AD5620: 12 bits
12-bit accuracy guaranteed
On-chip, 1.25 V/2.5 V, 5 ppm/C reference
Tiny 8-lead SOT-23/MSOP packages
Power-down to 480 nA @ 5 V, 200 nA @ 3 V
3 V/5 V single power supply
Guaranteed 16-bit monotonic by design
Power-on reset to zero/midscale
3 power-down functions
Serial interface with Schmitt-triggered inputs
Rail-to-rail operation
SYNC interrupt facility
APPLICATIONS
Process control
Data acquisition systems
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
PRODUCT HIGHLIGHTS
1.
12-/14-/16-bit nanoDAC--12-bit accuracy guaranteed.
2.
On-chip, 1.25 V/2.5 V, 5 ppm/C reference.
3.
Available in 8-lead SOT-23 and 8-lead MSOP packages.
4.
Power-on reset to 0 V or midscale.
5.
10 s settling time.
RELATED DEVICE
Part No.
Description
AD5662
2.7 V to 5.5 V, 16-bit DAC in SOT-23, external
reference
FUNCTIONAL BLOCK DIAGRAM
AD5620/AD5640/AD5660
V
REFOUT
GND
REF(+)
V
DD
RESISTOR
NETWORK
POWER-DOWN
CONTROL LOGIC
DAC
REGISTER
POWER-ON
RESET
1.25/2.5V
REF
OUTPUT
BUFFER
16-BIT
DAC
INPUT
CONTROL
LOGIC
V
OUT
V
FB
SYNC
SCLK
DIN
04539-001
Figure 1.
GENERAL DESCRIPTION
The AD5620/AD5640/AD5660, members of the nanoDAC
family of devices, are low power, single, 12-/14-/16-bit, buffered
voltage-out DACs and are guaranteed monotonic by design.
The AD5620/AD5640/AD5660-1 parts include an internal,
1.25 V, 5 ppm/C reference, giving a full-scale output voltage
range of 2.5 V. The AD5620/AD5640/AD5660-2-3 parts include
an internal, 2.5 V, 5 ppm/C reference, giving a full-scale output
voltage range of 5 V. The reference associated with each part is
available at the V
REFOUT
pin.
The parts incorporate a power-on reset circuit to ensure that the
DAC output powers up to 0 V (AD5620/AD5640/AD5660-1-2)
or midscale (AD5620-3 and AD5660-3) and remains there until
a valid write takes place. The parts contain a power-down
feature that reduces the current consumption of the device to
480 nA at 5 V and provides software-selectable output loads
while in power-down mode. The power consumption is
2.5 mW at 5 V, reducing to 1 W in power-down mode.
The AD5620/AD5640/AD5660 on-chip precision output
amplifier allows rail-to-rail output swing to be achieved. For
remote sensing applications, the output amplifier's inverting
input is available to the user. The AD5620/AD5640/AD5660 use
a versatile 3-wire serial interface that operates at clock rates up
to 30 MHz and is compatible with standard SPI, QSPITM,
MICROWIRETM, and DSP interface standards.
AD5620/AD5640/AD5660
Rev. A | Page 2 of 24
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Product Highlights ........................................................................... 1
Related Device................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
AD5620/AD5640/AD5660-2-3 .................................................. 3
AD5620/AD5640/AD5660-1 ...................................................... 5
Timing Characteristics ................................................................ 7
Absolute Maximum Ratings............................................................ 8
ESD Caution.................................................................................. 8
Pin Configurations and Function Descriptions ........................... 9
Typical Performance Characteristics ........................................... 10
Terminology .................................................................................... 16
Theory of Operation ...................................................................... 17
D/A Section................................................................................. 17
Resistor String ............................................................................. 17
Internal Reference ...................................................................... 17
Output Amplifier........................................................................ 17
Serial Interface ............................................................................ 17
Input Shift Register .................................................................... 18
SYNC Interrupt .......................................................................... 18
Power-On Reset.......................................................................... 19
Power-Down Modes .................................................................. 19
Microprocessor Interfacing....................................................... 19
Applications..................................................................................... 21
Using an REF19x as a Power Supply for the
AD5620/AD5640/AD5660 ....................................................... 21
Bipolar Operation Using the AD5660 ..................................... 21
Using the AD5660 as an Isolated, Programmable,
4 to 20 mA Process Controller ................................................. 21
Using the AD5620/AD5640/AD5660
with a Galvanically Isolated Interface...................................... 22
Power Supply Bypassing and Grounding................................ 22
Outline Dimensions ....................................................................... 23
AD5620 Ordering Guide........................................................... 23
AD5640 Ordering Guide........................................................... 24
AD5660 Ordering Guide........................................................... 24
REVISION HISTORY
9/05--Rev. 0 to Rev. A
Changes to Specifications ................................................................ 5
Changes to Outline Dimensions................................................... 23
7/05--Revision 0: Initial Version
AD5620/AD5640/AD5660
Rev. A | Page 3 of 24
SPECIFICATIONS
AD5620/AD5640/AD5660-2-3
V
DD
= 4.5 V to 5.5 V, R
L
= 2 k to GND, C
L
= 200 pF to GND, C
REFOUT
= 100 nF; all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 1.
Parameter A
Grade
1
B
Grade
1
C
Grade
1
Unit
Conditions/Comments
STATIC PERFORMANCE
2
AD5660
Resolution 16
16
16
Bits
min
Relative Accuracy
32
16
16
LSB max
Differential Nonlinearity
1
1
1
LSB max
Guaranteed monotonic by design
AD5640
Resolution 14
14
14
Bits
min
Relative Accuracy
8
4
4
LSB max
Differential Nonlinearity
1
1
1
LSB max
Guaranteed monotonic by design
AD5620
Resolution 12
12
12
Bits
min
Relative Accuracy
6
1
1
LSB max
Differential Nonlinearity
1
1
1
LSB max
Guaranteed monotonic by design
Zero-Code Error
2
2
2
mV typ
All 0s loaded to DAC register
10
10
10
mV
max
Offset Error
10
10
10
mV max
Full-Scale Error
-0.15
-0.15
-0.15
% FSR typ
All 1s loaded to DAC register
-1
-1
-1
% FSR max
Gain Error
1.5
1.5
1.5
% FSR max
Zero-Code Error Drift
2
2
2
V/C typ
Gain Temperature Coefficient
2.5
2.5
2.5
ppm typ
Of FSR/C
DC Power Supply Rejection Ratio
-75
-75
-75
dB typ
DAC code = midscale; V
DD
= 5 V 10%
OUTPUT CHARACTERISTICS
3
Output Voltage Range
0
0
0
V min
V
DD
V
DD
V
DD
V
max
Output Voltage Settling Time
8
8
8
s typ
to scale change settling to 2 LSB
10
10
10
s
max
R
L
= 2 k; 0 pF < C
L
< 200 pF
Slew Rate
1.5
1.5
1.5
V/s typ
to scale
Capacitive Load Stability
2
2
2
nF typ
R
L
=
10
10
10
nF
typ
R
L
= 2 k
Output Noise Spectral Density
80
80
80
nV/Hz typ
DAC code = midscale, 10 kHz
Output Noise (0.1 Hz to 10 Hz)
45
45
45
V p-p typ
DAC code = midscale
Digital-to-Analog Glitch Impulse
5
5
5
nV-s typ
1 LSB change around major carry
Digital Feedthrough
0.1
0.1
0.1
nV-s typ
DC Output Impedance
0.5
0.5
0.5
typ
Short-Circuit Current
30
30
30
mA typ
V
DD
= 5 V
Power-Up Time
5
5
5
s typ
Coming out of power-down mode; V
DD
= 5 V
REFERENCE OUTPUT
Output Voltage
2.495
2.495
2.495
V min
At ambient
2.505
2.505
2.505
V
max
Reference TC
3
10
10
5
ppm/C
typ
20
ppm/C
max
Output Impedance
2.8
2.8
2.8
k typ
AD5620/AD5640/AD5660
Rev. A | Page 4 of 24
Parameter A
Grade
1
B
Grade
1
C
Grade
1
Unit
Conditions/Comments
LOGIC INPUTS
3
Input Current
2
2
2
A max
All digital inputs
V
INL
, Input Low Voltage
0.8
0.8
0.8
V max
V
DD
= 5 V
V
INH
, Input High Voltage
2
2
2
V min
V
DD
= 5 V
Pin Capacitance
3
3
3
pF typ
POWER REQUIREMENTS
V
DD
4.5
4.5
4.5
V min
All digital inputs at 0 V or V
DD
5.5
5.5
5.5
V max
DAC active and excluding load current
I
DD
(Normal Mode)
V
DD
= 4.5 V to 5.5 V
0.55
0.55
0.55
mA typ
V
IH
= V
DD
and V
IL
= GND
V
DD
= 4.5 V to 5.5 V
1
1
1
mA max
V
IH
= V
DD
and V
IL
= GND
I
DD
(All Power-Down Modes)
V
DD
= 4.5 V to 5.5 V
0.48
0.48
0.48
A typ
V
IH
= V
DD
and V
IL
= GND
V
DD
= 4.5 V to 5.5 V
1
1
1
A max
V
IH
= V
DD
and V
IL
= GND
1
Temperature range is -15C to +105C, typical at 25C.
2
Linearity calculated using a reduced code range: AD5660 (Code 511 to Code 65024); AD5640 (Code 128 to Code 16256); AD5620 (Code 32 to Code 4064). Output
unloaded. Linearity tested with V
DD
= 5.5 V. If part is operated with a V
DD
< 5 V, the output is clamped to V
DD.
3
Guaranteed by design and characterization; not production tested.
AD5620/AD5640/AD5660
Rev. A | Page 5 of 24
AD5620/AD5640/AD5660-1
V
DD
1
= 2.7 V to 3.3 V, R
L
= 2 k to GND, C
L
= 200 pF to GND, C
REFOUT
= 100 nF; all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 2.
Parameter A
Grade
2
B
Grade
2
C
Grade
2
Unit
Conditions/Comments
STATIC PERFORMANCE
3
AD5660
Resolution 16
16
16
Bits
min
Relative Accuracy
32
16
16
LSB max
Differential Nonlinearity
1
1
1
LSB max
Guaranteed monotonic by design
AD5640
Resolution 14
14
14
Bits
min
Relative Accuracy
8
4
4
LSB max
Differential Nonlinearity
1
1
1
LSB max
Guaranteed monotonic by design
AD5620
Resolution 12
12
12
Bits
min
Relative Accuracy
6
1
1
LSB max
Differential Nonlinearity
1
1
1
LSB max
Guaranteed monotonic by design
Zero-Code Error
2
2
2
mV typ
All 0s loaded to DAC register
8
8
8
mV
max
Offset Error
9
9
9
mV max
Full-Scale Error
0.15
0.15
0.15
% FSR typ
All 1s loaded to DAC register
0.85
0.85
0.85
% FSR max
Gain Error
0.85
0.85
0.85
% FSR max
Zero-Code Error Drift
2
2
2
V/C typ
Gain Temperature Coefficient
2.5
2.5
2.5
ppm typ
Of FSR/C
DC Power Supply Rejection Ratio
-60
-60
-60
dB typ
DAC code = midscale; V
DD
= 3 V 10%
OUTPUT CHARACTERISTICS
4
Output Voltage Range
0
0
V min
V
DD
V
DD
V
DD
V
max
Output Voltage Settling Time
8
8
8
s typ
to scale change settling to 2 LSB
10
10
10
s
max
R
L
= 2 k; 0 pF < C
L
< 200 pF
Slew Rate
1.5
1.5
1.5
V/s typ
to scale
Capacitive Load Stability
2
2
2
nF typ
R
L
=
10
10
10
nF
typ
R
L
= 2 k
Output Noise Spectral Density
80
80
80
nV/Hz typ
DAC code = midscale, 10 kHz
Output Noise (0.1 Hz to 10 Hz)
20
20
20
V p-p typ
DAC code = midscale
Digital-to-Analog Glitch Impulse
5
5
5
nV-s typ
1 LSB change around major carry
Digital Feedthrough
0.1
0.1
0.1
nV-s typ
DC Output Impedance
0.5
0.5
0.5
typ
Short-Circuit Current
30
30
30
mA typ
V
DD
= 3 V
Power-Up Time
5
5
5
s typ
Coming out of power-down mode; V
DD
= 3 V
REFERENCE OUTPUT
Output Voltage
1.247
1.247
1.247
V min
At ambient
1.253
1.253
1.253
V
max
Reference TC
4
10
10
5
ppm/C
typ
25
ppm/C
max
Output Impedance
2.8
2.8
2.8
k typ
AD5620/AD5640/AD5660
Rev. A | Page 6 of 24
Parameter A
Grade
2
B
Grade
2
C
Grade
2
Unit
Conditions/Comments
LOGIC INPUTS
4
Input Current
1
1
1
A max
All digital inputs
V
INL
, Input Low Voltage
0.8
0.8
0.8
V max
V
DD
= 3 V
V
INH
, Input High Voltage
2
2
2
V min
V
DD
= 3 V
Pin Capacitance
3
3
3
pF max
POWER REQUIREMENTS
V
DD
2.7
2.7
2.7
V min
All digital inputs at 0 V or V
DD
3.3
3.3
3.3
V max
DAC active and excluding load current
I
DD
(Normal Mode)
V
DD
= 2.7 V to 3.3 V
0.55
0.55
0.55
mA typ
V
IH
= V
DD
and V
IL
= GND
V
DD
= 2.7 V to 3.3 V
0.65
0.65
0.65
mA max
V
IH
= V
DD
and V
IL
= GND
I
DD
(All Power-Down Modes)
V
DD
= 2.7 V to 3.3 V
0.2
0.2
0.2
A typ
V
IH
= V
DD
and V
IL
= GND
V
DD
= 2.7 V to 3.3 V
0.25
0.25
0.25
A max
V
IH
= V
DD
and V
IL
= GND
1
Part is functional with V
DD
up to 5.5 V.
2
Temperature range is -15C to +105C, typical at +25C.
3
Linearity calculated using a reduced code range: AD5660 (Code 511 to Code 65024); AD5640 (Code 128 to Code 16256); AD5620 (Code 32 to Code 4064). Output
unloaded.
4
Guaranteed by design and characterization; not production tested.
AD5620/AD5640/AD5660
Rev. A | Page 7 of 24
TIMING CHARACTERISTICS
All input signals are specified with tr = tf = 1 ns/V (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2. See Figure 2.
V
DD
= 2.7 V to 5.5 V; all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 3.
Limit
at
T
MIN
, T
MAX
Parameter
V
DD
= 2.7 V to 3.6 V
V
DD
= 3.6 V to 5.5 V
Unit
Conditions/Comments
t
1
1
50
33
ns min
SCLK cycle time
t
2
13
13
ns min
SCLK high time
t
3
13
13
ns min
SCLK low time
t
4
13
13
ns min
SYNC to SCLK falling edge set-up time
t
5
5
5
ns min
Data set-up time
t
6
4.5
4.5
ns min
Data hold time
t
7
0
0
ns min
SCLK falling edge to SYNC rising edge
t
8
50
33
ns min
Minimum SYNC high time
t
9
13
13
ns min
SYNC rising edge to SCLK fall ignore
t
10
0
0
ns min
SCLK falling edge to SYNC fall ignore
1
Maximum SCLK frequency is 30 MHz at V
DD
= 3.6 V to 5.5 V and 20 MHz at V
DD
= 2.7 V to 3.6 V.
DIN
LSB = DB0
MSB = DB23 FOR AD5660;
MSB = DB15 FOR AD5620/AD5640
SYNC
SCLK
MSB
LSB
t
9
t
10
t
4
t
3
t
2
t
7
t
6
t
5
t
1
t
8
04539-002
Figure 2. Serial Write Operation
AD5620/AD5640/AD5660
Rev. A | Page 8 of 24
ABSOLUTE MAXIMUM RATINGS
T
A
= 25C, unless otherwise noted.
Table 4.
Parameter Rating
V
DD
to GND
-0.3 V to +7 V
V
OUT
to GND
-0.3 V to V
DD
+ 0.3 V
V
FB
to GND
-0.3 V to V
DD
+ 0.3 V
V
REFOUT
to GND
-0.3 V to V
DD
+ 0.3 V
Digital Input Voltage to GND
-0.3 V to V
DD
+ 0.3 V
Operating Temperature Range
Industrial
-15C to +105C
Storage Temperature Range
-65C to +150C
Junction Temperature (T
J
max)
150C
Power Dissipation
(T
J
max - T
A
)/
JA
SOT-23 Package (4-Layer Board)
JA
Thermal Impedance
119C/W
MSOP Package (4-Layer Board)
JA
Thermal Impedance
141C/W
JC
Thermal Impedance
44C/W
Reflow Soldering Peak Temperature
SnPb 240C
Pb-Free
260C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
AD5620/AD5640/AD5660
Rev. A | Page 9 of 24
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
SYNC
04539-003
V
DD
1
V
REFOUT
2
V
FB
3
V
OUT
4
GND
8
DIN
7
SCLK
6
5
AD5620/
AD5640/
AD5660
TOP VIEW
(Not to Scale)
Figure 3. SOT-23 Pin Configuration
SYNC
04539-004
V
DD
1
V
REFOUT
2
V
FB
3
V
OUT
4
GND
8
DIN
7
SCLK
6
5
AD5620/
AD5640/
AD5660
TOP VIEW
(Not to Scale)
Figure 4. MSOP Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
V
DD
Power Supply Input. These parts can operate from 2.7 V to 5.5 V. V
DD
should be decoupled to GND.
2
V
REFOUT
Reference Voltage Output.
3
V
FB
Feedback Connection for the output amplifier. V
FB
should be connected to V
OUT
for normal operation.
4
V
OUT
Analog Output Voltage from DAC. The output amplifier has rail-to-rail operation.
5
SYNC
Level-Triggered Control Input (Active Low). This is the frame synchronization signal for the input data. When
SYNC goes low, it enables the input shift register and data is transferred in on the falling edges of the following
clocks. The DAC is updated following the 24
th
clock cycle for the AD5660 and the 16
th
clock cycle for
AD5620/AD5640 unless SYNC is taken high before this edge. In this case, the rising edge of SYNC acts as an
interrupt, and the write sequence is ignored by the DAC.
6
SCLK
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data
can be transferred at rates up to 30 MHz.
7
DIN
Serial Data Input. The AD5660 has a 24-bit shift register, and the AD5620/AD5640 have a 16 -bit shift register.
Data is clocked into the register on the falling edge of the serial clock input.
8
GND
Ground Reference Point for all circuitry on the part.
AD5620/AD5640/AD5660
Rev. A | Page 10 of 24
TYPICAL PERFORMANCE CHARACTERISTICS
CODE
INL E
RROR (LS
B
)
10
8
0
10
6
8
4
6
2
4
2
65000
60000
55000
50000
45000
40000
35000
30000
25000
20000
15000
10000
5000
0
V
DD
= 5V
V
REFOUT
= 2.5V
T
A
= 25C
04539-005
Figure 5. INL--AD5660-2/AD5660-3
CODE
INL E
RROR (LS
B
)
4
3
4
3
2
2
1
1
0
16250
15000
13750
12500
11250
10000
8750
7500
6250
5000
3750
2500
1250
0
V
DD
= 5V
V
REFOUT
= 2.5V
T
A
= 25C
04539-006
Figure 6. INL--AD5640-2/AD5640-3
CODE
INL E
RROR (LS
B
)
1.0
0.8
0
1.0
0.8
0.6
0.6
0.4
0.2
0.4
0.2
0
1000
500
2000
1500
3500
3000
2500
4000
V
DD
= 5V
V
REFOUT
= 2.5V
T
A
= 25C
04539-007
Figure 7. INL--AD5620-2/AD6520-3
CODE
DNL E
RROR (LS
B
)
1.0
0.8
0
1.0
0.6
0.8
0.4
0.6
0.2
0.4
0.2
65000
60000
55000
50000
45000
40000
35000
30000
25000
20000
15000
10000
5000
0
V
DD
= 5V
V
REFOUT
= 2.5V
T
A
= 25C
04539-008
Figure 8. DNL--AD5660-2/AD5660-3
CODE
DNL E
RROR (LS
B
)
0.5
0.4
0
0.5
0.3
0.4
0.2
0.3
0.1
0.2
0.1
16250
15000
13750
12500
11250
10000
8750
7500
6250
5000
3750
2500
1250
0
V
DD
= 5V
V
REFOUT
= 2.5V
T
A
= 25C
04539-009
Figure 9. DNL--AD5640-2/AD5640-3
CODE
DNL E
RROR (LS
B
)
0.20
0.15
0
0.20
0.15
0.10
0.10
0.05
0.05
0
1000
500
2000
1500
3500
3000
2500
4000
V
DD
= 5V
V
REFOUT
= 2.5V
T
A
= 25C
04539-010
Figure 10. DNL--AD5620-2/AD6520-3
AD5620/AD5640/AD5660
Rev. A | Page 11 of 24
CODE
INL E
R
ROR (LS
B
)
10
8
4
6
2
0
4
2
6
8
10
65000
60000
55000
50000
45000
40000
35000
30000
25000
20000
15000
10000
5000
0
04539-017
V
DD
= 3V
V
REFOUT
= 1.25V
T
A
= 25
C
Figure 11. INL--AD5660-1
CODE
INL E
RROR (LS
B
)
4
4
16250
15000
13750
12500
11250
10000
8750
7500
6250
5000
3750
2500
1250
0
04539-018
3
2
1
0
1
2
3
V
DD
= 3V
V
REFOUT
= 1.25V
T
A
= 25
C
Figure 12. INL--AD5640-1
CODE
INL E
RROR (LS
B
)
1.0
1.0
0
500
1000
1500
2000
2500
3000
3500
4000
04539-019
0
0.8
0.6
0.4
0.2
0.2
0.4
0.6
0.8
V
DD
= 3V
V
REFOUT
= 1.25V
T
A
= 25
C
Figure 13. INL--AD5620-1
CODE
DNL E
RROR (LS
B
)
1.0
0.8
0.4
0.6
0.2
0
0.4
0.2
0.6
0.8
1.0
65000
60000
55000
50000
45000
40000
35000
30000
25000
20000
15000
10000
5000
0
04539-020
V
DD
= 3V
V
REFOUT
= 1.25V
T
A
= 25
C
Figure 14. DNL--AD5660-1
CODE
DNL E
RROR (LS
B
)
0.5
0.5
16250
15000
13750
12500
11250
10000
8750
7500
6250
5000
3750
2500
1250
0
04539-021
0
0.4
0.3
0.2
0.1
0.1
0.2
0.3
0.4
V
DD
= 3V
V
REFOUT
= 1.25V
T
A
= 25
C
Figure 15. DNL--AD5640-1
CODE
DNL E
RROR (LS
B
)
0.20
0.20
0
500
1000
1500
2000
2500
3000
3500
4000
04539-025
0
0.15
0.10
0.05
0.05
0.10
0.15
V
DD
= 3V
V
REFOUT
= 1.25V
T
A
= 25
C
Figure 16. DNL--AD5620-1
AD5620/AD5640/AD5660
Rev. A | Page 12 of 24
TEMPERATURE (
C)
E
RROR (LS
B
)
10
4
6
8
2
10
8
6
4
2
0
15
25
5
45
65
85
105
04539-011
V
DD
= 5V
MAX INL
MAX DNL
MIN INL
MIN DNL
Figure 17. INL Error and DNL Error vs. Temperature
TEMPERATURE (
C)
E
R
ROR (% FS
R)
0.5
0.2
0.3
0.4
0.1
0.5
0.4
0.3
0.2
0.1
0
15
25
5
45
65
85
105
04539-012
V
DD
= 5V
GAIN ERROR
FULL-SCALE ERROR
Figure 18. Gain Error and Full-Scale Error vs. Temperature
TEMPERATURE (
C)
E
RROR (mV
)
2.5
1.5
0.5
3.5
2.5
1.5
0.5
15
25
5
45
65
85
105
04539-013
V
DD
= 5V
ZERO-CODE ERROR
OFFSET ERROR
Figure 19. Zero-Code and Offset Error vs. Temperature
I
DD
(mA)
NUMBE
R OF DE
V
I
CE
S
200
180
160
140
100
120
80
20
40
60
0
0.45
0.46
0.47
0.48
0.49
0.50
0.51
0.52
0.53
0.54
0.55
0.56
0.57
0.58
0.59
0.60
0.61
0.62
0.63
0.65
0.64
0.66
0.67
04539-014
V
DD
= 5V
T
A
= 25
C
V
DD
= 3.3V
Figure 20. I
DD
Histogram
CURRENT (mA)
E
RROR V
O
LTAGE
(V
)
0.50
0.40
0.50
0.40
0.30
0.20
0.10
0
0.10
0.20
0.30
10
8
6
4
2
0
2
4
8
6
10
04539-022
V
DD
= 3V
V
REFOUT
= 1.25V
V
DD
= 5V
V
REFOUT
= 2.5V
DAC LOADED WITH
ZERO-SCALE
SINKING CURRENT
DAC LOADED WITH
FULL-SCALE
SOURCING CURRENT
Figure 21. Headroom at Rails vs. Source and Sink
CURRENT (mA)
V
OUT
(V
)
6.00
5.00
4.00
3.00
2.00
1.00
1.00
0
30
20
10
0
10
20
30
04539-023
V
DD
= 5V
V
REFOUT
= 2.5V
T
A
= 25
C
ZERO SCALE
FULL SCALE
MIDSCALE
1/4 SCALE
3/4 SCALE
Figure 22. Source and Sink Capability--AD5660-2/AD5660-3
AD5620/AD5640/AD5660
Rev. A | Page 13 of 24
CURRENT (mA)
V
OUT
(V
)
4.00
1.00
0
1.00
2.00
3.00
30
20
10
0
10
20
30
04539-024
V
DD
= 3V
V
REFOUT
= 1.25V
T
A
= 25
C
ZERO SCALE
FULL SCALE
MIDSCALE
1/4 SCALE
3/4 SCALE
Figure 23. Source and Sink Capability--AD5660-1
CODE
I
DD
(mA)
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
512
20512
10512
30512
40512
50512
60512
04539-015
T
A
= 25
C
V
DD
= 3V
V
DD
= 5V
Figure 24. Supply Current vs. Code
V
LOGIC
(V)
I
DD
(
A)
1400
1200
1000
800
600
400
200
0
0
2
1
3
4
5
04539-016
T
A
= 25
C
V
DD
= 5V
V
DD
= 3V
Figure 25. Supply Current vs. Logic Input Voltage
04539-028
TIME BASE = 4
s/DIV
V
DD
= 5V
T
A
= 25
C
FULL-SCALE CODE CHANGE
0x0000 TO 0xFFFF
OUTPUT LOADED WITH 2k
AND 200pF TO GND
V
OUT
= 909mV/DIV
1
Figure 26. Full-Scale Settling Time, 5 V
04539-029
CH1 2.00V
CH3
100mV
CH2 2.00V
M40.0ms
CH1
V
OUT
V
DD
V
REF
3
1
2
Figure 27. Power-On Reset to 0 V--AD5660-2
04539-030
CH1 2.00V
CH3
200mV
CH2 2.00V
M20.0
s
CH1 1.88V
V
OUT
V
DD
V
REF
3
1
2
Figure 28. Power-On Reset to Midscale--AD5660-3
AD5620/AD5640/AD5660
Rev. A | Page 14 of 24
04539-031
CH1 1.20V
CH3
100mV
CH2 1.00V
M100
s
CH1 1.87V
V
OUT
V
DD
V
REF
3
1
2
Figure 29. Power-On Reset to 0 V--AD5660-1
04539-055
CH1 2.00V
CH3
50.0mV
M1.00
s
CH2 520mV
V
OUT
V
DD
= 3V
SCLK
3
1
Figure 30. Exiting Power-Down to Midscale
SAMPLE NUMBER
AMP
L
ITUDE
2.501250
2.501000
2.500750
2.500500
2.500250
2.500000
2.499750
2.499500
2.499250
2.498750
2.499000
2.498500
2.498250
2.498000
0
150 200 250
50
100
300
350 400 450 500 550
04539-032
V
DD
= 5V
V
REFOUT
= 2.5V
T
A
= 25
C
13nS/SAMPLE NUMBER
1LSB CHANGE AROUND MIDSCALE
(0x7FFF TO 0x8000)
GLITCH IMPULSE = 0.497nV-s
Figure 31. Digital-to-Analog Glitch Impulse--AD5660-2/AD5660-3
SAMPLE NUMBER
AMP
L
ITUDE
1.250800
1.250600
1.250400
1.250200
1.250000
1.249800
1.249600
1.249400
1.249200
1.249000
1.248800
1.248600
1.248400
0
150 200 250
50
100
300
350 400 450 500 550
04539-033
V
DD
= 3V
V
REFOUT
= 1.25V
T
A
= 25
C
13nS/SAMPLE NUMBER
1LSB CHANGE AROUND MIDSCALE
(0x7FFF TO 0x8000)
GLITCH IMPULSE = 0.284nV-s
Figure 32. Digital-to-Analog Glitch Impulse--AD5660-1
SAMPLE NUMBER
AMP
L
ITUDE
2.500250
2.500200
2.500150
2.500100
2.500050
2.500000
2.499950
2.499900
2.499850
2.499800
2.499750
2.499700
2.499650
2.499600
0
150 200 250
50
100
300
350 400 450 500 550
04539-034
V
DD
= 5V
T
A
= 25
C
20nS/SAMPLE NUMBER
DAC LOADED WITH MIDSCALE
DIGITAL FEEDTHROUGH = 0.06nV-s
Figure 33. Digital Feedthrough
CAPACITANCE (nF)
TIME (
s)
16
14
12
10
8
6
4
0
1
2
3
4
5
6
7
9
8
10
04539-036
T
A
= 25
C
V
DD =
5V
V
DD =
3V
Figure 34. Settling Time vs. Capacitive Load
AD5620/AD5640/AD5660
Rev. A | Page 15 of 24
5s/DIV
10
V/D
I
V
1
04539-037
V
DD
= 5V
V
REFOUT
= 2.5V
T
A
= 25
C
DAC LOADED WITH MIDSCALE
Figure 35. 0.1 Hz to 10 Hz Output Noise--AD5660-2/AD5660-3
4s/DIV
5
V/D
I
V
1
04539-054
V
DD
= 3V
V
REFOUT
= 1.25V
T
A
= 25
C
DAC LOADED WITH MIDSCALE
Figure 36. 0.1 Hz to 10 Hz Output Noise--AD5660-1
FREQUENCY (Hz)
OUTPUT NOISE (
n
V
Hz)
800
0
100
200
300
400
500
600
700
100
10000
1000
100000
1000000
04539-038
V
DD
= 3V
V
REFOUT
= 1.25V
V
DD
= 5V
V
REFOUT
= 2.5V
T
A
= 25
C
MIDSCALE LOADED
Figure 37. Noise Spectral Density
AD5620/AD5640/AD5660
Rev. A | Page 16 of 24
TERMINOLOGY
Relative Accuracy
For the DAC, relative accuracy, or integral nonlinearity (INL), is
a measurement of the maximum deviation, in LSBs, from a
straight line passing through the endpoints of the DAC transfer
function. Figure 5 through Figure 7 show typical INL vs. code.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of 1 LSB maximum
ensures monotonicity. This DAC is guaranteed monotonic by
design. Figure 8 through Figure 10 show typical DNL vs. code.
Zero-Code Error
Zero-code error is a measurement of the output error when
zero code (0x0000) is loaded to the DAC register. Ideally, the
output should be 0 V. The zero-code error is always positive in
the AD5620/AD5640/AD5660, because the output of the DAC
cannot go below 0 V. It is due to a combination of the offset
errors in the DAC and the output amplifier. Zero-code error is
expressed in mV. Figure 19 shows a plot of zero-code error vs.
temperature.
Full-Scale Error
Full-scale error is a measurement of the output error when full-
scale code (0xFFFF) is loaded to the DAC register. Ideally, the
output should be V
DD
- 1 LSB. Full-scale error is expressed as a
percentage of the full-scale range. Figure 18 shows a plot of full-
scale error vs. temperature.
Gain Error
This is a measurement of the span error of the DAC. It is the
deviation in slope of the DAC transfer characteristic from the
ideal, expressed as a percentage of the full-scale range.
Zero-Code Error Drift
This is a measurement of the change in zero-code error with a
change in temperature. It is expressed in V/C.
Gain Temperature Coefficient
This is a measurement of the change in gain error with changes
in temperature. It is expressed in (ppm of full-scale range)/C.
Offset Error
Offset error is a measurement of the difference between V
OUT
(actual) and V
OUT
(ideal) expressed in mV in the linear region of
the transfer function. Offset error is measured on the AD5660
with Code 512 loaded into the DAC register. It can be negative
or positive.
DC Power Supply Rejection Ratio (PSRR)
This indicates how the output of the DAC is affected by changes
in the supply voltage. PSRR is the ratio of the change in V
OUT
to
the change in V
DD
for the full-scale output of the DAC. It is
measured in dB. V
REF
is held at 2.5 V, and V
DD
is varied by 10%.
Output Voltage Settling Time
This indicates the amount of time for the output of a DAC to
settle to a specified level for a to full-scale input change. It
is measured from the 24th falling edge of SCLK.
Digital-to-Analog Glitch Impulse
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nV-s
and is measured when the digital input code is changed by
1 LSB at the major carry transition (0x7FFF to 0x8000). See
Figure 31 and Figure 32.
Digital Feedthrough
Digital feedthrough is a measurement of the impulse injected
into the analog output of the DAC from the digital inputs of the
DAC, but is measured when the DAC output is not updated. It
is specified in nV-s and measured with a full-scale code change
on the data bus, that is, from all 0s to all 1s or vice versa.
Noise Spectral Density
This is a measurement of the internally generated random
noise. Random noise is characterized as a spectral density
(voltage per Hz). It is measured by loading the DAC to
midscale and measuring noise at the output. It is measured
in nV/Hz. Figure 37 shows a plot of noise spectral density.
AD5620/AD5640/AD5660
Rev. A | Page 17 of 24
THEORY OF OPERATION
D/A SECTION
The AD5620/AD5640/AD5660 DACs are fabricated on a CMOS
process. The architecture consists of a string DAC followed by an
output buffer amplifier. The parts include an internal 1.25 V/2.5 V,
5 ppm/C reference that is internally gained up by 2. Figure 38
shows a block diagram of the DAC architecture.
V
DD
R
R
V
OUT
GND
RESISTOR
STRING
REF (+)
REF ()
OUTPUT
AMPLIFIER
DAC REGISTER
04777-022
V
FB
Figure 38. DAC Architecture
Because the input coding to the DAC is straight binary, the ideal
output voltage is given by
=
N
REFOUT
OUT
D
V
V
2
2
where:
D is the decimal equivalent of the binary code that is loaded to
the DAC register.
0 to 4,095 for AD5620 (12 bit)
0 to 16,383 for AD5640 (14 bit)
0 to 65,535 for AD5660 (16 bit)
N is the DAC resolution.
R
R
R
R
R
TO OUTPUT
AMPLIFIER
04539-040
Figure 39. Resistor String
RESISTOR STRING
The resistor string section is shown in Figure 39. It is simply a
string of resistors, each of value R. The code loaded to the DAC
register determines at which node on the string the voltage is
tapped off to be fed into the output amplifier. The voltage is
tapped off by closing one of the switches connecting the
string to the amplifier. Because it is a string of resistors, it is
guaranteed monotonic.
INTERNAL REFERENCE
The AD5620/AD5640/AD5660-1 parts include an internal,
1.25 V, 5 ppm/C reference, giving a full-scale output voltage of
2.5 V. The AD5620/AD5640/AD5660-2-3 parts include an
internal, 2.5 V, 5 ppm/C reference, giving a full-scale output
voltage of 5 V. The reference associated with each part is
available at the V
REFOUT
pin. A buffer is required if the reference
output is used to drive external loads. It is recommended that a
100 nF capacitor is placed between the reference output and
GND for reference stability.
OUTPUT AMPLIFIER
The output buffer amplifier can generate rail-to-rail voltages on
its output, which gives an output range of 0 V to V
DD
. This output
buffer amplifier has a gain of 2 derived from a 50 k resistor
divider network in the feedback path. The inverting input of the
output amplifier is available to the user, allowing for remote
sensing. This V
FB
pin must be connected to V
OUT
for normal
operation. It can drive a load of 2 k in parallel with 1,000 pF
to GND. Figure 21 shows the source and sink capabilities of the
output amplifier. The slew rate is 1.5 V/s with a to full-
scale settling time of 10 s.
SERIAL INTERFACE
The AD5620/AD5640/AD5660 have a 3-wire serial interface
(SYNC, SCLK, and DIN) that is compatible with SPI, QSPI, and
MICROWIRE interface standards as well as most DSPs.
See Figure 2 for a timing diagram of a typical write sequence.
The write sequence begins by bringing the SYNC line low.
Data from the DIN line is clocked into the 16-bit shift register
(AD5620/AD5640) or the 24-bit shift register (AD5660) on the
falling edge of SCLK. The serial clock frequency can be as high
as 30 MHz, making the AD5620/AD5640/AD5660 compatible
with high speed DSPs. On the 16th falling clock edge (AD5620/
AD5640) or the 24th falling clock edge (AD5660), the last data
bit is clocked in and the programmed function is executed, that
is, a change in the DAC register contents and/or a change in the
mode of operation is executed. At this stage, the SYNC line can
be kept low or be brought high. In either case, it must be brought
high for a minimum of 33 ns before the next write sequence so
that a falling edge of SYNC can initiate the next write sequence.
Because the SYNC buffer draws more current when V
IN
= 2 V
than it does when V
IN
= 0.8 V, SYNC should be idled low between
write sequences for even lower power operation of the parts. As
is mentioned previously, however, SYNC must be brought high
again just before the next write sequence.
AD5620/AD5640/AD5660
Rev. A | Page 18 of 24
INPUT SHIFT REGISTER
AD5620/AD5640
The input shift register is 16 bits wide for the AD5620/AD5640
(see Figure 40 and Figure 41). The first two bits are control bits
that control which mode of operation the part is in (normal
mode or any of the three power-down modes). The next
14/12 bits, respectively, are the data bits. These are transferred
to the DAC register on the 16th falling edge of SCLK.
AD5660
The input shift register is 24 bits wide for the AD5660 (see
Figure 42). The first six bits are don't care bits. The next two are
control bits that control which mode of operation the part is in
(normal mode or any of the three power-down modes). For a more
complete description of the various modes, see the Power-Down
Modes section. The next 16 bits are the data bits. These are
transferred to the DAC register on the 24th falling edge of SCLK.
SYNC INTERRUPT
In a normal write sequence for the AD5660, the SYNC line is
kept low for at least 24 falling edges of SCLK, and the DAC is
updated on the 24th falling edge. However, if SYNC is brought
high before the 24th falling edge, this acts as an interrupt to the
write sequence. The shift register is reset, and the write sequence
is seen as invalid. Neither an update of the DAC register contents
nor a change in the operating mode occurs--see Figure 43.
Similarly, in a normal write sequence for the AD5620/AD5640,
the SYNC line is kept low for at least 16 falling edges of SCLK,
and the DAC is updated on the 16th falling edge. However, if
SYNC is brought high before the 16th falling edge, this acts as
an interrupt to the write sequence.
DATA BITS
DB15 (MSB)
DB0 (LSB)
PD1
PD0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
X
04539-041
Figure 40. AD5620 Input Register Contents
DATA BITS
DB15 (MSB)
DB0 (LSB)
PD1
PD0
D11
D10
D13
D12
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
04539-042
Figure 41. AD5640 Input Register Contents
DATA BITS
DB23 (MSB)
DB0 (LSB)
PD1
PD0
D15
D14
D13
D12
X
X
X
X
X
X
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
04539-043
Figure 42. AD5660 Input Register Contents
04539-044
DIN
MSB
MSB
LSB
LSB
INVALID WRITE SEQUENCE:
SYNC HIGH BEFORE 16
TH
/24
TH
FALLING EDGE
VALID WRITE SEQUENCE, OUTPUT UPDATES
ON THE 16
TH
/24
TH
FALLING EDGE
SYNC
SCLK
Figure 43. SYNC Interrupt Facility
AD5620/AD5640/AD5660
Rev. A | Page 19 of 24
POWER-ON RESET
The AD5620/AD5640/AD5660 family contains a power-on
reset circuit that controls the output voltage during power-up.
The AD5620/AD5640/AD5660-1-2 DAC output powers up to
0 V, and the AD5620/AD5660-3 DAC output powers up to
midscale. The output remains at this level until a valid write
sequence is made to the DAC, which is useful in applications
where it is important to know the state of the DAC output while
it is in the process of powering up.
POWER-DOWN MODES
The AD5620/AD5640/AD5660 have four separate modes of
operation. These modes are software-programmable by setting
two bits in the control register. Table 6 and Table 7 show how
the state of the bits corresponds to the operating mode of the
device.
Table 6. Modes of Operation for the AD5660
DB17
DB16
AD5660 Operating Mode
0
0
Normal operation
Power-down modes:
0
1
1 k to GND
1
0
100 k to GND
1
1
Three-state
Table 7. Modes of Operation for the AD5620/AD5640
DB15
DB14
AD5620/AD5640 Operating Mode
0
0
Normal operation
Power-down
modes:
0
1
1 k to GND
1
0
100 k to GND
1
1
Three-state
When both bits are set to 0, the part works normally with its
normal power consumption of 550 A at 5 V. However, for the
three power-down modes, the supply current falls to 480 nA
at 5 V (200 nA at 3 V). Not only does the supply current fall,
but the output stage is internally switched from the output of
the amplifier to a resistor network of known values. The
advantage is that the output impedance of the part is known
while the part is in power-down mode. There are three options:
the output is connected internally to GND through a
1 k or a 100 k resistor, or it is left open-circuited (three-
stated). The output stage is shown in Figure 44.
RESISTOR
NETWORK
V
OUT
RESISTOR
STRING DAC
04539-045
POWER-DOWN
CIRCUITRY
AMPLIFIER
Figure 44. Output Stage During Power-Down
The bias generator, output amplifier, reference, resistor string,
and other associated linear circuitry are all shut down when
power-down mode is activated. However, the contents of the
DAC register are unaffected when in power-down. The time to
exit power-down is typically 5 s for V
DD
= 5 V and V
DD
= 3 V.
See Figure 23.
MICROPROCESSOR INTERFACING
AD5660-to-Blackfin ADSP-BF53x Interface
Figure 45 shows a serial interface between the AD5660 and the
Blackfin ADSP-BF53x microprocessor. The ADSP-BF53x
processor family incorporates two dual-channel synchronous
serial ports, SPORT1 and SPORT0, for serial and multi-
processor communications. Using SPORT0 to connect to the
AD5660, the setup for the interface is as follows: DT0PRI drives
the DIN pin of the AD5660, while TSCLK0 drives the SCLK of
the part and SYNC is driven from TFS0.
AD5660
1
1
ADDITIONAL PINS OMITTED FOR CLARITY
TFS0
DTOPRI
TSCLK0
SYNC
DIN
SCLK
04539-046
ADSP-BF53x
1
Figure 45. AD5660-to-Blackfin ADSP-BF53x Interface
AD5620/AD5640/AD5660
Rev. A | Page 20 of 24
AD5660-to-68HC11/68L11 Interface
Figure 46 shows a serial interface between the AD5660 and the
68HC11/68L11 microcontroller. SCK of 68HC11/68L11 drives
the SCLK of AD5660, and the MOSI output drives the serial
data line of the DAC. The SYNC signal is derived from a port line
(PC7). The set-up conditions for correct operation of this
interface are as follows: The 68HC11/68L11 should be con-
figured so that its CPOL bit is 0, and its CPHA bit is 1. When
data is being transmitted to the DAC, the SYNC line is taken
low (PC7). When the 68HC11/68L11 is configured in this way,
data appearing on the MOSI output is valid on the falling edge
of SCK. Serial data from the 68HC11/68L11 is transmitted in
8-bit bytes with only eight falling clock edges occurring in the
transmit cycle. Data is transmitted MSB first. To load data to the
AD5660, PC7 is left low after the first eight bits are transferred, a
second serial write operation is performed to the DAC, and PC7
is taken high at the end of this procedure.
AD5660
1
1
ADDITIONAL PINS OMITTED FOR CLARITY
PC7
SCK
MOSI
SYNC
SCLK
DIN
04539-047
68HC11/68L11
1
Figure 46. AD5660-to-68HC11/68L11 Interface
AD5660-to-80C51/80L51 Interface
Figure 47 shows a serial interface between the AD5660 and the
80C51/80L51 microcontroller. The setup for the interface is as
follows: TxD of the 80C51/80L51 drives SCLK of the AD5660,
and RxD drives the serial data line of the part. The SYNC signal
is again derived from a bit-programmable pin on the port. In
this case, Port Line P3.3 is used. When data is to be transmitted
to the AD5660, P3.3 is taken low. The 80C51/80L51 transmit
data only in 8-bit bytes; therefore, only eight falling clock edges
occur in the transmit cycle. To load data to the DAC, P3.3 is left
low after the first eight bits are transmitted, and a second write
cycle is initiated to transmit the second byte of data. P3.3 is taken
high following the completion of this cycle. The 80C51/80L51
output the serial data LSB first; however, the AD5660 requires
its data with the MSB as the first bit received. The 80C51/80L51
transmit routine should take this into account.
80C51/80L51
1
AD5660
1
P3.3
TxD
RxD
SYNC
SCLK
DIN
04539-048
1
ADDITIONAL PINS OMITTED FOR CLARITY
Figure 47. AD5660-to-80C51/80L51 Interface
AD5660-to-MICROWIRE Interface
Figure 48 shows an interface between the AD5660 and any
MICROWIRE-compatible device. Serial data is shifted out on
the falling edge of the serial clock and is clocked into the
AD5660 on the rising edge of the SK.
MICROWIRE
1
AD5660
1
CS
SK
SO
SYNC
SCLK
DIN
04539-049
1
ADDITIONAL PINS OMITTED FOR CLARITY
Figure 48. AD5660-to-MICROWIRE Interface
AD5620/AD5640/AD5660
Rev. A | Page 21 of 24
APPLICATIONS
USING AN REF19x AS A POWER SUPPLY FOR THE
AD5620/AD5640/AD5660
Because the supply current required by the AD5620/AD5640/
AD5660 is extremely low, an alternative option is to use a REF19x
voltage reference (REF195 for 5 V or REF193 for 3 V) to supply
the required voltage to the part--see Figure 49. This is especially
useful if the power supply is quite noisy or if the system supply
voltages are at some value other than 5 V or 3 V, for example, 15 V.
The REF19x outputs a steady supply voltage for the AD5620/
AD5640/AD5660. If the low dropout REF195 is used, the current
it needs to supply to the AD5660 is 500 A. This is with no load
on the output of the DAC. When the DAC output is loaded, the
REF195 also must supply the current to the load. The total current
required (with a 5 k load on the DAC output) is
500 A + (5 V/5 k) = 1.5 mA
The load regulation of the REF195 is typically 2 ppm/mA,
which results in an error of 3 ppm (15 V) for the 1.5 mA
current drawn from it. This corresponds to a 0.197 LSB error
for the AD5660.
AD5660
3-WIRE
SERIAL
INTERFACE
SYNC
SCLK
DIN
15V
5V
V
OUT
= 0V TO 5V
REF195
04539-050
Figure 49. REF195 as the Power Supply to the AD5660
BIPOLAR OPERATION USING THE AD5660
The AD5660 is designed for single-supply operation, but a
bipolar output range is also possible using the circuit in
Figure 50. Figure 50 gives an output voltage range of 5 V.
Rail-to-rail operation at the amplifier output is achievable
using an AD820 or an OP295 as the output amplifier.
The output voltage for any input code can be calculated as
-
+
=
R1
R2
V
R1
R2
R1
D
V
V
DD
DD
O
65536
where D represents the input code in decimal (0 to 65,535).
When V
DD
= 5 V, R1 = R2 = 10 k,
V
5
65536
10
-
=
D
V
O
This results in an output voltage range of 5 V, with 0x0000
corresponding to a -5 V output and 0xFFFF corresponding to a
+5 V output.
R2
10k
04539-051
+5V
5V
AD820/
OP295
3-WIRE
SERIAL
INTERFACE
+5V
AD5660
V
DD
V
FB
V
OUT
R1
10k
5V
0.1
F
10
F
Figure 50. Bipolar Operation with the AD5660
USING THE AD5660 AS AN ISOLATED,
PROGRAMMABLE, 4 TO 20 mA PROCESS
CONTROLLER
In many process-control system applications, 2-wire current
transmitters are used to transmit analog signals through noisy
environments. These current transmitters use a zero-scale signal
current of 4 mA to power the signal conditioning circuitry of
the transmitter. The full-scale output signal in these transmitters
is 20 mA. The converse approach to process control can also be
used, in which a low-power, programmable current source is
used to control remotely located sensors or devices in the loop.
A circuit that performs this function is shown in Figure 51.
Using the AD5660 as the controller, the circuit provides a
programmable output current of 4 to 20 mA, proportional to
the digital code of the DAC. Biasing for the controller is provided
by the ADR02 and requires no external trim for two reasons: first,
the ADR02's tight initial output voltage tolerance, and second,
the low supply current consumption of both the AD8627 and
the AD5660. The entire circuit, including optocouplers, consumes
less than 3 mA from the total budget of 4 mA. The AD8627
regulates the output current to satisfy the current summation
at the noninverting node of the AD8627.
I
OUT
= 1/R7 (V
DAC
R3/R1 + V
REF
R3/R2)
For the values shown in Figure 51,
I
OUT
= 0.2435 A D + 4 mA
where D = 0 D 65,535, giving a full-scale output current of
20 mA when the AD5660's digital code equals 0xFFFF.
Offset trim at 4 mA is provided by P2, and P1 provides the circuit
gain trim at 20 mA. These two trims do not interact because
the noninverting input of the AD8627 is at virtual ground. The
Schottky diode, D1, is required in this circuit to prevent loop
supply power-on transients from pulling the noninverting input
of the AD8627 more than 300 mV below its inverting input.
Without this diode, such transients could cause phase reversal
AD5620/AD5640/AD5660
Rev. A | Page 22 of 24
of the AD8627 and possible latch-up of the controller. The loop
supply voltage compliance of the circuit is limited by the maximum
applied input voltage to the ADR02 and is from 12 V to 40 V.
04539-
052
SERIAL
LOAD
AD5660
V
LOOP
12V TO 36V
420mA
AD8627
R1
4.7k
R2
18.5k
P1
20mA
ADJUST
P2
4mA
ADJUST
R6
3.3k
R3
1.5k
D1
Q1
2N3904
R7
100
RL
ADR02
Figure 51. Programmable 4 to 20 mA Process Controller
USING THE AD5620/AD5640/AD5660 WITH A
GALVANICALLY ISOLATED INTERFACE
For process-control applications in industrial environments, it
is often necessary to use a galvanically isolated interface to
protect and isolate the controlling circuitry from hazardous
common-mode voltages that might occur in the area where
the DAC is functioning. The iCoupler provides isolation in
excess of 2.5 kV. The AD5620/AD5640/AD5660 use a 3-wire
serial logic interface; therefore, the ADuM1300 3-channel
digital isolator provides the required isolation (see Figure 52).
The power supply to the part also must be isolated, which is
done by using a transformer. On the DAC side of the trans-
former, a 5 V regulator provides the 5 V supply required for the
AD5620/AD5640/AD5660.
0.1
F
5V
REGULATOR
GND
04539-053
DIN
SYNC
SCLK
POWER
10
F
SDI
SCLK
DATA
AD56x0
V
OUT
VOB
VOA
VOC
V
DD
V1C
V1B
V1A
ADuM1300
Figure 52. AD5620/AD5640/AD5660 with a Galvanically Isolated Interface
POWER SUPPLY BYPASSING AND GROUNDING
When accuracy is important in a circuit, it is helpful to carefully
consider the power supply and ground return layout on the
board. The printed circuit board containing the AD5620/
AD5640/AD5660 should have separate analog and digital
sections, each having its own area of the board. If the AD5620/
AD5640/AD5660 are in a system where other devices require
an AGND-to-DGND connection, the connection should be
made at one point only. This ground point should be as close as
possible to the AD5620/AD5640/AD5660.
The power supply to the AD5620/AD5640/AD5660 should be
bypassed with 10 F and 0.1 F capacitors. The capacitors
should be as close as physically possible to the device, with the
0.1 F capacitor ideally right up against the device. The 10 F
capacitors are the tantalum bead type. It is important that the
0.1 F capacitor has a low effective series resistance (ESR) and
low effective series inductance (ESI), such as is typical of
common ceramic types of capacitors. This 0.1 F capacitor
provides a low impedance path to ground for high frequencies
caused by transient currents due to internal logic switching.
The power supply line itself should have as large a trace as
possible to provide a low impedance path and reduce glitch
effects on the supply line. Clocks and other components with
fast switching digital signals should be shielded from other
parts of the board by digital ground. Avoid crossover of digital
and analog signals if possible. When traces cross on opposite
sides of the board, ensure that they run at right angles to each
other to reduce feedthrough effects on the board. The best
board layout technique is the microstrip technique, where the
component side of the board is dedicated to the ground plane
only and the signal traces are placed on the solder side.
However, this is not always possible with a 2-layer board.
AD5620/AD5640/AD5660
Rev. A | Page 23 of 24
OUTLINE DIMENSIONS
1
3
5
6
2
8
4
7
2.90 BSC
1.60 BSC
1.95
BSC
0.65 BSC
0.38
0.22
0.15 MAX
1.30
1.15
0.90
SEATING
PLANE
1.45 MAX
0.22
0.08
0.60
0.45
0.30
8
4
0
2.80 BSC
PIN 1
INDICATOR
COMPLIANT TO JEDEC STANDARDS MO-178-BA
COMPLIANT TO JEDEC STANDARDS MO-187-AA
0.80
0.60
0.40
8
0
4
8
1
5
PIN 1
0.65 BSC
SEATING
PLANE
0.38
0.22
1.10 MAX
3.20
3.00
2.80
COPLANARITY
0.10
0.23
0.08
3.20
3.00
2.80
5.15
4.90
4.65
0.15
0.00
0.95
0.85
0.75
Figure 53. 8-Lead Small Outline Transistor Package [SOT-23]
(RJ-8)
Dimensions shown in millimeters
Figure 54. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
AD5620 ORDERING GUIDE
Model Temp.
Range
Package
Description
Package
Option Branding
Power-On
Reset to Code
Accuracy
Internal
Reference
AD5620ARJ-1500RL7
-15C to +105C
8-Lead SOT-23
RJ-8
D2K
Zero
6 LSB INL
1.25 V
AD5620ARJ-1REEL7
-15C to +105C
8-Lead SOT-23
RJ-8
D2K
Zero
6 LSB INL
1.25 V
AD5620ARJ-2500RL7
-15C to +105C
8-Lead SOT-23
RJ-8
D2L
Zero
6 LSB INL
2.5 V
AD5620ARJ-2REEL7
-15C to +105C
8-Lead SOT-23
RJ-8
D2L
Zero
6 LSB INL
2.5 V
AD5620BRJ-1500RL7
-15C to +105C
8-Lead SOT-23
RJ-8
D2H
Zero
1 LSB INL
1.25 V
AD5620BRJ-1REEL7
-15C to +105C
8-Lead SOT-23
RJ-8
D2H
Zero
1 LSB INL
1.25 V
AD5620BRJ-2500RL7
-15C to +105C
8-Lead SOT-23
RJ-8
D2J
Zero
1 LSB INL
2.5 V
AD5620BRJ-2REEL7
-15C to +105C
8-Lead SOT-23
RJ-8
D2J
Zero
1 LSB INL
2.5 V
AD5620CRM-1
-15C to +105C
8-Lead MSOP
RM-8
D2M
Zero
1 LSB INL
1.25 V
AD5620CRM-1REEL7
-15C to +105C
8-Lead MSOP
RM-8
D2M
Zero
1 LSB INL
1.25 V
AD5620CRM-2
-15C to +105C
8-Lead MSOP
RM-8
D2N
Zero
1 LSB INL
2.5 V
AD5620CRM-2REEL7
-15C to +105C
8-Lead MSOP
RM-8
D2N
Zero
1 LSB INL
2.5 V
AD5620CRM-3
-15C to +105C
8-Lead MSOP
RM-8
D2P
Midscale
1 LSB INL
2.5 V
AD5620CRM-3REEL7
-15C to +105C
8-Lead MSOP
RM-8
D2P
Midscale
1 LSB INL
2.5 V
EVAL-AD5620EB
Evaluation
Board
AD5620/AD5640/AD5660
Rev. A | Page 24 of 24
AD5640 ORDERING GUIDE
Model Temp.
Range
Package
Description
Package
Option Branding
Power-On
Reset to Code
Accuracy
Internal
Reference
AD5640ARJ-2500RL7
-15C to +105C
8-Lead SOT-23
RJ-8
D2T
Zero
8 LSB INL
2.5 V
AD5640ARJ-2REEL7
-15C to +105C
8-Lead SOT-23
RJ-8
D2T
Zero
8 LSB INL
2.5 V
AD5640BRJ-1500RL7
-15C to +105C
8-Lead SOT-23
RJ-8
D2Q
Zero
4 LSB INL
1.25 V
AD5640BRJ-1REEL7
-15C to +105C
8-Lead SOT-23
RJ-8
D2Q
Zero
4 LSB INL
1.25 V
AD5640BRJ-2500RL7
-15C to +105C
8-Lead SOT-23
RJ-8
D2R
Zero
4 LSB INL
2.5 V
AD5640BRJ-2REEL7
-15C to +105C
8-Lead SOT-23
RJ-8
D2R
Zero
4 LSB INL
2.5 V
AD5640CRM-1
-15C to +105C
8-Lead MSOP
RM-8
D2U
Zero
4 LSB INL
1.25 V
AD5640CRM-1REEL7
-15C to +105C
8-Lead MSOP
RM-8
D2U
Zero
4 LSB INL
1.25 V
AD5640CRM-2
-15C to +105C
8-Lead MSOP
RM-8
D2V
Zero
4 LSB INL
2.5 V
AD5640CRM-2REEL7
-15C to +105C
8-Lead MSOP
RM-8
D2V
Zero
4 LSB INL
2.5 V
EVAL-AD5640EB
Evaluation
Board
AD5660 ORDERING GUIDE
Model Temp.
Range
Package
Description
Package
Option Branding
Power-On
Reset to Code
Accuracy
Internal
Reference
AD5660ARJ-1500RL7
-15C to +105C
8-Lead SOT-23
RJ-8
D30
Zero
32 LSB INL
1.25 V
AD5660ARJ-1REEL7
-15C to +105C
8-Lead SOT-23
RJ-8
D30
Zero
32 LSB INL
1.25 V
AD5660ARJ-2500RL7
-15C to +105C
8-Lead SOT-23
RJ-8
D31
Zero
32 LSB INL
2.5 V
AD5660ARJ-2REEL7
-15C to +105C
8-Lead SOT-23
RJ-8
D31
Zero
32 LSB INL
2.5 V
AD5660ARJ-3500RL7
-15C to +105C
8-Lead SOT-23
RJ-8
D32
Midscale
32 LSB INL
2.5 V
AD5660ARJ-3REEL7
-15C to +105C
8-Lead SOT-23
RJ-8
D32
Midscale
32 LSB INL
2.5 V
AD5660BRJ-1500RL7
-15C to +105C
8-Lead SOT-23
RJ-8
D2X
Zero
16 LSB INL
1.25 V
AD5660BRJ-1REEL7
-15C to +105C
8-Lead SOT-23
RJ-8
D2X
Zero
16 LSB INL
1.25 V
AD5660BRJ-2500RL7
-15C to +105C
8-Lead SOT-23
RJ-8
D2Y
Zero
16 LSB INL
2.5 V
AD5660BRJ-2REEL7
-15C to +105C
8-Lead SOT-23
RJ-8
D2Y
Zero
16 LSB INL
2.5 V
AD5660BRJ-3500RL7
-15C to +105C
8-Lead SOT-23
RJ-8
D2Z
Midscale
16 LSB INL
2.5 V
AD5660BRJ-3REEL7
-15C to +105C
8-Lead SOT-23
RJ-8
D2Z
Midscale
16 LSB INL
2.5 V
AD5660CRM-1
-15C to +105C
8-Lead MSOP
RM-8
D33
Zero
16 LSB INL
1.25 V
AD5660CRM-1REEL7
-15C to +105C
8-Lead MSOP
RM-8
D33
Zero
16 LSB INL
1.25 V
AD5660CRM-2
-15C to +105C
8-Lead MSOP
RM-8
D34
Zero
16 LSB INL
2.5 V
AD5660CRM-2REEL7
-15C to +105C
8-Lead MSOP
RM-8
D34
Zero
16 LSB INL
2.5 V
AD5660CRM-3
-15C to +105C
8-Lead MSOP
RM-8
D35
Midscale
16 LSB INL
2.5 V
AD5660CRM-3REEL7
-15C to +105C
8-Lead MSOP
RM-8
D35
Midscale
16 LSB INL
2.5 V
EVAL-AD5660EB
Evaluation
Board
2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D0453909/05(A)
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