Document Outline
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Octal, 12-/14-/16-Bit DAC with 5 ppm/C
On-Chip Reference in 14-Lead TSSOP
AD5628/AD5648/AD5668
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
2005 Analog Devices, Inc. All rights reserved.
FEATURES
Low power, smallest-pin-compatible octal DACs
AD5668: 16 bits
AD5648: 14 bits
AD5628: 12 bits
14-lead/16-lead TSSOP
On-chip 1.25 V/2.5 V, 5 ppm/C reference
Power down to 400 nA @ 5 V, 200 nA @ 3 V
2.7 V to 5.5 V power supply
Guaranteed monotonic by design
Power-on reset to zero scale or midscale
3 power-down functions
Hardware LDAC and LDAC override function
CLR function to programmable code
Rail-to-rail operation
APPLICATIONS
Process control
Data acquisition systems
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
FUNCTIONAL BLOCK DIAGRAM
INTERFACE
LOGIC
INPUT
REGISTER
DIN
LDAC
GND
V
OUT
H
V
DD
LDAC
1
V
REFIN
/V
REFOUT
SYNC
SCLK
AD5628/AD5648/AD5668
CLR
1
1
RU-16 PACKAGE ONLY
1.25V/2.5V
REF
V
OUT
A
V
OUT
B
V
OUT
C
V
OUT
D
V
OUT
E
V
OUT
F
V
OUT
G
DAC
REGISTER
STRING
DAC A
BUFFER
INPUT
REGISTER
DAC
REGISTER
STRING
DAC B
BUFFER
INPUT
REGISTER
DAC
REGISTER
STRING
DAC C
BUFFER
INPUT
REGISTER
DAC
REGISTER
STRING
DAC D
BUFFER
INPUT
REGISTER
DAC
REGISTER
STRING
DAC E
BUFFER
INPUT
REGISTER
DAC
REGISTER
STRING
DAC F
BUFFER
INPUT
REGISTER
DAC
REGISTER
STRING
DAC G
BUFFER
INPUT
REGISTER
DAC
REGISTER
STRING
DAC H
BUFFER
POWER-DOWN
LOGIC
POWER-ON
RESET
0
5302-
00
1
Figure 1.
GENERAL DESCRIPTION
The AD5628/AD5648/AD5668 devices are low power, octal,
12-/14-/16-bit, buffered voltage-output DACs. All devices
operate from a single 2.7 V to 5.5 V supply and are guaranteed
monotonic by design.
The AD5628/AD5648/AD5668 have an on-chip reference with
an internal gain of 2. The AD5628/AD5648/AD5668-1 have a
1.25 V 5 ppm/C reference, giving a full-scale output range of
2.5 V; the AD5628/AD5648/AD5668-2, -3 have a 2.5 V 5 ppm/C
reference, giving a full-scale output range of 5 V. The on-board
reference is off at power-up, allowing the use of an external refer-
ence. The internal reference is enabled via a software write.
The part incorporates a power-on reset circuit that ensures that the
DAC output powers up to 0 V (AD5628/AD5648/AD5668-1, -2)
or midscale (AD5668-3) and remains powered up at this level
until a valid write takes place. The part contains a power-down
feature that reduces the current consumption of the device to
400 nA at 5 V and provides software-selectable output loads
while in power-down mode for any or all DAC channels.
The outputs of all DACs can be updated simultaneously
using the LDAC function, with the added functionality of user-
selectable DAC channels to simultaneously update. There is also
an asynchronous CLR that updates all DACs to a user-
programmable code--zero scale, midscale, or full scale.
The AD5628/AD5648/AD5668 utilize a versatile 3-wire serial
interface that operates at clock rates of up to 50 MHz and is
compatible with standard SPI, QSPITM, MICROWIRETM, and
DSP interface standards. The on-chip precision output amplifier
enables rail-to-rail output swing.
PRODUCT HIGHLIGHTS
1.
Octal, 12-/14-/16-bit DAC.
2.
On-chip 1.25 V/2.5 V, 5 ppm/C reference.
3.
Available in 14-lead/16-lead TSSOP.
4.
Power-on reset to 0 V or midscale.
5.
Power-down capability. When powered down, the DAC
typically consumes 200 nA at 3 V and 400 nA at 5 V.
AD5628/AD5648/AD5668
Rev. A | Page 2 of 28
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
AC Characteristics........................................................................ 7
Timing Characteristics ................................................................ 8
Absolute Maximum Ratings............................................................ 9
ESD Caution.................................................................................. 9
Pin Configurations and Function Descriptions ......................... 10
Typical Performance Characteristics ........................................... 11
Terminology .................................................................................... 19
Theory of Operation ...................................................................... 21
D/A Section................................................................................. 21
Resistor String............................................................................. 21
Internal Reference ...................................................................... 21
Output Amplifier........................................................................ 22
Serial Interface ............................................................................ 22
Input Shift Register .................................................................... 23
SYNC Interrupt .......................................................................... 23
Internal Reference Register ....................................................... 24
Power-On Reset.......................................................................... 24
Power-Down Modes .................................................................. 24
Clear Code Register ................................................................... 24
LDAC Function .......................................................................... 26
Power Supply Bypassing and Grounding................................ 26
Outline Dimensions ....................................................................... 27
AD5628 Ordering Guide........................................................... 28
AD5648 Ordering Guide........................................................... 28
AD5668 Ordering Guide........................................................... 28
REVISION HISTORY
11/05--Rev. 0 to Rev. A
Change to Specifications.................................................................. 3
10/05--Revision 0: Initial Version
AD5628/AD5648/AD5668
Rev. A | Page 3 of 28
SPECIFICATIONS
V
DD
= 4.5 V to 5.5 V, R
L
= 2 k to GND, C
L
= 200 pF to GND, V
REFIN
= V
DD
. All specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 1.
A
Grade
1
B
Grade
1
Parameter
Min Typ Max Min Typ Max Unit Conditions/Comments
STATIC PERFORMANCE
2
AD5628
Resolution
12
12
Bits
Relative
Accuracy
0.5
2
0.5
1
LSB
See
Figure 7
Differential
Nonlinearity 0.25
0.25
LSB
Guaranteed monotonic by design
(see Figure 10)
AD5648
Resolution
14
14
Bits
Relative
Accuracy
2
8
2
4
LSB
See
Figure 6
Differential
Nonlinearity 0.5
0.5
LSB
Guaranteed monotonic by design
(see Figure 9)
AD5668
Resolution
16
16
Bits
Relative
Accuracy
8 32
8 16 LSB
See
Figure 5
Differential
Nonlinearity 1
1
LSB
Guaranteed monotonic by design
(see Figure 8)
Zero-Code
Error
1
9 1
9 mV All 0s loaded to DAC register
(see Figure 24)
Zero-Code Error Drift
2
2
V/C
Full-Scale
Error
-0.2
-1
-0.2
-1
%
FSR
All 1s loaded to DAC register
(see Figure 25)
Gain
Error
1
1
%
FSR
Gain
Temperature
Coefficient
2.5
2.5
ppm
Of
FSR/C
Offset
Error
1
9
1
9
mV
DC Power Supply Rejection Ratio
80
80
dB
V
DD
10%
DC Crosstalk
(External Reference)
10
10
V Due to full-scale output change,
R
L
= 2 k to GND or V
DD
5
5
V/mA
Due to load current change
10
10
V
Due to powering down (per channel)
DC Crosstalk
(Internal Reference)
25
25
V Due to full-scale output change,
R
L
= 2 k to GND or V
DD
10
10
V/mA
Due to load current change
OUTPUT CHARACTERISTICS
3
Output Voltage Range
0
V
DD
0 V
DD
V
Capacitive Load Stability
2
2
nF
R
L
=
10
10
nF R
L
= 2 k
DC
Output
Impedance
0.5
0.5
Short-Circuit
Current
30
30
mA
V
DD
= 5 V
Power-Up Time
4
4
s
Coming out of power-down mode, V
DD
= 5 V
REFERENCE
INPUTS
Reference
Current
40
50
40
50
A V
REF
= V
DD
= 5.5 V (per DAC channel)
Reference Input Range
0
V
DD
0 V
DD
V
Reference Input Impedance
14.6
14.6
k
AD5628/AD5648/AD5668
Rev. A | Page 4 of 28
A
Grade
1
B
Grade
1
Parameter
Min Typ Max Min Typ Max Unit Conditions/Comments
REFERENCE
OUTPUT
Output
Voltage
AD5628/AD5648/AD5668-2, -3
2.495
2.505 2.495
2.505 V
At
ambient
Reference TC
3
5 10
5 10 ppm/C
Reference
Output
Impedance
7.5
7.5
k
LOGIC INPUTS
3
Input Current
3
3
A
All digital inputs
Input Low Voltage, V
INL
0.8
0.8
V V
DD
= 5 V
Input High Voltage, V
INH
2 2 V V
DD
= 5 V
Pin
Capacitance
3
3
pF
POWER
REQUIREMENTS
V
DD
4.5 5.5 4.5 5.5 V
All digital inputs at 0 or V
DD
,
DAC active, excludes load current
I
DD
(Normal Mode)
4
V
IH
= V
DD
and V
IL
= GND
V
DD
= 4.5 V to 5.5 V
1.3
1.8
1.3
1.8
mA
Internal reference off
V
DD
= 4.5 V to 5.5 V
2
2.5
2
2.5
mA
Internal reference on
I
DD
(All Power-Down Modes)
5
V
DD
= 4.5 V to 5.5 V
0.4
1
0.4
1
A
V
IH
= V
DD
and V
IL
= GND
1
Temperature range is -40C to +105C, typical at 25C.
2
Linearity calculated using a reduced code range of AD5628 (Code 32 to Code 4064), AD5648 (Code 128 to Code 16,256), and AD5668 (Code 512 to 65,024). Output
unloaded.
3
Guaranteed by design and characterization; not production tested.
4
Interface inactive. All DACs active. DAC outputs unloaded.
5
All eight DACs powered down.
AD5628/AD5648/AD5668
Rev. A | Page 5 of 28
V
DD
= 2.7 V to 3.6 V, R
L
= 2 k to GND, C
L
= 200 pF to GND, V
REFIN
= V
DD
. All specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 2.
A
Grade
1
B
Grade
1
Parameter
Min Typ Max Min Typ Max Unit Conditions/Comments
STATIC PERFORMANCE
2
AD5628
Resolution
12
12
Bits
Relative
Accuracy
0.5
2
0.5
1
LSB
See
Figure 7
Differential
Nonlinearity
0.25
0.25
LSB
Guaranteed monotonic by design
(see Figure 10)
AD5648
Resolution
14
14
Bits
Relative
Accuracy
2
8
2
4
LSB
See
Figure 6
Differential
Nonlinearity
0.5
0.5
LSB
Guaranteed monotonic by design
(see Figure 9)
AD5668
Resolution
16
16
Bits
Relative
Accuracy
8 32
8 16 LSB
See
Figure 5
Differential
Nonlinearity
1
1
LSB
Guaranteed monotonic by design
(see Figure 8)
Zero-Code Error
1
9
1
9
mV
All 0s loaded to DAC register (see Figure 24)
Zero-Code Error Drift
2
2
V/C
Full-Scale Error
-0.2
-1
-0.2
-1
% FSR
All 1s loaded to DAC register (see Figure 25)
Gain
Error
1
1
%
FSR
Gain
Temperature
Coefficient
2.5
2.5
ppm
Of
FSR/C
Offset
Error
1
9
1
9
mV
DC Power Supply Rejection
Ratio
80
80
dB V
DD
10%
DC Crosstalk
(External Reference)
10
10
V Due to full-scale output change,
R
L
= 2 k to GND or V
DD
5
5
V/mA
Due to load current change
10
10
V
Due to powering down (per channel)
DC Crosstalk
(Internal Reference)
25
25
V Due to full-scale output change,
R
L
= 2 k to GND or V
DD
10
10
V/mA
Due to load current change
OUTPUT CHARACTERISTICS
3
Output Voltage Range
0
V
DD
0 V
DD
V
Capacitive Load Stability
2
2
nF
R
L
=
10
10
nF R
L
= 2 k
DC
Output
Impedance 0.5
0.5
Short-Circuit
Current
30
30
mA
V
DD
= 3 V
Power-Up Time
4
4
s
Coming out of power-down mode, V
DD
= 3 V
REFERENCE
INPUTS
Reference
Current
40
50
40
50
A V
REF
= V
DD
= 3.6 V (per DAC channel)
Reference Input Range
0
V
DD
0 V
DD
Reference Input Impedance
14.6
14.6
k
REFERENCE OUTPUT
Output
Voltage
AD5628/AD5648/AD5668-1
1.247
1.253 1.247
1.253 V
At
ambient
Reference TC
3
5 15
5 15 ppm/C
Reference Output
Impedance
7.5
7.5
k
AD5628/AD5648/AD5668
Rev. A | Page 6 of 28
A
Grade
1
B
Grade
1
Parameter
Min Typ Max Min Typ Max Unit Conditions/Comments
LOGIC INPUTS
3
Input Current
3
3
A
All digital inputs
Input Low Voltage, V
INL
0.8
0.8
V V
DD
= 3 V
Input High Voltage, V
INH
2 2 V V
DD
= 3 V
Pin
Capacitance
3
3
pF
POWER
REQUIREMENTS
V
DD
2.7 3.6 2.7 3.6 V
All digital inputs at 0 or V
DD
,
DAC active, excludes load current
I
DD
(Normal Mode)
4
V
IH
= V
DD
and V
IL
= GND
V
DD
= 2.7 V to 3.6 V
1.2
1.5
1.2
1.5
mA
Internal reference off
V
DD
= 2.7 V to 3.6 V
1.7
2.25
1.7
2.25
mA
Internal reference on
I
DD
(All Power-Down Modes)
5
V
DD
= 2.7 V to 3.6 V
0.2
1
0.2
1
A
V
IH
= V
DD
and V
IL
= GND
1
Temperature range is -40C to +105C, typical at 25C.
2
Linearity calculated using a reduced code range of AD5628 (Code 32 to Code 4064), AD5648 (Code 128 to Code 16256), and AD5668 (Code 512 to 65024). Output
unloaded.
3
Guaranteed by design and characterization; not production tested.
4
Interface inactive. All DACs active. DAC outputs unloaded.
5
All eight DACs powered down.
AD5628/AD5648/AD5668
Rev. A | Page 7 of 28
AC CHARACTERISTICS
V
DD
= 2.7 V to 5.5 V, R
L
= 2 k to GND, C
L
= 200 pF to GND, V
REFIN
= V
DD
. All specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 3.
Parameter
1, 2
Min
Typ
Max
Unit
Conditions/Comments
3
Output Voltage Settling Time
6
10
s
to scale settling to 2 LSB
Slew Rate
1.5
V/s
Digital-to-Analog Glitch Impulse
4
nV-s
1 LSB change around major carry (see Figure 40)
Digital Feedthrough
0.1
nV-s
Reference Feedthrough
-90
dB
V
REF
= 2 V 0.1 V p-p, frequency = 10 Hz to 20 MHz
Digital Crosstalk
0.5
nV-s
Analog Crosstalk
2.5
nV-s
DAC-to-DAC Crosstalk
3
nV-s
Multiplying Bandwidth
340
kHz
V
REF
= 2 V 0.2 V p-p
Total Harmonic Distortion
-80
dB
V
REF
= 2 V 0.1 V p-p, frequency = 10 kHz
Output Noise Spectral Density
120
nV/Hz
DAC code = 0x8400, 1 kHz
100
nV/Hz
DAC code = 0x8400, 10 kHz
Output Noise
15
V p-p
0.1 Hz to 10 Hz
1
Guaranteed by design and characterization; not production tested.
2
See the Terminology section.
3
Temperature range is -40C to +105C, typical at 25C.
AD5628/AD5648/AD5668
Rev. A | Page 8 of 28
TIMING CHARACTERISTICS
All input signals are specified with tr = tf = 1 ns/V (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2. See Figure 2.
V
DD
= 2.7 V to 5.5 V. All specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 4.
Limit
at
T
MIN
, T
MAX
Parameter
V
DD
= 2.7 V to 5.5 V
Unit
Conditions/Comments
t
1
1
20
ns min
SCLK cycle time
t
2
8
ns min
SCLK high time
t
3
8
ns min
SCLK low time
t
4
13
ns min
SYNC to SCLK falling edge set-up time
t
5
4
ns min
Data set-up time
t
6
4
ns min
Data hold time
t
7
0
ns min
SCLK falling edge to SYNC rising edge
t
8
15
ns min
Minimum SYNC high time
t
9
13
ns min
SYNC rising edge to SCLK fall ignore
t
10
0
ns min
SCLK falling edge to SYNC fall ignore
t
11
10
ns min
LDAC pulse width low
t
12
15
ns min
SCLK falling edge to LDAC rising edge
t
13
5
ns min
CLR pulse width low
t
14
0
ns min
SCLK falling edge to LDAC falling edge
t
15
300
ns
typ
CLR pulse activation time
1
Maximum SCLK frequency is 50 MHz at V
DD
= 2.7 V to 5.5 V. Guaranteed by design and characterization; not production tested.
05
30
2-
00
2
t
4
t
3
SCLK
SYNC
DIN
t
1
t
2
t
5
t
6
t
7
t
8
DB31
t
9
t
10
t
11
t
12
LDAC
1
LDAC
2
t
14
1
ASYNCHRONOUS LDAC UPDATE MODE.
2
SYNCHRONOUS LDAC UPDATE MODE.
CLR
t
13
t
15
V
OUT
DB0
Figure 2. Serial Write Operation
AD5628/AD5648/AD5668
Rev. A | Page 9 of 28
ABSOLUTE MAXIMUM RATINGS
T
A
= 25C, unless otherwise noted.
Table 5.
Parameter Rating
V
DD
to GND
-0.3 V to +7 V
Digital Input Voltage to GND
-0.3 V to V
DD
+ 0.3 V
V
OUT
to GND
-0.3 V to V
DD
+ 0.3 V
V
REFIN
/V
REFOUT
to GND
-0.3 V to V
DD
+ 0.3 V
Operating Temperature Range
Industrial
-40C to +105C
Storage Temperature Range
-65C to +150C
Junction Temperature (T
J
MAX
)
+150C
TSSOP Package
Power Dissipation
(T
J
MAX
- T
A
)/
JA
JA
Thermal Impedance
150.4C/W
Reflow Soldering Peak Temperature
SnPb 240C
Pb Free
260C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
AD5628/AD5648/AD5668
Rev. A | Page 10 of 28
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
05
30
2-
0
03
1
2
3
4
5
6
7
AD5628/
AD5648/
AD5668
V
DD
V
OUT
A
V
OUT
C
V
REFIN
/V
REFOUT
V
OUT
G
V
OUT
E
14
13
12
11
10
9
8
DIN
GND
V
OUT
B
V
OUT
H
V
OUT
F
V
OUT
D
SCLK
TOP VIEW
(Not to Scale)
SYNC
Figure 3. 14-Lead TSSOP (RU-14)
05
30
2-
0
04
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SYNC
V
DD
V
OUT
A
V
OUT
G
V
OUT
E
V
OUT
C
LDAC
DIN
GND
V
OUT
B
V
OUT
H
V
REFIN
/V
REFOUT
CLR
V
OUT
F
V
OUT
D
SCLK
AD5628/
AD5648/
AD5668
TOP VIEW
(Not to Scale)
Figure 4. 16-Lead TSSOP (RU-16)
Table 6. Pin Function Descriptions
Pin No.
14-Lead
TSSOP
16-Lead
TSSOP Mnemonic
Description
1
LDAC
Pulsing this pin low allows any or all DAC registers to be updated if the input registers have
new data. This allows all DAC outputs to simultaneously update. Alternatively, this pin can be
tied permanently low.
1 2 SYNC
Active Low Control Input. This is the frame synchronization signal for the input data. When
SYNC goes low, it powers on the SCLK and DIN buffers and enables the input shift register.
Data is transferred in on the falling edges of the next 32 clocks. If SYNC is taken high before
the 32
nd
falling edge, the rising edge of SYNC acts as an interrupt and the write sequence is
ignored by the device.
2 3 V
DD
Power Supply Input. These parts can be operated from 2.7 V to 5.5 V, and the supply should
be decoupled with a 10 F capacitor in parallel with a 0.1 F capacitor to GND.
3 4
V
OUT
A
Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
11 13 V
OUT
B
Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
4 5 V
OUT
C
Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.
10 12 V
OUT
D
Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.
7 8 V
REFIN
/V
REFOUT
The AD5628/AD5648/AD5668 have a common pin for reference input and reference output.
When using the internal reference, this is the reference output pin. When using an external
reference, this is the reference input pin. The default for this pin is as a reference input.
9 CLR
Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all LDAC
pulses are ignored. When CLR is activated, the input register and the DAC register are
updated with the data contained in the CLR code register--zero, midscale, or full scale.
Default setting clears the output to 0 V.
5 6 V
OUT
E
Analog Output Voltage from DAC E. The output amplifier has rail-to-rail operation.
9 11 V
OUT
F
Analog Output Voltage from DAC F. The output amplifier has rail-to-rail operation.
6 7 V
OUT
G
Analog Output Voltage from DAC G. The output amplifier has rail-to-rail operation.
8 10 V
OUT
H
Analog Output Voltage from DAC H. The output amplifier has rail-to-rail operation.
12
14
GND
Ground Reference Point for All Circuitry on the Part.
13 15 DIN
Serial Data Input. This device has a 32-bit shift register. Data is clocked into the register on
the falling edge of the serial clock input.
14 16 SCLK
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial
clock input. Data can be transferred at rates of up to 50 MHz.
AD5628/AD5648/AD5668
Rev. A | Page 11 of 28
TYPICAL PERFORMANCE CHARACTERISTICS
CODE
I
N
L
ER
R
O
R
(
L
SB
)
10
4
6
8
0
2
6
10
8
2
4
0
5k 10k 15k 20k 25k 30k 35k 40k 45k 50k 55k 60k 65k
05
30
2-
00
5
V
DD
= V
REF
= 5V
T
A
= 25C
Figure 5. INL AD5668--External Reference
CODE
I
NL
E
RRO
R
(
L
S
B)
4
4
0
2500
5000
7500
10000
12500
15000
05
30
2-
0
06
3
2
1
0
1
2
3
V
DD
= V
REF
= 5V
T
A
= 25C
Figure 6. INL AD5648--External Reference
CODE
I
NL
E
RRO
R
(
L
S
B)
1.0
1.0
0
500
1000
1500
2000
2500
3000
3500
4000
05
30
2-
0
07
0.8
0.6
0.4
0
0.4
0.2
0.2
0.6
0.8
V
DD
= V
REF
= 5V
T
A
= 25C
Figure 7. INL AD5628--External Reference
CODE
DN
L
E
RRO
R
(
L
S
B)
1.0
0.6
0.4
0.2
0.8
0
0.4
0.2
0.6
1.0
0.8
0
10k
20k
30k
40k
50k
60k
05
30
2-
00
8
V
DD
= V
REF
= 5V
T
A
= 25C
Figure 8. DNL AD5668--External Reference
DN
L E
RRO
R (
L
S
B
)
0.5
0.3
0.2
0.1
0.4
0
0.2
0.1
0.3
0.5
0.4
05
30
2-
0
09
V
DD
= V
REF
= 5V
T
A
= 25C
CODE
0
2500
5000
7500
10000
12500
15000
Figure 9. DNL AD5648--External Reference
DN
L E
RRO
R (
L
S
B
)
0.20
0.10
0.05
0.15
0
0.05
0.10
0.20
0.15
05
30
2-
0
10
CODE
0
500
1000
1500
2000
2500
3000
3500
4000
V
DD
= V
REF
= 5V
T
A
= 25C
Figure 10. DNL AD5628--External Reference
AD5628/AD5648/AD5668
Rev. A | Page 12 of 28
CODE
I
NL
E
RRO
R (
L
S
B)
10
8
0
10
6
8
4
6
2
4
2
6
5000
6
0000
5
5000
5
0000
4
5000
4
0000
3
5000
3
0000
2
5000
2
0000
1
5000
1
0000
500
0
0
V
DD
= 5V
V
REFOUT
= 2.5V
T
A
= 25C
05
302
-
0
1
1
Figure 11. INL AD5668-2/AD5668-3
CODE
I
N
L
ER
R
O
R
(
L
SB
)
4
3
4
3
2
2
1
1
0
162
50
150
00
137
50
125
00
1
1250
100
00
8750
7500
6250
5000
3750
2500
1250
0
V
DD
= 5V
V
REFOUT
= 2.5V
T
A
= 25C
05
30
2-
0
12
Figure 12. INL AD5648-2
CODE
I
NL
E
RRO
R (
L
S
B)
1.0
0.8
0
1.0
0.8
0.6
0.6
0.4
0.2
0.4
0.2
0
1000
500
2000
1500
3500
3000
2500
4000
V
DD
= 5V
V
REFOUT
= 2.5V
T
A
= 25C
05
30
2-
01
3
Figure 13. INL AD5628-2
CODE
DN
L
E
RRO
R
(
L
S
B)
1.0
0.8
0
1.0
0.6
0.8
0.4
0.6
0.2
0.4
0.2
6
5000
6
0000
5
5000
5
0000
4
5000
4
0000
3
5000
3
0000
2
5000
2
0000
1
5000
1
0000
500
0
0
V
DD
= 5V
V
REFOUT
= 2.5V
T
A
= 25C
05
302
-
01
4
Figure 14. DNL AD5668-2/AD5668-3
CODE
D
N
L
E
RRO
R (
L
S
B)
0.5
0.4
0
0.5
0.3
0.4
0.2
0.3
0.1
0.2
0.1
162
50
150
00
137
50
125
00
1
1250
100
00
8750
7500
6250
5000
3750
2500
1250
0
V
DD
= 5V
V
REFOUT
= 2.5V
T
A
= 25C
05
30
2-
0
15
Figure 15. DNL AD5648-2
CODE
DN
L
E
RRO
R (
L
S
B)
0.20
0.15
0
0.20
0.15
0.10
0.10
0.05
0.05
0
1000
500
2000
1500
3500
3000
2500
4000
V
DD
= 5V
V
REFOUT
= 2.5V
T
A
= 25C
05
30
2-
01
6
Figure 16. DNL AD5628-2
AD5628/AD5648/AD5668
Rev. A | Page 13 of 28
CODE
I
NL
E
RRO
R
(
L
S
B)
10
8
4
6
2
0
4
2
6
8
10
650
00
600
00
550
00
500
00
450
00
400
00
350
00
300
00
250
00
200
00
150
00
100
00
5000
0
05
30
2-
0
17
V
DD
= 3V
V
REFOUT
= 1.25V
T
A
= 25
C
Figure 17. INL AD5668-1
CODE
I
NL
E
RRO
R
(
L
S
B)
4
4
162
50
150
00
137
50
125
00
1
1250
100
00
8750
7500
6250
5000
3750
2500
1250
0
05
30
2-
0
18
3
2
1
0
1
2
3
V
DD
= 3V
V
REFOUT
= 1.25V
T
A
= 25
C
Figure 18. INL AD5648-1
CODE
I
NL
E
RRO
R (
L
S
B)
1.0
1.0
0
500
1000
1500
2000
2500
3000
3500
4000
05
302
-
01
9
0
0.8
0.6
0.4
0.2
0.2
0.4
0.6
0.8
V
DD
= 3V
V
REFOUT
= 1.25V
T
A
= 25
C
Figure 19. INL AD5628-1
CODE
D
N
L
E
RRO
R
(
L
S
B)
1.0
0.8
0.4
0.6
0.2
0
0.4
0.2
0.6
0.8
1.0
650
00
600
00
550
00
500
00
450
00
400
00
350
00
300
00
250
00
200
00
150
00
100
00
5000
0
05
30
2-
0
20
V
DD
= 3V
V
REFOUT
= 1.25V
T
A
= 25
C
Figure 20. DNL AD5668-1
CODE
D
N
L
E
RRO
R
(
L
S
B)
0.5
0.5
162
50
150
00
137
50
125
00
1
1250
100
00
8750
7500
6250
5000
3750
2500
1250
0
05
30
2-
0
21
0
0.4
0.3
0.2
0.1
0.1
0.2
0.3
0.4
V
DD
= 3V
V
REFOUT
= 1.25V
T
A
= 25
C
Figure 21. DNL AD5648-1
TEMPERATURE (
C)
E
RRO
R (
%
F
S
R)
0
0.04
0.02
0.06
0.08
0.01
0.18
0.16
0.14
0.12
0.20
40
20
40
20
0
100
80
60
05
30
2
-
02
3
V
DD
= 5V
GAIN ERROR
FULL-SCALE ERROR
Figure 22. DNL AD5628-1
AD5628/AD5648/AD5668
Rev. A | Page 14 of 28
TEMPERATURE (
C)
E
R
RO
R
(
%
F
S
R)
0
0.04
0.02
0.06
0.08
0.10
0.18
0.16
0.14
0.12
0.20
40
20
40
20
0
100
80
60
05
30
2-
0
23
V
DD
= 5V
GAIN ERROR
FULL-SCALE ERROR
Figure 23. Gain Error and Full-Scale Error vs. Temperature
TEMPERATURE (
C)
E
R
RO
R (
m
V
)
1.5
1.0
0.5
0
2.0
1.5
1.0
0.5
2.5
40
20
40
20
0
80
60
100
05
30
2
-
02
4
OFFSET ERROR
ZERO-SCALE ERROR
Figure 24. Zero-Scale Error and Offset Error vs. Temperature
V
DD
(V)
E
RRO
R (
%
F
S
R)
1.0
1.5
1.0
0.5
0
0.5
2.0
2.7
3.2
3.7
4.7
4.2
5.2
05
30
2-
0
25
GAIN ERROR
FULL-SCALE ERROR
Figure 25. Gain Error and Full-Scale Error vs. Supply Voltage
V
DD
(V)
ER
R
O
R
(
m
V)
1.0
0.5
0
2.0
1.5
1.0
0.5
2.5
2.7
3.2
4.2
3.7
5.2
4.7
05
30
2-
0
26
ZERO-SCALE ERROR
OFFSET ERROR
T
A
= 25
C
Figure 26. Zero-Scale Error and Offset Error vs. Supply Voltage
I
DD
(mA)
FR
E
Q
U
E
N
C
Y
20
0
1.20 1.22 1.24 1.26 1.28 1.30 1.32 1.34 1.36 1.38 1.40 1.42 1.44
05
30
2-
02
7
2
4
6
8
10
12
14
16
18
V
DD
= 3.6V
V
DD
= 5.5V
Figure 27. I
DD
Histogram with External Reference
I
DD
(mA)
FR
E
Q
U
E
N
C
Y
14
0
2.02
05
30
2-
02
8
2
4
6
8
10
12
V
DD
= 3.6V
V
DD
= 5.5V
2.04 2.06 2.08 2.10 2.12 2.14 2.16 2.18 2.20 2.22 2.24 2.26 2.28
V
REFOUT
= 1.25V
V
REFOUT
= 2.5V
Figure 28. I
DD
Histogram with Internal Reference
AD5628/AD5648/AD5668
Rev. A | Page 15 of 28
CURRENT (mA)
E
RRO
R V
O
L
T
AG
E
(
V
)
0.50
0.40
0.50
0.40
0.30
0.20
0.10
0
0.10
0.20
0.30
10
8
6
4
2
0
2
4
8
6
10
0
530
2-
0
29
V
DD
= 3V
V
REFOUT
= 1.25V
V
DD
= 5V
V
REFOUT
= 2.5V
DAC LOADED WITH
ZERO-SCALE
SINKING CURRENT
DAC LOADED WITH
FULL-SCALE
SOURCING CURRENT
Figure 29. Headroom at Rails vs. Source and Sink
CURRENT (mA)
V
OU
T
(V
)
6.00
5.00
4.00
3.00
2.00
1.00
1.00
0
30
20
10
0
10
20
30
0
530
2-
0
30
V
DD
= 5V
V
REFOUT
= 2.5V
T
A
= 25
C
ZERO SCALE
FULL SCALE
MIDSCALE
1/4 SCALE
3/4 SCALE
Figure 30. AD5668-2/AD5668-3 Source and Sink Capability
CURRENT (mA)
V
OU
T
(V
)
4.00
1.00
0
1.00
2.00
3.00
30
20
10
0
10
20
30
0
530
2-
0
31
V
DD
= 3V
V
REFOUT
= 1.25V
T
A
= 25
C
ZERO SCALE
FULL SCALE
MIDSCALE
1/4 SCALE
3/4 SCALE
Figure 31. AD5668-1 Source and Sink Capability
CODE
I
DD
(m
A
)
2.0
0
05
30
2-
0
32
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
512
10512
20512
30512
40512
50512
60512
T
A
= 25C
V
DD
= V
REF
= 3V
V
DD
= V
REF
= 5V
Figure 32. Supply Current vs. Code
TEMPERATURE (C)
I
DD
(m
A
)
1.6
0
0.2
1.0
1.2
1.4
0.4
0.6
0.8
40
20
0
20
40
60
80
100
05
30
2-
0
33
V
DD
= V
REFIN
= 3.6V
V
DD
= V
REFIN
= 5.5V
Figure 33. Supply Current vs. Temperature
V
DD
(V)
I
DD
(
m
A)
1.6
0
0.2
1.0
1.2
1.4
0.4
0.6
0.8
2.7
0
530
2-
0
34
3.2
4.2
3.7
5.2
4.7
T
A
= 25C
Figure 34. Supply Current vs. Supply Voltage
AD5628/AD5648/AD5668
Rev. A | Page 16 of 28
V
LOGIC
(V)
I
DD
(m
A
)
8
0
1
5
6
7
2
3
4
0
1
2
3
4
5
6
0
530
2-
0
35
V
DD
= 5V
V
DD
= 3V
T
A
= 25C
Figure 35. Supply Current vs. Logic Input Voltage
05
30
2-
03
6
TIME BASE = 4
s/DIV
V
DD
= V
REF
= 5V
T
A
= 25
C
FULL-SCALE CODE CHANGE
0x0000 TO 0xFFFF
OUTPUT LOADED WITH 2k
AND 200pF TO GND
V
OUT
= 909mV/DIV
1
Figure 36. Full-Scale Settling Time, 5 V
05
30
2
-
03
7
CH1 2.0V
CH2 500mV
M100
s 125MS/s
A CH1
1.28V
8.0ns/pt
V
DD
= V
REF
= 5V
T
A
= 25
C
V
OUT
V
DD
1
2
MAX(C2)*
420.0mV
Figure 37. Power-On Reset to 0 V
05
30
2
-
03
8
CH1 2.0V
CH2 1.0V
M100
s 125MS/s
A CH1
1.28V
8.0ns/pt
V
DD
= V
REF
= 5V
T
A
= 25
C
V
OUT
V
DD
1
2
Figure 38. Power-On Reset to Midscale
0
530
2-
0
39
V
DD
= 5V
SYNC
SLCK
V
OUT
1
3
CH1 5.0V
CH3 5.0V
CH2
500mV
M400ns
A CH1 1.4V
2
Figure 39. Exiting Power-Down to Midscale
SAMPLE
V
OU
T
(V
)
2.505
2.485
0
512
05
30
2-
0
40
64
128
192
256
320
384
448
V
DD
= 5V
V
REFOUT
= 2.5V
T
A
= 25C
4ns/SAMPLE NUMBER
GLITCH IMPULSE = 3.55nV-s
1 LSB CHANGE AROUND
MIDSCALE (0x8000 TO 0x7FFF)
2.486
2.487
2.488
2.489
2.490
2.491
2.492
2.493
2.494
2.495
2.496
2.497
2.498
2.499
2.500
2.501
2.502
2.503
2.504
Figure 40. Digital-to-Analog Glitch Impulse (Negative)
AD5628/AD5648/AD5668
Rev. A | Page 17 of 28
SAMPLE
V
OU
T
(V
)
2.5000
2.4950
0
512
05
30
2-
0
42
2.4955
2.4960
2.4965
2.4970
2.4975
2.4980
2.4985
2.4990
2.4995
64
128
192
256
320
384
448
V
DD
= 5V
V
REFOUT
= 2.5V
T
A
= 25C
4ns/SAMPLE NUMBER
Figure 41. Analog Crosstalk
SAMPLE
V
OU
T
(V
)
2.4900
2.4855
0
512
05
30
2-
0
43
64
128
192
256
320
384
448
2.4860
2.4865
2.4870
2.4875
2.4880
2.4885
2.4890
2.4895
V
DD
= 5V
V
REFOUT
= 2.5V
T
A
= 25C
4ns/SAMPLE NUMBER
Figure 42. DAC-to-DAC Crosstalk
05
30
2-
0
44
1
Y AXIS = 2
V/DIV
X AXIS = 4s/DIV
V
DD
= V
REF
= 5V
T
A
= 25
C
DAC LOADED WITH MIDSCALE
Figure 43. 0.1 Hz to 10 Hz Output Noise Plot, External Reference
5s/DIV
10
V/
D
I
V
1
05
30
2-
0
45
V
DD
= 5V
V
REFOUT
= 2.5V
T
A
= 25
C
DAC LOADED WITH MIDSCALE
Figure 44. 0.1 Hz to 10 Hz Output Noise Plot, Internal Reference
4s/DIV
5
V/
D
I
V
1
05
30
2-
04
6
V
DD
= 3V
V
REFOUT
= 1.25V
T
A
= 25
C
DAC LOADED WITH MIDSCALE
Figure 45. 0.1 Hz to 10 Hz Output Noise Plot, Internal Reference
FREQUENCY (Hz)
O
UT
P
UT
NO
I
S
E
(
n
V
/
Hz
)
800
0
100
200
300
400
500
600
700
100
10000
1000
100000
1000000
0
530
2-
0
47
V
DD
= 3V
V
REFOUT
= 1.25V
V
DD
= 5V
V
REFOUT
= 2.5V
T
A
= 25C
MIDSCALE LOADED
Figure 46. Noise Spectral Density, Internal Reference
AD5628/AD5648/AD5668
Rev. A | Page 18 of 28
FREQUENCY (Hz)
(d
B
)
20
50
80
30
40
60
70
90
100
2k
4k
6k
8k
10k
0
530
2-
0
48
V
DD
= 5V
T
A
= 25
C
DAC LOADED WITH FULL SCALE
V
REF
= 2V
0.3Vp-p
Figure 47. Total Harmonic Distortion
CAPACITANCE (nF)
TI
M
E
(
s)
16
14
12
10
8
6
4
0
1
2
3
4
5
6
7
9
8
10
0
530
2-
0
49
V
REF
= V
DD
T
A
= 25
C
V
DD =
5V
V
DD =
3V
Figure 48. Settling Time vs. Capacitive Load
05
30
2-
05
0
V
OUT
F
V
OUT
B
3
CH3 5.0V
CH4 1.0V
CH2
1.0V
M200ns A CH3
1.10V
2
4
4
CLR
Figure 49. Hardware CLR
FREQUENCY (Hz)
(d
B
)
5
40
10k
100k
1M
10M
05
30
2-
0
51
35
30
25
20
15
10
5
0
V
DD
= 5V
T
A
= 25C
Figure 50. Multiplying Bandwidth
AD5628/AD5648/AD5668
Rev. A | Page 19 of 28
TERMINOLOGY
Relative Accuracy
For the DAC, relative accuracy, or integral nonlinearity (INL), is
a measure of the maximum deviation in LSBs from a straight line
passing through the endpoints of the DAC transfer function.
Figure 5 to Figure 7, Figure 11 to Figure 13, and Figure 17 to
Figure 19 show plots of typical INL vs. code.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between the
measured change and the ideal 1 LSB change between any two
adjacent codes. A specified differential nonlinearity of 1 LSB
maximum ensures monotonicity. This DAC is guaranteed mono-
tonic by design. Figure 8 to Figure 10, Figure 14 to Figure 16,
and Figure 20 to Figure 22 show plots of typical DNL vs. code.
Offset Error
Offset error is a measure of the difference between the actual
V
OUT
and the ideal V
OUT
, expressed in millivolts in the linear
region of the transfer function. Offset error is measured on the
AD5668 with Code 512 loaded into the DAC register. It can be
negative or positive and is expressed in millivolts.
Zero-Code Error
Zero-code error is a measure of the output error when zero
code (0x0000) is loaded into the DAC register. Ideally, the
output should be 0 V. The zero-code error is always positive in
the AD5628/AD5648/AD5668, because the output of the DAC
cannot go below 0 V. It is due to a combination of the offset
errors in the DAC and output amplifier. Zero-code error is
expressed in millivolts. Figure 26 shows a plot of typical zero-
code error vs. temperature.
Gain Error
Gain error is a measure of the span error of the DAC. It is the
deviation in slope of the DAC transfer characteristic from the
ideal, expressed as a percentage of the full-scale range.
Zero-Code Error Drift
Zero-code error drift is a measure of the change in zero-code
error with a change in temperature. It is expressed in V/C.
Gain Error Drift
Gain error drift is a measure of the change in gain error with
changes in temperature. It is expressed in (ppm of full-scale
range)/C.
Full-Scale Error
Full-scale error is a measure of the output error when full-scale
code (0xFFFF) is loaded into the DAC register. Ideally, the
output should be V
DD
1 LSB. Full-scale error is expressed as a
percentage of the full-scale range. Figure 23 shows a plot of
typical full-scale error vs. temperature.
Digital-to-Analog Glitch Impulse
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nV-s and
is measured when the digital input code is changed by 1 LSB at
the major carry transition (0x7FFF to 0x8000). See Figure 40.
DC Power Supply Rejection Ratio (PSRR)
PSRR indicates how the output of the DAC is affected by changes
in the supply voltage. PSRR is the ratio of the change in V
OUT
to
a change in V
DD
for full-scale output of the DAC. It is measured
in decibels. V
REF
is held at 2 V, and V
DD
is varied 10%.
DC Crosstalk
DC crosstalk is the dc change in the output level of one DAC in
response to a change in the output of another DAC. It is measured
with a full-scale output change on one DAC (or soft power-down
and power-up) while monitoring another DAC kept at midscale.
It is expressed in microvolts.
DC crosstalk due to load current change is a measure of the
impact that a change in load current on one DAC has to another
DAC kept at midscale. It is expressed in microvolts per milliamp.
Reference Feedthrough
Reference feedthrough is the ratio of the amplitude of the signal
at the DAC output to the reference input when the DAC output
is not being updated (that is, LDAC is high). It is expressed in
decibels.
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into
the analog output of a DAC from the digital input pins of the
device, but is measured when the DAC is not being written to
(SYNC held high). It is specified in nV-s and measured with a
full-scale change on the digital input pins, that is, from all 0s to
all 1s or vice versa.
Digital Crosstalk
Digital crosstalk is the glitch impulse transferred to the output
of one DAC at midscale in response to a full-scale code change
(all 0s to all 1s or vice versa) in the input register of another DAC.
It is measured in standalone mode and is expressed in nV-s.
Analog Crosstalk
Analog crosstalk is the glitch impulse transferred to the output
of one DAC due to a change in the output of another DAC. It is
measured by loading one of the input registers with a full-scale
code change (all 0s to all 1s or vice versa) while keeping LDAC
high, and then pulsing LDAC low and monitoring the output of
the DAC whose digital code has not changed. The area of the
glitch is expressed in nV-s.
AD5628/AD5648/AD5668
Rev. A | Page 20 of 28
DAC-to-DAC Crosstalk
DAC-to-DAC crosstalk is the glitch impulse transferred to the
output of one DAC due to a digital code change and subsequent
output change of another DAC. This includes both digital and
analog crosstalk. It is measured by loading one of the DACs
with a full-scale code change (all 0s to all 1s or vice versa) with
LDAC low and monitoring the output of another DAC. The
energy of the glitch is expressed in nV-s.
Multiplying Bandwidth
The amplifiers within the DAC have a finite bandwidth. The
multiplying bandwidth is a measure of this. A sine wave on the
reference (with full-scale code loaded to the DAC) appears on
the output. The multiplying bandwidth is the frequency at
which the output amplitude falls to 3 dB below the input.
Total Harmonic Distortion (THD)
Total harmonic distortion is the difference between an ideal
sine wave and its attenuated version using the DAC. The sine
wave is used as the reference for the DAC, and the THD is a
measure of the harmonics present on the DAC output. It is
measured in decibels.
AD5628/AD5648/AD5668
Rev. A | Page 21 of 28
THEORY OF OPERATION
D/A SECTION
The AD5628/AD5648/AD5668 DACs are fabricated on a
CMOS process. The architecture consists of a string of DACs
followed by an output buffer amplifier. Each part includes an
internal 1.25 V/2.5 V, 5 ppm/C reference with an internal gain
of 2. Figure 51 shows a block diagram of the DAC architecture.
053
02
-
052
DAC REGISTER
REF (+)
V
DD
V
OUT
GND
REF ()
RESISTOR
STRING
OUTPUT
AMPLIFIER
(GAIN = +2)
Figure 51. DAC Architecture
Because the input coding to the DAC is straight binary, the ideal
output voltage when using an external reference is given by
=
N
REFIN
OUT
D
V
V
2
The ideal output voltage when using the internal reference is
given by
=
N
REFOUT
OUT
D
V
V
2
2
where:
D
= decimal equivalent of the binary code that is loaded to the
DAC register.
0 to 4095 for AD5628 (12 bits).
0 to 16,383 for AD5648 (14 bits).
0 to 65,535 for AD5668 (16 bits).
N
= the DAC resolution.
RESISTOR STRING
The resistor string section is shown in Figure 52. It is simply a
string of resistors, each of value R. The code loaded into the
DAC register determines at which node on the string the
voltage is tapped off to be fed into the output amplifier. The
voltage is tapped off by closing one of the switches connecting
the string to the amplifier. Because it is a string of resistors, it is
guaranteed monotonic.
05
30
2-
0
53
TO OUTPUT
AMPLIFIER
R
R
R
R
R
Figure 52. Resistor String
INTERNAL REFERENCE
The AD5628/AD5648/AD5668 have an on-chip reference with
an internal gain of 2. The AD5628/AD5648/AD5668-1 have a
1.25 V, 5 ppm/C reference, giving a full-scale output of 2.5 V;
the AD5628/AD5648/AD5668-2, -3 have a 2.5 V, 5 ppm/C
reference, giving a full-scale output of 5 V. The on-board
reference is off at power-up, allowing the use of an external
reference. The internal reference is enabled via a write to the
control register (see Table 7).
The internal reference associated with each part is available at
the V
REFOUT
pin. A buffer is required if the reference output is
used to drive external loads. When using the internal reference,
it is recommended that a 100 nF capacitor be placed between
the reference output and GND for reference stability.
Individual channel power-down is not supported while using
the internal reference.
AD5628/AD5648/AD5668
Rev. A | Page 22 of 28
OUTPUT AMPLIFIER
The output buffer amplifier can generate rail-to-rail voltages on
its output, which gives an output range of 0 V to V
DD
. The
amplifier is capable of driving a load of 2 k in parallel with
1000 pF to GND. The source and sink capabilities of the output
amplifier can be seen in Figure 30 and Figure 31. The slew rate
is 1.5 V/s with a to scale settling time of 10 s.
SERIAL INTERFACE
The AD5628/AD5648/AD5668 have a 3-wire serial interface
(SYNC, SCLK, and DIN) that is compatible with SPI, QSPI, and
MICROWIRE interface standards as well as most DSPs. See
Figure 2 for a timing diagram of a typical write sequence.
The write sequence begins by bringing the SYNC line low. Data
from the DIN line is clocked into the 32-bit shift register on the
falling edge of SCLK. The serial clock frequency can be as high
as 50 MHz, making the AD5628/AD5648/AD5668 compatible
with high speed DSPs. On the 32
nd
falling clock edge, the last
data bit is clocked in and the programmed function is executed,
that is, a change in DAC register contents and/or a change in
the mode of operation. At this stage, the SYNC line can be kept
low or be brought high. In either case, it must be brought high
for a minimum of 15 ns before the next write sequence so that a
falling edge of SYNC can initiate the next write sequence.
Because the SYNC buffer draws more current when V
IN
= 2 V
than it does when V
IN
= 0.8 V, SYNC should be idled low
between write sequences for even lower power operation of the
part. As is mentioned previously, however, SYNC must be
brought high again just before the next write sequence.
Table 7. Command Definitions
Command
C3 C2 C1 C0 Description
0 0 0 0 Write
to
Input
Register
n
0
0
0
1
Update DAC Register n
0 0 1 0 Write to Input Register n, update all
(software LDAC)
0
0
1
1
Write to and update DAC Channel n
0
1
0
0
Power down/power up DAC
0 1 0 1 Load
clear
code
register
0 1 1 0 Load LDAC register
0 1 1 1 Reset
(power-on
reset)
1
0
0
0
Set up internal REF register
1 0 0 1 Reserved
Reserved
1 1 1 1 Reserved
Table 8. Address Commands
Address (n)
A3 A2 A1 A0
Selected DAC
Channel
0 0 0 0 DAC
A
0 0 0 1 DAC
B
0 0 1 0 DAC
C
0 0 1 1 DAC
D
0 1 0 0 DAC
E
0 1 0 1 DAC
F
0 1 1 0 DAC
G
0 1 1 1 DAC
H
1 1 1 1 All
DACs
AD5628/AD5648/AD5668
Rev. A | Page 23 of 28
INPUT SHIFT REGISTER
The input shift register is 32 bits wide. The first four bits are
don't cares. The next four bits are the command bits, C3 to C0
(see Table 7), followed by the 4-bit DAC address, A3 to A0 (see
Table 8) and finally the 16-/14-/12-bit data-word. The data-
word comprises the 16-/14-/12-bit input code followed by four,
six, or eight don't care bits for the AD5668, AD5648, and
AD5628, respectively (see Figure 53 through Figure 55). These
data bits are transferred to the DAC register on the 32
nd
falling
edge of SCLK.
SYNC INTERRUPT
In a normal write sequence, the SYNC line is kept low for
32 falling edges of SCLK, and the DAC is updated on the 32
nd
falling edge and rising edge of SYNC. However, if SYNC is brought
high before the 32
nd
falling edge, this acts as an interrupt to the
write sequence. The shift register is reset, and the write sequence
is seen as invalid. Neither an update of the DAC register contents
nor a change in the operating mode occurs (see Figure 56).
05
30
2-
0
54
ADDRESS BITS
COMMAND BITS
C3
C2
C1
C0
A3
A2
A1
A0
D15 D14 D13 D12 D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
X
X
X
X
DB31 (MSB)
DB0 (LSB)
DATA BITS
Figure 53. AD5668 Input Register Contents
05
30
2-
0
55
ADDRESS BITS
COMMAND BITS
C3
C2
C1
C0
A3
A2
A1
A0
D13 D12 D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
X
X
X
X
X
X
DB31 (MSB)
DB0 (LSB)
DATA BITS
Figure 54. AD5648 Input Register Contents
0
530
2-
0
56
ADDRESS BITS
COMMAND BITS
C3
C2
C1
C0
A3
A2
A1
A0
D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
X
X
X
X
X
X
X
X
DB31 (MSB)
DB0 (LSB)
DATA BITS
Figure 55. AD5628 Input Register Contents
05
30
2-
05
7
SCLK
DIN
DB31
DB0
INVALID WRITE SEQUENCE:
SYNC HIGH BEFORE 32ND FALLING EDGE
VALID WRITE SEQUENCE, OUTPUT UPDATES
ON THE 32ND FALLING EDGE
DB31
DB0
SYNC
Figure 56. SYNC Interrupt Facility
AD5628/AD5648/AD5668
Rev. A | Page 24 of 28
INTERNAL REFERENCE REGISTER
The on-board reference is off at power-up by default. This allows
the use of an external reference if the application requires it. The
on-board reference can be turned on or off by a user-program-
mable internal REF register by setting Bit DB0 high or low (see
Table 9). Command 1000 is reserved for setting the internal
REF register (see Table 7). Table 11 shows how the state of the
bits in the input shift register corresponds to the mode of
operation of the device.
POWER-ON RESET
The AD5628/AD5648/AD5668 family contains a power-on
reset circuit that controls the output voltage during power-up.
The AD5628/AD5648/AD5668-1, -2 DAC output powers up to
0 V, and the AD5668-3 DAC output powers up to midscale. The
output remains powered up at this level until a valid write
sequence is made to the DAC. This is useful in applications
where it is important to know the state of the output of the DAC
while it is in the process of powering up. There is also a software
executable reset function that resets the DAC to the power-on
reset code. Command 0111 is reserved for this reset function
(see Table 7). Any events on LDAC or CLR during power-on
reset are ignored.
POWER-DOWN MODES
The AD5628/AD5648/AD5668 contain four separate modes
of operation. Command 0100 is reserved for the power-down
function (see Table 7). These modes are software-programmable
by setting two bits, Bit DB9 and Bit DB8, in the control register.
Table 11 shows how the state of the bits corresponds to the
mode of operation of the device. Any or all DACs (DAC H to
DAC A) can be powered down to the selected mode by setting
the corresponding eight bits (DB7 to DB0) to 1. See Table 12 for
the contents of the input shift register during power-down/power-
up operation. When using the internal reference, only all channel
power-down to the selected modes is supported.
When both bits are set to 0, the part works normally with its
normal power consumption of 1.3 mA at 5 V. However, for the
three power-down modes, the supply current falls to 0.4 A at
5 V (0.2 A at 3 V). Not only does the supply current fall, but
the output stage is also internally switched from the output of
the amplifier to a resistor network of known values. This has the
advantage that the output impedance of the part is known while
the part is in power-down mode. There are three different
options. The output is connected internally to GND through
either a 1 k or a 100 k resistor, or it is left open-circuited
(three-state). The output stage is illustrated in Figure 57.
The bias generator of the selected DAC(s), output amplifier,
resistor string, and other associated linear circuitry are shut
down when the power-down mode is activated. The internal
reference is powered down only when all channels are powered
down. However, the contents of the DAC register are unaffected
when in power-down. The time to exit power-down is typically
4 s for V
DD
= 5 V and for V
DD
= 3 V. See Figure 39 for a plot.
Any combination of DACs can be powered up by setting PD1
and PD0 to 0 (normal operation). The output powers up to the
value in the input register (LDAC low) or to the value in the
DAC register before powering down (LDAC high).
CLEAR CODE REGISTER
The AD5628/AD5648/AD5668 have a hardware CLR pin that
is an asynchronous clear input. The CLR input is falling edge
sensitive. Bringing the CLR line low clears the contents of the
input register and the DAC registers to the data contained in
the user-configurable CLR register and sets the analog outputs
accordingly. This function can be used in system calibration to load
zero scale, midscale, or full scale to all channels together. These
clear code values are user-programmable by setting two bits,
Bit DB1 and Bit DB0, in the CLR control register (see Table 13).
The default setting clears the outputs to 0 V. Command 0101 is
reserved for loading the clear code register (see Table 7).
The part exits clear code mode on the 32
nd
falling edge of the next
write to the part. If CLR is activated during a write sequence, the
write is aborted.
The CLR pulse activation time--the falling edge of CLR to
when the output starts to change--is typically 280 ns. However, if
outside the DAC linear region, it typically takes 520 ns after
executing CLR for the output to start changing (see Figure 49).
See Table 14 for contents of the input shift register during the
loading clear code register operation.
AD5628/AD5648/AD5668
Rev. A | Page 25 of 28
Table 9. Internal Reference Register
Internal REF Register (DB0)
Action
0
Reference off (default)
1 Reference
on
Table 10. 32-Bit Input Shift Register Contents for Reference Set-Up Command
MSB
LSB
DB31 to DB28
DB27
DB26
DB25
DB24
DB23
DB22
DB21
DB20
DB19 to DB1
DB0
X
1 0 0 0 X X X X X
1/0
Don't cares
Command bits (C3 to C0)
Address bits (A3 to A0)--don't cares
Don't cares
Internal REF
register
Table 11. Power-Down Modes of Operation
DB9
DB8
Operating Mode
0
0
Normal operation
Power-down modes
0
1
1 k to GND
1
0
100 k to GND
1
1
Three-state
Table 12. 32-Bit Input Shift Register Contents for Power-Down/Power-Up Function
MSB
LSB
DB31
to
DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20
DB19
to
DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
X 0 1 0 0 X X X X X PD1
PD0
DAC
H
DAC
G
DAC
F
DAC
E
DAC
D
DAC
C
DAC
B
DAC
A
Don't
cares
Command bits (C3 to C0)
Address bits (A3 to A0)--
don't cares
Don't
cares
Power-
down mode
Power-down/power-up channel selection--set bit to 1 to select
RESISTOR
NETWORK
V
OUT
RESISTOR
STRING DAC
053
02
-
05
8
POWER-DOWN
CIRCUITRY
AMPLIFIER
Figure 57. Output Stage During Power-Down
Table 13. Clear Code Register
Clear Code Register
DB1 DB0
CR1 CR0 Clears
to
Code
0 0 0x0000
0 1 0x8000
1 0 0xFFFF
1 1 No
operation
Table 14. 32-Bit Input Shift Register Contents for Clear Code Function
MSB
LSB
DB31 to DB28
DB27
DB26
DB25
DB24
DB23
DB22
DB21
DB20
DB19 to DB2
DB1
DB0
X
0 1 0 1 X X X X X
CR1 CR0
Don't cares
Command bits (C3 to C0)
Address bits (A3 to A0)--don't cares
Don't cares
Clear code register
AD5628/AD5648/AD5668
Rev. A | Page 26 of 28
LDAC FUNCTION
The outputs of all DACs can be updated simultaneously using
the hardware LDAC pin.
Synchronous LDAC: After new data is read, the DAC registers
are updated on the falling edge of the 32
nd
SCLK pulse. LDAC
can be permanently low or pulsed as in Figure 2.
Asynchronous LDAC: The outputs are not updated at the same
time that the input registers are written to. When LDAC goes
low, the DAC registers are updated with the contents of the
input register.
Alternatively, the outputs of all DACs can be updated simulta-
neously using the software LDAC function by writing to Input
Register n and updating all DAC registers. Command 0011 is
reserved for this software LDAC function.
An LDAC register gives the user extra flexibility and control
over the hardware LDAC pin. This register allows the user to
select which combination of channels to simultaneously update
when the hardware LDAC pin is executed. Setting the LDAC bit
register to 0 for a DAC channel means that this channel's update
is controlled by the LDAC pin. If this bit is set to 1, this channel
updates synchronously; that is, the DAC register is updated
after new data is read, regardless of the state of the LDAC pin. It
effectively sees the LDAC pin as being tied low. (See Table 15
for the LDAC register mode of operation.) This flexibility is
useful in applications where the user wants to simultaneously
update select channels while the rest of the channels are
synchronously updating.
Writing to the DAC using command 0110 loads the 8-bit LDAC
register (DB7 to DB0). The default for each channel is 0, that is,
the LDAC pin works normally. Setting the bits to 1 means the
DAC channel is updated regardless of the state of the LDAC
pin. See Table 16 for the contents of the input shift register
during the load LDAC register mode of operation.
POWER SUPPLY BYPASSING AND GROUNDING
When accuracy is important in a circuit, it is helpful to carefully
consider the power supply and ground return layout on the board.
The printed circuit board containing the AD5628/AD5648/
AD5668 should have separate analog and digital sections. If the
AD5628/AD5648/AD5668 are in a system where other devices
require an AGND-to-DGND connection, the connection should
be made at one point only. This ground point should be as close
as possible to the AD5628/AD5648/AD5668.
The power supply to the AD5628/AD5648/AD5668 should be
bypassed with 10 F and 0.1 F capacitors. The capacitors
should physically be as close as possible to the device, with the
0.1 F capacitor ideally right up against the device. The 10 F
capacitors are the tantalum bead type. It is important that the
0.1 F capacitor has low effective series resistance (ESR) and
low effective series inductance (ESI), such as is typical of
common ceramic types of capacitors. This 0.1 F capacitor
provides a low impedance path to ground for high frequencies
caused by transient currents due to internal logic switching.
The power supply line should have as large a trace as possible to
provide a low impedance path and reduce glitch effects on the
supply line. Clocks and other fast switching digital signals should
be shielded from other parts of the board by digital ground. Avoid
crossover of digital and analog signals if possible. When traces
cross on opposite sides of the board, ensure that they run at right
angles to each other to reduce feedthrough effects through the
board. The best board layout technique is the microstrip technique,
where the component side of the board is dedicated to the ground
plane only and the signal traces are placed on the solder side.
However, this is not always possible with a 2-layer board.
Table 15. LDAC Register
Load DAC Register
LDAC Bits (DB7 to DB0)
LDAC Pin
LDAC Operation
0 1/0
Determined by LDAC pin.
1 X--don't
care
DAC channels update, overriding the LDAC pin. DAC channels see LDAC as 0.
Table 16. 32-Bit Input Shift Register Contents for LDAC Register Function
MSB
LSB
DB31
to
DB28
DB27
DB26
DB25
DB24
DB23
DB22
DB21
DB20
DB19
to
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
X 0 1 1 0 X X X X X DAC
H
DAC
G
DAC
F
DAC
E
DAC
D
DAC
C
DAC
B
DAC
A
Don't
cares
Command bits (C3 to C0)
Address bits (A3 to A0)--
don't cares
Don't
cares
Setting LDAC bit to 1 overrides LDAC pin
AD5628/AD5648/AD5668
Rev. A | Page 27 of 28
OUTLINE DIMENSIONS
4.50
4.40
4.30
14
8
7
1
6.40
BSC
PIN 1
5.10
5.00
4.90
0.65
BSC
SEATING
PLANE
0.15
0.05
0.30
0.19
1.20
MAX
1.05
1.00
0.80
0.20
0.09
8
0
0.75
0.60
0.45
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AB-1
Figure 58. 14-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-14)
Dimensions shown in millimeters
16
9
8
1
PIN 1
SEATING
PLANE
8
0
4.50
4.40
4.30
6.40
BSC
5.10
5.00
4.90
0.65
BSC
0.15
0.05
1.20
MAX
0.20
0.09
0.75
0.60
0.45
0.30
0.19
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 59. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
AD5628/AD5648/AD5668
Rev. A | Page 28 of 28
AD5628 ORDERING GUIDE
Model
Temperature Range
Package Description
Package
Option
Power-On
Reset to Code
Accuracy
Internal
Reference
AD5628BRUZ-1
1
-40C to +105C
14-Lead TSSOP
RU-14
Zero
1 LSB INL
1.25 V
AD5628BRUZ-1REEL7
1
-40C to +105C
14-Lead TSSOP
RU-14
Zero
1 LSB INL
1.25 V
AD5628BRUZ-2
1
-40C to +105C
16-Lead TSSOP
RU-16
Zero
1 LSB INL
2.5 V
AD5628BRUZ-2REEL7
1
-40C to +105C
16-Lead TSSOP
RU-16
Zero
1 LSB INL
2.5 V
AD5628ARUZ-2
1
-40C to +105C
16-Lead TSSOP
RU-16
Zero
2 LSB INL
2.5 V
AD5628ARUZ-2REEL7
1
-40C to +105C
16-Lead TSSOP
RU-16
Zero
2 LSB INL
2.5 V
1
Z = Pb-free part.
AD5648 ORDERING GUIDE
Model
Temperature Range
Package Description
Package
Option
Power-On
Reset to Code
Accuracy
Internal
Reference
AD5648BRUZ-1
1
-40C to +105C
14-Lead TSSOP
RU-14
Zero
4 LSB INL
1.25 V
AD5648BRUZ-1REEL7
1
-40C to +105C
14-Lead TSSOP
RU-14
Zero
4 LSB INL
1.25 V
AD5648BRUZ-2
1
-40C to +105C
16-Lead TSSOP
RU-16
Zero
4 LSB INL
2.5 V
AD5648BRUZ-2REEL7
1
-40C to +105C
16-Lead TSSOP
RU-16
Zero
4 LSB INL
2.5 V
AD5648ARUZ-2
1
-40C to +105C
16-Lead TSSOP
RU-16
Zero
8 LSB INL
2.5 V
AD5648ARUZ-2REEL7
1
-40C to +105C
16-Lead TSSOP
RU-16
Zero
8 LSB INL
2.5 V
1
Z = Pb-free part.
AD5668 ORDERING GUIDE
Model Temperature
Range
Package
Description
Package
Option
Power-On
Reset to Code
Accuracy
Internal
Reference
AD5668BRUZ-1
1
-40C to +105C
16-Lead TSSOP
RU-16
Zero
16 LSB INL
1.25 V
AD5668BRUZ-1REEL7
1
-40C to +105C
16-Lead TSSOP
RU-16
Zero
16 LSB INL
1.25 V
AD5668BRUZ-2
1
-40C to +105C
16-Lead TSSOP
RU-16
Zero
16 LSB INL
2.5 V
AD5668BRUZ-2REEL7
1
-40C to +105C
16-Lead TSSOP
RU-16
Zero
16 LSB INL
2.5 V
AD5668BRUZ-3
1
-40C to +105C
16-Lead TSSOP
RU-16
Midscale
16 LSB INL
2.5 V
AD5668BRUZ-3REEL7
1
-40C to +105C
16-Lead TSSOP
RU-16
Midscale
16 LSB INL
2.5 V
AD5668ARUZ-2
1
-40C to +105C
16-Lead TSSOP
RU-16
Zero
32 LSB INL
2.5 V
AD5668ARUZ-2REEL7
1
-40C to +105C
16-Lead TSSOP
RU-16
Zero
32 LSB INL
2.5 V
AD5668ARUZ-3
1
-40C to +105C
16-Lead TSSOP
RU-16
Midscale
32 LSB INL
2.5 V
AD5668ARUZ-3REEL7
1
-40C to +105C
16-Lead TSSOP
RU-16
Midscale
32 LSB INL
2.5 V
EVAL-AD5668EB
Evaluation
board
1
Z = Pb-free part.
2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05302011/05(A)
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