AD5930 Programmable Frequency Sweep and Output Burst Waveform Generator Data Sheet (Rev. PrF)
Programmable Frequency Sweep and
Output Burst Waveform Generator
Preliminary Technical Data
AD5930
Rev. PrF
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Fax: 781.326.8703
2005 Analog Devices, Inc. All rights reserved.
FEATURES
Programmable frequency profile--no external
components necessary
Ouput frequency up to 25 Mhz
Burst and listen capability
Predefined frequency profile minimizes number
of DSP/controller writes
Sinusoidal/triangular/square wave outputs
Automatic or single pin control of frequency stepping
Frequency starts at known phase--increments at 0 phase
or phase continuous
Powerdown mode (20 A)
+2.3 V to +5.5 V power supply
Extended temperature range -40C to +105C
20-lead TSSOP
APPLICATIONS
Frequency Sweeping/Radar
Network/Impedance Measurements
Incremental Frequency stimulus
Sensory Applications--Proximity and Motion
BFSK
Frequency Bursting/Pulse Trains
GENERAL DESCRIPTION
The AD5930
1
is a waveform generator with programmable
frequency sweep and output burst capability. Utilizing
embedded digital processing allowing enhanced frequency
control the device generates synthesized analog or digital
frequency-stepped waveforms. Because frequency profiles are
preprogrammed continuous write cycles are eliminated, thereby
freeing up valuable DSP/Controller resources. Waveforms start
from a known phase and are incremented phase conti0nuously
allowing phase shifts to be easily determined. Consuming only
8mA the AD5930 provides a convenient low power solution to
waveform generation.
The AD5930 can be operated in three modes. In continuous
output mode the device outputs the required frequency for a
defined length of time and then steps to the next frequency.
The length of time the device outputs a particular frequency
can be either preprogrammed and the device increments the
frequency automatically or alternatively can be incremented
externally via the CTRL pin. In Burst mode, the device outputs
it's frequency for a length of time and then returns to midscale
for a further predefined length of time before stepping to the
next frequency. In MSB mode a digital output is generated.
(continued on Page 3)
1
Protected by US Patent Number 6747583, other patents pending.
FUNCTIONAL BLOCK DIAGRAM
CONTROL
REGISTER
DATA
24
INCR
SYNC
AND CONTROL
SYNC OUT
OPDGND
MSB OUT
IOUT
IOUT
COMP
MCLK
CTRL
INCREMENT
CONTROLLER
FREQUENCY
CONTROLLER
SERIAL INTERFACE
OUTPUT BURST
CONTROLLER
INTERRUPT
STANDBY
DVDD
CAP/2.6V
DGND
AGND AVDD
REF
FS ADJUST
24-BIT
PIPELINED
DOS CORE
DATA
DATA
SYNC
BUFFER
BUFFER
10-BIT
DAC
FSYNC SCLK
SDATA
FULL-SCALE
CONTROL
ON-BOARD
REFERENCE
REGULATOR
VCC
2.5V
05333-001
Figure 1.
AD5930
Preliminary Technical Data
Rev. PrF | Page 2 of 16
TABLE OF CONTENTS
General Description ......................................................................... 3
Specifications..................................................................................... 4
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configurations And Functional Descriptions ....................... 7
Terminology ...................................................................................... 9
Detailed Operation......................................................................... 10
Functional Description.............................................................. 11
Outputs from the AD5930 ........................................................ 11
Programming the AD5930........................................................ 11
Setting up the Sweep .................................................................. 13
Activating and controlling the Sweep...................................... 14
Outline Dimensions ....................................................................... 16
Ordering Guide .......................................................................... 16
REVISION HISTORY
2/05--Revision PrF: Preliminary Version
Preliminary Technical Data
AD5930
Rev. PrF | Page 3 of 16
GENERAL DESCRIPTION
(continued from Page 1)
To program the device, the user enters the start frequency, the
increment step size, the number of increments to be made and
the time interval the part stays at each frequency. The frequency
profile can be initiated by toggling the CTRL pin.
A number of different sweep profiles are offered. Frequencies
can be stepped in triangular-sweep mode continuously
sweeping up and down through the frequency range or in saw-
sweep mode sweeping up but returning to the initial frequency
before initiating the sweep again. In addition a single frequency
or burst can generate without any sweep.
The AD5930 is written to via a 3-wire serial interface, which
operates at clock rates up to 40 MHz. The device operates with a
power supply from 2.3 V to 5.5 V and has a standby function
which allows sections of the device that are not being used to be
powered down.
The AD5930 is available in a 20-lead TSSOP package.
AD5930
Preliminary Technical Data
Rev. PrF | Page 4 of 16
SPECIFICATIONS
A
V
DD
= D
V
DD
= +2.3 V to +5.5 V; AGND = DGND = 0 V; T
A
= T
MIN
to T
MAX
; R
SET
= 6.8 k, R
LOAD
= 200 for IOUT and IOUTB,
unless otherwise noted.
Table 1.
Y
Grade
2
Parameter
Min Typ
Max
Unit Test
Conditions/Comments
SIGNAL DAC SPECIFICATIONS
Resolution
10
Bits
Update Rate
50
MSPS
Iout Fullscale
3
3.124
4.0
mA
Vout peak-to-peak
0.6
V
Vout offset
30
mV
From 0V to the trough of the waveform
Output Compliance
0.8
V
AVDD = 2.3 V, Internal reference used
DC Accuracy:
Integral Nonlinearity (INL)
1
LSB
Differential nonlinearity (DNL)
0.5
LSB
DDS SPECIFICATIONS
Dynamic Specifications:
Signal to Noise Ratio
55
60
dB
f
MCLK
= 50 MHz, f
OUT
= f
MCLK
/4096
Total Harmonic Distortion
-66
-56
dBc
f
MCLK
= 50 MHz, f
OUT
= f
MCLK
/4096
Spurious Free Dynamic Range
(SFDR):
Wideband (0 to Nyquist)
-60
-56
dBc
f
MCLK
= 50 MHz, f
OUT
= f
MCLK
/50
NarrowBand ( 200 kHz)
-78
-67
dBc
f
MCLK
= 50 MHz, f
OUT
= f
MCLK
/50
Clock Feedthrough
-50
dBc
Wake Up Time
1
ms
OUTPUT BUFFER
Vout peak-to peak
D
VDD
V
Squarewave on MSB OUT
Output Rise/Fall Time
12
ns
Output Jitter
120
ps rms
When DAC data MSB is output
VOLTAGE REFERENCE
Internal Reference
1.12
1.18
1.24
V
External Reference Range
1.3
V
REFOUT Input Impedance
1
k
Reference TC
100
ppm/C
LOGIC INPUTS
Input current
10
A
V
INH
, input high voltage
1.7
V
Vdd = 2.3 V to 2.7 V
2.0
V
Vdd = 2.7 V to 5.5 V
V
INL
, input low voltage
0.7
V
Vdd = 2.3 V to 2.7 V
0.8
V
Vdd = 2.7 V to 5.5 V
C
IN
, input capacitance
3
3
pF
LOGIC OUTPUTS
V
OHL
, output high voltage
D
VDD
- 0.8 V
V
I
SINK
= 1 mA
V
OL
, output low voltage
0.4
V
I
SINK
= 1 mA
Floating-state O/P capacitance
8
pF
Preliminary Technical Data
AD5930
Rev. PrF | Page 5 of 16
Y
Grade
2
Parameter
Min Typ
Max
Unit Test
Conditions/Comments
POWER REQUIREMENTS
f
MCLK
= 50 MHz, f
OUT
= f
MCLK
/7
AVDD/DVDD 2.3
5.5
V
I
AA
3.8
5
MA
I
DD
2.0
3
mA
I
AA
+ I
DD
5.8
8
mA
Low Power Sleep Mode
20
A
All outputs powered down, MCLK =0MHz, Serial interface
active
2
Operating temperature range is as follows: Y Version:
-40C to + 105C; typical specifications are at 25C.
3
Guaranteed by Design.
Document Outline
- FEATURES
- APPLICATIONS
- GENERAL DESCRIPTION
-
-
-
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