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1 MSPS 12-Bit Impedance Converter,
Network Analyzer
Preliminary Technical Data
AD5933
Rev. PrA
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Fax: 781.326.8703
2004 Analog Devices, Inc. All rights reserved.
FEATURES
50KHz Max Excitation Output
Impedance Range .1k-20M, 12 Bit Resolution
Selectable System Clock from the following:
PLL, RC Oscillator, External Clock
DSP Real and Imaginary Calculation (FFT)
3V Power Supply,
Programmable Sinewave Output
Frequency Resolution 27 Bits (<0.1Hz)
Frequency Sweep Capability
12 Bit Sampling ADC
ADC Sampling 1MSPS, INL +/- 1LSB Max.
On Chip Temp Sensor allows +/-2 oC accuracy
Serial
I2
C Loading
Temperature Range 40-125oC 16 SSOP
APPLICATIONS
Complex Impedance Measurement
Impedance Spectrometry
Biomedical and Automotive Sensors
Proximity Sensors
FFT Processing
GENERAL DESCRIPTION
The AD5933 is a high precision impedance converter system
solution which combines an on board frequency generator with
a 12 Bit 1MSPS ADC. The frequency generator allows an
external complex impedance to be excited with a known
frequency. The response signal from the impedance is sampled
by the on board ADC and FFT processed by an on-board DSP
engine. The FFT algorithm returns a Real (R) and Imaginary (I)
data word, allowing impedance to be conveniently calculated.
The impedance magnitude and phase is easily calculated using
the following equations:
Magnitude =
R + I
2
2
Phase = Tan (I/R)
-1
To determine the actual real impedance value Z(W) , generally a
frequency sweep is performed. The impedance can be
calculated at each point and a frequency vs magnitude plot can
be created.
The system allows the user to program a 2V PK-PK sinusoidal
signal as excitation to an external load. Output ranges of 1V,
500mV, 200mV can also be programmed. The signal is
provided on chip using DDS techniques. Frequency resolution
of 27 bits (less than 0.1HZ) can be achieved. The clock for the
DDS can be generated from an external reference clock, an
internal RC oscillator or an internal PLL. The PLL has a gain
stage of 512 and typically needs a reference clock of 32KHz on
the MCLK pin.
To perform the frequency sweep, the user must first program
the conditions required for the sweep; start frequency, delta
frequency, step frequency, etc. A Start Command is then
required to begin the sweep.
At each point on the sweep the ADC will take 1024 samples and
calculate a Discrete Fourier Transform to provide the real and
imaginary data for the waveform. The real and imaginary data
is available to the user through the 12C interface.
To determine the impedance of the load at any one frequency
point, Z(w), a measurement system comprised of a trans
impedance amplifier, gain stage and ADC are used to record
data. The gain stage for the response stage is 1 or 5.
The ADC is a low noise, high speed 1MSPS sampling ADC that
operates from a 3V supply. Clocking for both the DDS and
ADC signals is provided externally via the MCLK reference
clock, which is provided externally from a crystal oscillator. The
AD5933 is available in a 16 ld SSOP.
DDS CORE
(27 Bits)
DAC
ADC
(12Bit)
I2C Interface
Digital Control
Logic
SCL
SDA
VOUT = 2V (G=1)
1024 POINT DFT
Z(w)
G=1/0.5/0.2/0.1
VB
RC Osc
4
G=1/5
4
Rfb
IMAGE DATA 16Bits
REAL DATA 16Bits
INTERNAL
BANDGAP
REFERENCE
PLL
TEMP
SENSOR
MCLK
AD5933
Preliminary Technical Data
Rev. PrA | Page 2 of 20
TABLE OF CONTENTS
Specifications..................................................................................... 3
Timing Characteristics..................................................................... 5
Pin Configuration and function description ................................ 6
General Description ......................................................................... 7
Output Stage.................................................................................. 7
Circuit Description....................................................................... 7
Numerical Controlled Oscillator + Phase Modulator ............. 7
SIN ROM ....................................................................................... 8
Response Stage.............................................................................. 8
ADC Operation ............................................................................ 8
DFT Conversion ........................................................................... 8
Temperature Sensor ..................................................................... 9
Register Map (Each Row equals 8 Bits of Data) ......................... 11
Control Register.......................................................................... 13
Control Register Decode: .......................................................... 14
Initialize Sensor with Start Frequency..................................... 14
Start Frequency Sweep............................................................... 14
Increment Frequency ................................................................. 14
Repeat Frequency ....................................................................... 14
Power Down................................................................................ 14
Standby Mode ............................................................................. 14
Read Temperature ...................................................................... 14
Error Checking ........................................................................... 14
RESET .......................................................................................... 14
System Clock............................................................................... 14
Output Voltage............................................................................ 14
Post Gain ..................................................................................... 14
Performing a Frequency Sweep Flow Chart ............................ 15
Serial Bus Interface..................................................................... 15
General I
2
C Timing.................................................................... 15
Writing/Reading to the AD5933 .............................................. 16
Block Write.................................................................................. 17
AD5933 Read Operations ......................................................... 17
Error Correction......................................................................... 18
P.E.C. ............................................................................................ 18
Checksum.................................................................................... 18
User Command Codes .............................................................. 18
Outline Dimensions ....................................................................... 20
ESD Caution................................................................................ 20
REVISION HISTORY
12/04--Revision PrA--Preliminary Version
Preliminary Technical Data
AD5933
Rev. PrA | Page 3 of 20
SPECIFICATIONS
V
DD
= +3.0 V +/- 10%, T
MIN
to T
MAX
unless otherwise noted.
Table 1.
Parameter
B Version
1
Min Typ Max
Unit Test
Conditions/Comments
System Specs:
Impedance Range
.0001 20
M Ohm
Total System Accuracy
1
%
System ppm
TDB ppm/oC
MCLK Update Rate
16
MSPS
Output Stage
Frequency Specs
Output Frequency Range
0 50KHz
Hz
Uni-Polar Sinusoidal Signal.
Frequency Resoltuion
27
Bits.
<0.1 Hz Resolution
MCLK
External Rerference Clock. Typically 16.667MHz.
Initial Frequency Accuracy
0.1
Hz
Output Exitation Accuracy. 0 -50KHz Range.
RC OSCILLATOR
Internal RC Oscillator.
Initial Frequency Accuracy
1.5
%
Output Excitation Accuracy. 0 -50KHz Range.
Calibrated Frequency Accuracy
0.1
Hz
0 -50KHz Range.
1 point Offset Calibration
Frequency Tempco
10
ppm/oC
Requires 2 point User Calibration.
Frequency Jitter
TDB
Jitter on VOUT Pin, 30KHz output.
PLL
PLL Gain
512
INPUT CLOCK RANGE
32
KHZ
Frequency Jitter
TDB
Jitter on VOUT Pin, 30KHz output.
Output Voltage Specs
AC Voltage Range
2.0
Volts
Pk-Pk Unipolar Voltage on Output.
Output Voltage Error
TBD
%
Voltage Error on Pk-Pk Output.
DC Bias
Vdd/2
Volts
DC bias of AC Signal
DC Bias Error
TBD
%
Tolerance of DC Bias
AC Voltage Range
1.0
Volts
Pk-Pk Unipolar Voltage on Output.
Output Voltage Error
TBD
%
Voltage Error on Pk-Pk Output.
DC Bias
Vdd/4
Volts
DC bias of AC Signal
DC Bias Error
1
%
Tolerance of DC Bias
AC Voltage Range
0.4
Volts
Pk-Pk Unipolar Voltage on Output.
Output Voltage Error
TBD
%
Voltage Error on Pk-Pk Output.
DC Bias
Vdd/8
Volts
DC bias of AC Signal
DC Bias Error
TBD
%
Tolerance of DC Bias
AC Voltage Range
0.2
Volts
Pk-Pk Unipolar Voltage on Output.
Output Voltage Error
TBD
%
Voltage Error on Pk-Pk Output.
DC Bias
Vdd/16
Volts
DC bias of AC Signal
DC Bias Error
TBD
%
Tolerance of DC Bias
DC Output Impedance
120
Ohm
Short Circuit Current
75
mA
At 3 Volts.
Short Circuit Current
100
mA
At 5 Volts.
AC Characteristics
Signal to Noise Ratio
60
db
Total Harmonic Distortion
-66
db
Spurious free Dynamic Range
Wideband
60
db
AD5933
Preliminary Technical Data
Rev. PrA | Page 4 of 20
Parameter
B Version
1
Min Typ Max
Unit Test
Conditions/Comments
Narrowband
80
db
Clock Feedthrough
TBD
db
System Response Stage
Analog Input VIN
Input Leakage Current
1
nA
To Pin VIN
Input Capacitance
0.5
pF
To Pin VIN
Input Impedance
100M
Ohm
To Pin VIN
ADC Accuracy
Resolution
12
Sampling Rate
1
MSPS
Integral Nonlinearity
1
LSB
No missing Codes
Differential Nonlinearity
1
LSB
Offset Error
Gain Error
TEMPERATURE SENSOR
Accuracy
1
oC
TA = -40 - 125 DEGREES
Resolution
0.03125
oC
Temperature Conversion Time
TBD
uS
LOGIC INPUTS
Vih, Input High Voltage
2.2
VDD = 3v
Vil, Input Low Voltage
0.8
VDD = 3V
Input Current
1
uA
Input Capacitance
3
pF
POWER REQUIREMENTS
Vdd
3.0
Volts
IDD (Normal Mode)
15
mA
IDD (Powerdown Mode)
TBD
uA
1
Temperature ranges are as follows: B Version: 40C to +125C, typical at 25C.
2
Guaranteed by design and characterization, not production tested.
Preliminary Technical Data
AD5933
Rev. PrA | Page 5 of 20
TIMING CHARACTERISTICS
Table 2. I
2
C Serial Interface
Parameter
1
Limit at T
MIN
, T
MAX
Unit Description
F
SCL
400
kHz max
SCL clock frequency
t
1
2.5
s min
SCL cycle time
t
2
0.6 s
min
t
HIGH
, SCL high time
t
3
1.3 s
min
t
LOW
, SCL low time
t
4
0.6 s
min
t
HD
,
STA
, start/repeated start condition hold time
t
5
100 ns
min
t
SU
,
DAT
, data setup time
t
6
2
0.9 s
max
t
HD
,
DAT
data hold time
0 s
min
t
HD
,
DAT
data hold time
t
7
0.6 s
min
t
SU
,
STA
setup time for repeated start
t
8
0.6 s
min
t
SU
,
STO
stop condition setup time
t
9
1.3 s
min
t
BUF
, bus free time between a stop and a start condition
t
10
300 ns
max
t
F
, fall time of SDA when transmitting
0 ns
min
t
R
, rise time of SCL and SDA when receiving (CMOS compatible)
t
11
300 ns
max
t
F
, fall time of SDA when transmitting
0 ns
min
t
F
, fall time of SDA when receiving (CMOS compatible)
300 ns
max
t
F
, fall time of SCL and SDA when receiving
20 + 0.1 C
B
ns min
t
F
, fall time of SCL and SDA when transmitting
C
B
3
400
pF max
Capacitive load for each bus line
03773-0-007
SCL
SDA
START
CONDITION
REPEATED
START
CONDITION
STOP
CONDITION
t
9
t
3
t
10
t
11
t
4
t
4
t
6
t
2
t
5
t
7
t
8
t
1
Figure 1. I
2
C Interface Timing Diagram
Document Outline
- FEATURES
- APPLICATIONS
- GENERAL DESCRIPTION
-
-
-
-
-
-
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