Document Outline
- FEATURES
- APPLICATIONS
- GENERAL DESCRIPTION
- FUNCTIONAL BLOCK DIAGRAM
- SPECIFICATIONS
- ABSOLUTE MAXIMUM RATINGS
- PIN CONFIGURATION
- ORDERING GUIDE
- PIN FUNCTION DESCRIPTIONS
- Typical Performance Characteristics (per Channel)
- THEORY OF OPERATION
- Differential Ladder (Attenuator)
- AC Coupling
- Gain Control Interface
- Active Feedback Amplifier (Fixed Gain Amp)
- APPLICATIONS
- Connecting Two Amplifiers to Double the Gain Range
- OUTLINE DIMENSIONS
- Revision History
REV. C
a
AD605
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
2004 Analog Devices, Inc. All rights reserved.
Dual, Low Noise, Single-Supply
Variable Gain Amplifier
FUNCTIONAL BLOCK DIAGRAM
PRECISION PASSIVE
INPUT ATTENUATOR
FIXED GAIN
AMPLIFIER
+34.4dB
DIFFERENTIAL
ATTENUATOR
0 TO 48.4dB
OUT
VOCM
VGN
VREF
+IN
IN
GAIN
CONTROL
AND
SCALING
FBK
AD605
FEATURES
Two Independent Linear-in-dB Channels
Input Noise at Maximum Gain: 1.8 nV/
Hz, 2.7 pA/Hz
Bandwidth: 40 MHz (3 dB)
Differential Input
Absolute Gain Range Programmable:
14 dB to +34 dB (FBK Shorted to OUT) Through
0 dB to +48 dB (FBK Open)
Variable Gain Scaling: 20 dB/V Through 40 dB/V
Stable Gain with Temperature and Supply Variations
Single-Ended Unipolar Gain Control
Output Common-Mode Independently Set
Power Shutdown at Lower End of Gain Control
Single 5 V Supply
Low Power: 90 mW/Channel
Drives A/D Converters Directly
APPLICATIONS
Ultrasound and Sonar Time-Gain Control
High Performance AGC Systems
Signal Measurement
GENERAL DESCRIPTION
The AD605 is a low noise, accurate, dual channel, linear-in-dB
variable gain amplifier, which is optimized for any application
requiring high performance, wide bandwidth variable gain con-
trol. Operating from a single 5 V supply, the AD605 provides
differential inputs and unipolar gain control for ease of use.
Added flexibility is achieved with a user-determined gain range
and an external reference input which provides user-determined
gain scaling (dB/V).
The high performance linear-in-dB response of the AD605 is
achieved with the differential input, single supply, exponential
amplifier (DSX-AMP) architecture. Each of the DSX-AMPs
comprise a variable attenuator of 0 dB to 48.4 dB followed by
a high speed fixed gain amplifier. The attenuator is based on a
7-stage R-1.5R ladder network. The attenuation between tap
points is 6.908 dB, and 48.360 dB for the entire ladder network.
The DSX-AMP architecture results in 1.8 nV/
Hz input noise
spectral density and will accept a
2.0 V input signal when
VOCM is biased at VP/2.
Each independent channel of the AD605 provides a gain range
of 48 dB which can be optimized for the application. Gain
ranges between 14 dB to +34 dB and 0 dB to +48 dB can be
selected by a single resistor between pins FBK and OUT. The
lower and upper gain ranges are determined by shorting pin
FBK to OUT, or leaving pin FBK unconnected, respectively.
The two channels of the AD605 can be cascaded to provide 96
dB of very accurate gain range in a monolithic package.
The gain control interface provides an input resistance of approxi-
mately 2 M
and scale factors from 20 dB/V to 30 dB/V for a
VREF input voltage of 2.5 V to 1.67 V, respectively. Note that
scale factors up to 40 dB/V are achievable with reduced accu-
racy for scales above 30 dB/V. The gain scales linearly in dB
with control voltages (VGN) of 0.4 V to 2.4 V for the 20 dB/V
scale and 0.20 V to 1.20 V for the 40 dB/V scale. When VGN
is <50 mV the amplifier is powered down to draw 1.9 mA.
Under normal operation, the quiescent supply current of each
amplifier channel is only 18 mA.
The AD605 is available in 16-lead PDIP and SOIC, and is
guaranteed for operation over the 40
C to +85C tempera-
ture range.
AD605SPECIFICATIONS
2
REV. C
Model
AD605A
AD605B
Parameter
Conditions
Min
Typ
Max
Min Typ
Max
Unit
INPUT CHARACTERISTICS
Input Resistance
175
40
175
40
Input Capacitance
3.0
3.0
pF
Peak Input Voltage
At Minimum Gain
2.5
2.5
2.5
2.5
V
Input Voltage Noise
VGN = 2.9 V
1.8
1.8
nV/
Hz
Input Current Noise
VGN
= 2.9 V
2.7
2.7
pA/
Hz
Noise Figure
R
S
= 50
, f = 10 MHz, VGN = 2.9 V
8.4
8.4
dB
R
S
= 200
, f = 10 MHz, VGN = 2.9 V
12
12
dB
Common-Mode Rejection Ratio
f = 1 MHz, VGN = 2.65 V
20
20
dB
OUTPUT CHARACTERISTICS
3 dB Bandwidth
Constant with Gain
40
40
MHz
Slew Rate
VGN = 1.5 V, Output = 1 V Step
170
170
V/
s
Output Signal Range
R
L
500
2.5
1.5
2.5
1.5
V
Output Impedance
f = 10 MHz
2
2
Output Short-Circuit Current
40
40
mA
Harmonic Distortion
VGN = 1 V, VOUT = 1 V p-p,
HD2
f = 1 MHz
64
64
dBc
HD3
f = 1 MHz
68
68
dBc
HD2
f = 10 MHz
51
51
dBc
HD3
f = 10 MHz
53
53
dBc
Two-Tone Intermodulation
R
S
= 0
, VGN = 2.9 V, VOUT = 1 V p-p
Distortion (IMD)
f = 1 MHz
72
72
dBc
f = 10 MHz
60
60
dBc
1 dB Compression Point
f = 10 MHz, VGN = 2.9 V, Output Referred
+15
+15
dBm
Third Order Intercept
f = 10 MHz, VGN = 2.9 V, VOUT = 1 V p-p,
1
1
dBm
Input Referred
Channel-to-Channel Crosstalk
Ch1: VGN = 2.65 V, Inputs Shorted,
70
70
dB
Ch2: VGN = 1.5 V (Mid Gain), f = 1 MHz,
VOUT = 1 V p-p
Group Delay Variation
1 MHz < f < 10 MHz, Full Gain Range
2.0
2.0
ns
VOCM Input Resistance
45
45
k
ACCURACY
Absolute Gain Error
14 dB to 11 dB
0.25 V < VGN < 0.40 V
1.2
+1.0
+3.0
1.2 +0.75
+3.0
dB
11 dB to +29 dB
0.40 V < VGN < 2.40 V
1.0
0.3
+1.0
1.0
0.2
+1.0
dB
+29 dB to +34 dB
2.40 V < VGN < 2.65 V
3.5
1.25
+1.2
3.5 1.25
+1.2
dB
Gain Scaling Error
0.4 V < VGN < 2.4 V
0.25
0.25
dB/V
Output Offset Voltage
VREF
= 2.500 V, VOCM = 2.500 V
50
30
50
50
30
50
mV
Output Offset Variation
VREF
= 2.500 V, VOCM = 2.500 V
30
95
30
50
mV
GAIN CONTROL INTERFACE
Gain Scaling Factor
VREF = 2.5 V, 0.4 V < VGN < 2.4 V
19
20
21
19
20
21
dB/V
VREF = 1.67 V
30
30
dB/V
Gain Range
FBK Short to OUT
14 +34
14 +34
dB
FBK Open
0 +48
0 +48
dB
Input Voltage (VGN) Range
20 dB/V, VREF = 2.5 V
0.1 2.9
0.1 2.9
V
Input Bias Current
0.4
0.4
A
Input Resistance
2
2
M
Response Time
48 dB Gain Change
0.2
0.2
s
POWER SUPPLY
Supply Voltage
4.5
5.0
5.5
4.5
5.0
5.5
V
Power Dissipation
90
90
mW
VREF Input Resistance
10
10
k
Quiescent Supply Current
VPOS
18
23
18
23
mA
Power Down
VPOS, VGN < 50 mV
1.9
3.0
1.9
3.0
mA
Power-Up Response Time
48 dB Gain, V
OUT
= 2 V p-p
0.6
0.6
s
Power-Down Response Time
0.4
0.4
s
(Each channel @ T
A
= 25 C, V
S
= 5 V, R
S
= 50
, R
L
= 500
, C
L
= 5 pF, VREF = 2.5 V
(Scaling = 20 dB/V), 14 dB to +34 dB gain range, unless otherwise noted.)
AD605
3
REV. C
ABSOLUTE MAXIMUM RATINGS
*
Supply Voltage +V
S
Pins 12, 13 (with Pins 4, 5 = 0 V) . . . . . . . . . . . . . . . 6.5 V
Input Voltage Pins 13, 69, 16 . . . . . . . . . . . . . . . . VPOS, 0
Internal Power Dissipation
Plastic (N) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 W
Small Outline (R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 W
Operating Temperature Range . . . . . . . . . . . 40
C to +85C
Storage Temperature Range . . . . . . . . . . . . 65
C to +150C
Lead Temperature, Soldering 60 seconds . . . . . . . . . . 300
C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
JA
AD605AN
40
C to +85C
PDIP
N-16
85
C/W
AD605AR
40
C to +85C
SOIC
R-16
100
C/W
AD605AR-REEL
40
C to +85C
SOIC 13" Reel
R-16
100
C/W
AD605AR-REEL7
40
C to +85C
SOIC 7" Reel
R-16
100
C/W
AD605BN
40
C to +85C
PDIP
N-16
85
C/W
AD605BR
40
C to +85C
SOIC
R-16
100
C/W
AD605BR-REEL
40
C to +85C
SOIC 13" Reel
R-16
100
C/W
AD605BR-REEL7
40
C to +85C
SOIC 7" Reel
R-16
100
C/W
AD605ACHIPS
DIE
AD605-EB
Evaluation Board
PIN FUNCTION DESCRIPTIONS
16-Lead Package for Dual Channel AD605
Pin No.
Mnemonic
Description
1
VGN1
CH1 Gain-Control Input and Power-Down Pin. If grounded, device is off, otherwise positive voltage
increases gain.
2
IN1
CH1 Negative Input.
3
+IN1
CH1 Positive Input.
4
GND1
Ground.
5
GND2
Ground.
6
+IN2
CH2 Positive Input.
7
IN2
CH2 Negative Input.
8
VGN2
CH2 Gain-Control Input and Power-Down Pin. If grounded, device is off, otherwise positive voltage
increases gain.
9
VOCM
Input to this pin defines common-mode voltage for OUT1 and OUT2.
10
OUT2
CH2 Output.
11
FBK2
Feedback Pin that Selects Gain Range of CH2.
12
VPOS
Positive Supply.
13
VPOS
Positive Supply.
14
FBK1
Feedback Pin that Selects Gain Range of CH1.
15
OUT1
CH1 Output.
16
VREF
Input to this pin sets gain-scaling for both channels: 2.5 V = 20 dB/V, 1.67 V = 30 dB/V.
PIN CONFIGURATION
14
13
12
11
16
15
10
9
8
1
2
3
4
7
6
5
TOP VIEW
(Not to Scale)
AD605
VGN1
VPOS
FBK1
OUT1
VREF
IN1
+IN1
GND1
OUT2
FBK2
VPOS
GND2
+IN2
IN2
VGN2
VOCM
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD605 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
VGN (V)
GAIN (dB)
40
20
0.1
0.5
2.9
0.9
1.3
1.7
2.1
2.5
30
20
10
0
10
40 C, +25 C, +85 C
TPC 1. Gain vs. VGN
V
REF
(V)
GAIN SCALING (dBV)
40.0
37.5
20.0
1.25
1.50
2.50
1.75
2.00
2.25
30.0
27.5
25.0
22.5
35.0
32.5
THEORETICAL
ACTUAL
TPC 4. Gain Scaling vs. V
REF
TPC 7. Gain Error vs. VGN for
Different Gain Scalings
VGN (V)
GAIN (dB)
50
20
0.1
0.5
2.9
0.9
1.3
1.7
2.1
2.5
40
20
10
0
10
30
FBK (OPEN)
FBK (SHORT)
TPC 2. Gain vs. VGN for Different
Gain Ranges
VGN (V)
GAIN ERROR (dB)
3.0
2.5
3.0
0.2
0.7
2.7
1.2
1.7
2.2
1.0
1.5
2.0
2.5
2.0
1.0
1.5
0.5
0.5
0.0
40 C
+85 C
+25 C
TPC 5. Gain Error vs. VGN at
Different Temperatures
DELTA GAIN (dB)
PERCENTAGE
20
6
0
0.8 0.6 0.4
0.2
0.0
0.2
0.4
18
8
4
2
16
12
14
10
0.6
0.8
G(dB) =
G(CH1) G(CH2)
N = 50
TPC 8. Gain Match, VGN1 = VGN2 =
1.0 V
(V
REF
= 2.5 V (20 dB/V Scaling), f = 1 MHz, R
L
= 500
, C
L
= 5 pF, T
A
= 25 C, V
SS
= 5 V)
AD605Typical Performance Characteristics (per Channel)
4
REV. C
VGN (V)
GAIN (dB)
40
20
0.1
0.5
2.9
0.9
1.3
1.7
2.1
2.5
30
20
10
0
10
30dB/V
(V
REF
= 1.67V)
20dB/V
(V
REF
= 2.50V)
ACTUAL
ACTUAL
TPC 3. Gain vs. VGN for Different
Gain Scalings
VGN (V)
GAIN ERROR (dB)
2.0
1.5
2.0
0.2
0.7
2.7
1.2
1.7
2.2
0.0
0.5
1.0
1.5
1.0
0.5
f = 1MHz
f = 5MHz
f = 10MHz
TPC 6. Gain Error vs. VGN at
Different Frequencies
DELTA GAIN (dB)
PERCENTAGE
20
6
0
0.8 0.6 0.4 0.2
0.0
0.2
0.4
0.6
0.8
18
8
4
2
16
12
14
10
G(dB) =
G(CH1) G(CH2)
N = 50
TPC 9. Gain Match, VGN1 = VGN2 =
2.50 V
AD605
5
REV. C
FREQUENCY (Hz)
GAIN (dB)
60
40
60
100k
1M
100M
10M
0
20
40
20
VGN = 2.9V (FBK = OPEN)
VGN = 2.9V (FBK = SHORT)
VGN = 1.5V (FBK = OPEN)
VGN = 1.5V (FBK = SHORT)
VGN = 0.1V (FBK = OPEN)
VGN = 0.1V (FBK = SHORT)
VGN = 0.0V
TPC 10. AC Response
VGN (V)
1000
100
1
0.1
0.5
2.1
10
0.9
1.3
1.7
2.5
2.9
NOISE (nV/
Hz)
TPC 13. Input Referred Noise vs.
VGN
Frequency ( )
100
10
0.1
1
10
1k
100
1
VGN = 2.9V
R
SOURCE
ALONE
NOISE (nV/
Hz)
TPC 16. Input Referred Noise vs.
R
SOURCE
VGN (V)
V
OS
(V)
2.525
2.475
0
0.5
3.0
1.0
1.5
2.0
2.5
2.520
2.495
2.490
2.485
2.480
2.515
2.510
2.500
2.505
V
OCM
= 2.50V
40 C
+25 C
+85 C
TPC 11. Output Offset vs. VGN
TEMPERATURE ( C)
2.00
1.75
1.60
40
90
20
0
20
40
60
80
1.95
1.80
1.70
1.65
1.90
1.85
VGN = 2.9V
NOISE (nV/
Hz)
TPC 14. Input Referred Noise vs.
Temperature
R
SOURCE
( )
NOISE FIGURE (dB)
30
25
5
1
10
1k
100
15
10
20
VGN = 2.9V
TPC 17. Noise TPC vs. R
SOURCE
VGN (V)
130
90
125
110
105
100
95
120
115
0
0.5
3.0
1.0
1.5
2.0
2.5
+85 C
+25 C
40 C
NOISE (nV/
Hz)
TPC 12. Output Referred Noise vs.
VGN
FREQUENCY (Hz)
1.90
1.85
1.60
100k
1M
10M
1.80
1.75
1.70
1.65
VGN = 2.9V
NOISE (nV/
Hz)
TPC 15. Input Referred Noise vs.
Frequency
VGN (V)
NOISE FIGURE (dB)
60
0
0.1
0.5
2.9
0.9
1.3
1.7
2.1
2.5
50
40
30
20
10
R
S
= 50
TPC 18. Noise TPC vs. VGN
AD605
6
REV. C
FREQUENCY (Hz)
HARMONIC DISTORTION (dBc)
30
35
70
100k
1M
100M
10M
50
55
65
60
40
45
V
O
= 1V p-p
VGN = 1.0V
HD2
HD3
TPC 19. Harmonic Distortion vs.
Frequency
VGN (V)
P
IN
(dBm)
15
20
0.1
0.5
2.9
0.9
1.3
1.7
2.1
2.5
10
0
5
10
15
5
FREQ = 10MHz
FREQ = 1MHz
INPUT
GENERATOR
LIMIT = 21 dBm
TPC 22. 1 dB Compression vs. VGN
100ns / DIV
40mV / DIV
V
O
= 200mV p-p
VGN = 1.5V
200
200
253ns
1.253 s
TRIG'D
TPC 25. Small Signal Pulse Response
VGN (V)
0.5
0.8
2.9
1.1
1.4
1.7
2.0
2.3
2.6
HARMONIC DISTORTION (dBc)
35
75
55
60
65
70
40
50
45
HD3
(10MHz)
HD2
(10MHz)
HD2
(1MHz)
HD3
(1MHz)
TPC 20. Harmonic Distortion vs. VGN
VGN (V)
INTERCEPT (dBm)
35
5
30
15
10
5
0
25
20
0.6
1
3
1.4
1.8
2.2
2.6
V
O
= 1V p-p
f = 1MHz
f = 10MHz
TPC 23. Third Order Intercept vs. VGN
VGN (V)
2.9V
0.0V
10
0%
100
90
500mV
200ns
500mV
TPC 26. Power-Up/Down Response
FREQUENCY (MHz)
P
OUT
(dBm)
20
90
120
9.92
9.96
10
10.02
10.04
30
80
100
110
60
70
40
50
f = 10MHz
V
O
= 1V p-p
VGN = 1.0V
TPC 21. Intermodulation Distortion
100ns / DIV
400mV / DIV
V
O
= 2V p-p
VGN = 1.5V
2V
2V
253ns
1.253 s
TPC 24. Large Signal Pulse Response
VGN(V)
2.9V
0.1V
10
0%
100
90
500mV
100ns
500mV
TPC 27. Gain Response
AD605
7
REV. C
FREQUENCY (Hz)
CROSSTALK (dB)
30
40
90
100k
1M
100M
10M
50
60
80
70
VGN1 = 1V
V
OUT1
= 1V p-p
V
IN2
= GND
VGN2 = 2.9V
VGN2 = 2.5V
VGN2 = 2.0V
VGN2 = 0.1V
TPC 28. Crosstalk (CH1 to CH2) vs.
Frequency
TEMPERATURE ( C)
SUPPLY CURRENT (mA)
25
20
0
40
90
20
0
20
40
60
80
15
10
5
+I
S
(AD605)
+I
S
(VGN = 0)
TPC 31. Supply Current (One
Channel) vs. Temperature
FREQUENCY (Hz)
0
10
60
100k
1M
100M
10M
20
30
50
40
CMRR (dB)
V
IN
= 0dBm
VGN = 2.9V
VGN = 2.5V
VGN = 2.0V
VGN = 0.1V
TPC 29. Common-Mode Rejection vs.
Frequency
FREQUENCY (Hz)
INPUT IMPEDANCE (
)
180
175
140
100k
1M
100M
10M
160
155
145
150
170
165
VGN = 2.9V
TPC 30. Input Impedance vs.
Frequency
FREQUENCY (Hz)
16
14
4
100k
1M
100M
10M
12
10
6
8
DELAY (ns)
VGN = 0.1V
VGN = 2.9V
TPC 32. Group Delay vs. Frequency
AD605
8
REV. C
THEORY OF OPERATION
The AD605 is a dual channel, low noise variable gain amplifier.
Figure 1 shows the simplified block diagram of one channel.
Each channel consists of a single-supply X-AMP
(hereafter
called DSX, differential single-supply X-AMP) comprised of
(a) precision passive attenuator (differential ladder)
(b) gain control block
(c) VOCM buffer with supply splitting resistors R3 and R4
(d) active feedback amplifier
1
(AFA) with gain setting
resistors R1 and R2
The linear-in-dB gain response of the AD605 can generally be
described by Equation 1.
G (dB) = (Gain Scaling (dB/V))
(Gain Control (V))
(19 dB (14 dB)
(FB))
(1)
where FB = 0 if FBK-to-OUT are shorted,
FB = 1 if FBK-to-OUT is open.
Each channel provides between 14 dB to +34.4 dB through
0 dB to +48.4 dB of gain depending on the value of the resistance
connected between pin FBK and OUT. The center 40 dB of
gain is exactly linear-in-dB while the gain error increases at the
top and bottom of the range. The gain is set by the gain control
voltage (VGN). The VREF input establishes the gain scaling.
The useful gain scaling range is between 20 dB/V and 40 dB/V for
a VREF voltage of 2.5 V and 1.25 V, respectively. For example,
if FBK to OUT were shorted and VREF were set to 2.50 V (to
establish a gain scaling of 20 dB/V), the gain equation would
simplify to
G (dB) = (20 (dB/V ))
(VGN (V)) 19 dB
(2)
The desired gain can then be achieved by setting the unipolar
gain control (VGN) to a voltage within its nominal operating
range of 0.25 V to 2.65 V (for 20 dB/V gain scaling). The gain is
monotonic for a complete gain control range of 0.1 V to 2.9 V.
Maximum gain can be achieved at a VGN of 2.9 V.
Since the two channels are identical, only Channel 1 will be
used to describe their operation. VREF and VOCM are the only
inputs that are shared by the two channels, and since they are
normally ac grounds, crosstalk between the two channels is
minimized. For highest gain scaling accuracy, VREF should
have an external low impedance voltage source. For low accu-
racy 20 dB/V applications, the VREF input can be decoupled with
a capacitor to ground. In this mode the gain scaling will be
1
To understand the active-feedback amplifier topology, refer to the AD830 data
sheet. The AD830 is a practical implementation of the idea.
determined by the midpoint between +VCC and GND, so care
should be taken to control the supply voltage to 5 V. The input
resistance looking into the VREF pin is 10 k
20%.
The AD605 is a single-supply circuit and the VOCM pin is used
to establish the dc level of the midpoint of this portion of the
circuit. VOCM needs only an external decoupling capacitor to
ground to center the midpoint between the supply voltages (5 V,
GND); however if the dc level of the output is important to the
user (see Applications section for the AD9050 data sheet example),
then VOCM can be specifically set. The input resistance look-
ing into the VOCM pin is 45 k
20%.
Differential Ladder (Attenuator)
The attenuator before the fixed gain amplifier is realized by a
differential 7-stage R-1.5R resistive ladder network with an
untrimmed input resistance of 175
single-ended or 350
differentially. The signal applied at the input of the ladder
network (Figure 2) is attenuated by 6.908 dB per tap; thus, the
attenuation at the first tap is 6.908 dB, at the second, 13.816 dB,
and so on all the way to the last tap where the attenuation is
48.356 dB. A unique circuit technique is used to interpolate
continuously between the tap points, thereby providing continu-
ous attenuation from 0 dB to 48.36 dB. One can think of the
ladder network together with the interpolation mechanism as a
voltage-controlled potentiometer.
Since the DSX is a single-supply circuit, some means of biasing
its inputs must be provided. Node MID together with the
VOCM buffer performs this function. Without internal biasing,
external biasing would be required. If not done carefully, the
biasing network can introduce additional noise and offsets. By
providing internal biasing, the user is relieved of this task and
only needs to ac couple the signal into the DSX. It should be
made clear again that the input to the DSX is still fully differen-
tial if driven differentially, i.e., pins +IN and IN see the same
signal but with opposite polarity. What changes is the load as
seen by the driver; it is 175
when each input is driven single-
ended, but 350
when driven differentially. This can be easily
explained when thinking of the ladder network as just two 175
resistors connected back-to-back with the middle node, MID,
being biased by the VOCM buffer. A differential signal applied
between nodes +IN and IN will result in zero current into
node MID, but a single-ended signal applied to either input
+IN or IN while the other input is ac grounded will cause the
current delivered by the source to flow into the VOCM buffer
via node MID.
R1
820
VREF
VGN
VPOS
VOCM
R3
200k
C3
OUT
DISTRIBUTED G
M
175
175
G1
GAIN
CONTROL
Ao
G2
R2
20
R4
200k
EXT
+IN
IN
FBK
3.36k
DIFFERENTIAL
ATTENUATOR
EXT
C2
C1
Figure 1. Simplified Block Diagram of a Single Channel of the AD605
AD605
9
REV. C
From these equations one can see that all gain curves intercept
at the same 19 dB point; this intercept will be 14 dB higher
(5 dB) if the FBK to OUT connection is left open. Outside
of the central linear range, the gain starts to deviate from the
ideal control law but still provides another 8.4 dB of range.
For a given gain scaling one can calculate V
REF
as shown in
Equation 6.
V
REF
=
2.500V
20 dB /V
Gain Scale
(6)
35
30
25
20
15
10
5
0
5
10
15
20
GAIN (dB)
40dB/V
30dB/V
20dB/V
LINEAR-IN-dB RANGE
OF AD605
1.0
0.5
1.5
2.0
2.5
3.0
GAIN CONTROL VOLTAGE
Figure 3. Ideal Gain Curves vs. V
REF
Usable gain control voltage ranges are 0.1 V to 2.9 V for 20 dB/V
scale and 0.1 V to 1.45 V for the 40 dB/V scale. VGN voltages
of less than 0.1 V are not used for gain control since below
50 mV the channel is powered down. This can be used to con-
serve power and at the same time gate-off the signal. The supply
current for a powered-down channel is 1.9 mA, the response
time to power the device on or off is less than 1
s.
Active Feedback Amplifier (Fixed Gain Amp)
To achieve single-supply operation and a fully differential input
to the DSX, an active feedback amplifier (AFA) was utilized.
The AFA is basically an op amp with two g
m
stages; one of the
active stages is used in the feedback path (therefore the name),
while the other is used as a differential input. Note that the
differential input is an open-loop g
m
stage which requires that it
be highly linear over the expected input signal range. In this
design, the g
m
stage that senses the voltages on the attenuator is
a distributed one; for example, there are as many g
m
stages as
there are taps on the ladder network. Only a few of them are on
at any one time, depending on the gain control voltage.
R
6.908dB
R
1.5R
1.5R
R
R
13.82dB
R
1.5R
1.5R
R
20.72dB
R
1.5R
1.5R
R
27.63dB
R
1.5R
1.5R
R
34.54dB
R
1.5R
1.5R
R
41.45dB
R
1.5R
1.5R
R
48.36dB
1.5R
1.5R
175
175
+IN
MID
IN
NOTE: R = 96
1.5R = 144
Figure 2. R-1.5R Dual Ladder Network
One feature of the X-AMP architecture is that the output referred
noise is constant versus gain over most of the gain range. This
can be easily explained by looking at Figure 2 and observing
that the tap resistance is equal for all taps after only a few taps
away from the inputs. The resistance seen looking into each tap is
54.4
which makes 0.95 nV/Hz of Johnson noise spectral
density. Since there are two attenuators, the overall noise
contribution of the ladder network is
2 times 0.95 nV/Hz
or 1.34 nV/
Hz, a large fraction of the total DSX noise. The rest
of the DSX circuit components contribute another 1.20 nV/
Hz
which together with the attenuator produces 1.8 nV/
Hz of
total DSX input referred noise.
AC Coupling
The DSX is a single, single-supply circuit and therefore its
inputs need to be ac-coupled to accommodate ground-based
signals. External capacitors C1 and C2 in Figure 1 level shift
the input signal from ground to the dc value established by
VOCM (nominal 2.5 V). C1 and C2, together with the 175
looking into each of DSX inputs (+IN and IN), will act as
high-pass filters with corner frequencies depending on the
values chosen for C1 and C2. For example, if C1 and C2 are
0.1
F, then together with the 175 input resistance of each
side of the differential ladder of the DSX, a 3 dB high-pass
corner at 9.1 kHz is formed.
If the DSX output needs to be ground referenced, then another
ac-coupling capacitor will be required for level shifting. This
capacitor will also eliminate any dc offsets contributed by the
DSX. With a nominal load of 500
and a 0.1 F coupling
capacitor, this adds a high-pass filter with 3 dB corner fre-
quency at about 3.2 kHz.
The choice for all three of these coupling capacitors depends on
the application. They should allow the signals of interest to pass
unattenuated, while at the same time they can be used to limit
the low frequency noise in the system.
Gain Control Interface
The gain control interface provides an input resistance of
approximately 2 M
at pin VGN1 and gain scaling factors
from 20 dB/V to 40 dB/V for VREF input voltages of 2.5 V to
1.25 V, respectively. The gain varies linearly-in-dB for the cen-
ter 40 dB of gain range, that is for VGN equal to 0.4 V to 2.4 V
for the 20 dB/V scale, and 0.25 V to 1.25 V for the 40 dB/V
scale. Figure 3 shows the ideal gain curves when the FBK to
OUT connection is shorted as described by the following
equations:
G (20 dB/V ) = 20
VGN 19, VREF = 2.500 V
(3)
G (30 dB/V ) = 30
VGN 19, VREF = 1.6666 V
(4)
G (40 dB/V ) = 40
VGN 19, VREF = 1.250 V
(5)
AD605
10
REV. C
The AFA makes a differential input structure possible since one
of its inputs (G1) is fully differential; this input is made up of a
distributed gm stage. The second input (G2) is used for feed-
back. The output of G1 will be some function of the voltages
sensed on the attenuator taps which is applied to a high-gain
amplifier (A0). Because of negative feedback, the differential
input to the high-gain amplifier has to be zero; this in turn implies
that the differential input voltage to G2 times g
m2
(the transcon-
ductance of G2) has to be equal to the differential input voltage
to G1 times g
m1
(the transconductance of G1). Therefore the
overall gain function of the AFA is
V
V
gm
gm
R
R
R
OUT
ATTEN
=
1
2
1
2
2
(7)
where V
OUT
is the output voltage, V
ATTEN
is the effective voltage
sensed on the attenuator, (R1 + R2)/R2 = 42, and g
m1
/g
m2
=
1.25; the overall gain is thus 52.5 (34.4 dB).
The AFA has additional features: (1) inverting the output signal
by switching the positive and negative input to the ladder network;
(2) the possibility of using the IN input as a second signal input;
and (3) independent control of the DSX common-mode voltage.
Under normal operating conditions it is best to just connect a
decoupling capacitor to pin VOCM in which case the common-
mode voltage of the DSX is half the supply voltage; this allows for
maximum signal swing. Nevertheless, the common-mode voltage
can be shifted up or down by directly applying a voltage to VOCM.
It can also be used as another signal input, the only limitation
being the rather low slew rate of the VOCM buffer.
If the dc level of the output signal is not critical, another coupling
capacitor is normally used at the output of the DSX; again this
is done for level shifting and to eliminate any dc offsets contrib-
uted by the DSX (see AC Coupling section).
The gain range of the DSX is programmable by a resistor con-
nected between pins FBK and OUT. The possible ranges are
14 dB to +34.4 dB when the pins are shorted together, to 0 dB
to +48.4 dB when FBK is left open. Note that for the higher
gain range, the bandwidth of the amplifier is reduced by a factor
of five to about 8 MHz since the gain increased by 14 dB. This
is the case for any constant gain bandwidth product amplifier
which includes the active feedback amplifier.
APPLICATIONS
The basic circuit in Figure 4 shows the connections for one chan-
nel of the AD605 with a gain range of 14 dB to +34.4 dB. The
signal is applied at Pin 3. The ac-coupling capacitors before pins
IN1 and +IN1 should be selected according to the required lower
cutoff frequency. In this example, the 0.1
F capacitors to-
gether with the 175
of each of the DSX input pins provides a
3 dB high-pass corner of about 9.1 kHz. The upper cutoff
frequency is determined by the amplifier and is 40 MHz.
14
13
12
11
16
15
10
9
8
1
2
3
4
7
6
5
VREF
GND1
+IN1
IN1
VGN1
OUT1
FBK1
VPOS
IN2
+IN2
GND2
VPOS
FBK2
OUT2
VOCM
VGN2
AD605
0.1 F
0.1 F
VGN
V
IN
0.1 F
5V
0.1 F
OUT
2.500V
Figure 4. Basic Connections for a Single Channel
As shown here, the output is ac-coupled for optimum perfor-
mance. In the case of connecting to the 10-bit 40 MSPS A/D
converter AD9050, ac coupling can be eliminated as long as
pin VOCM is biased by the same 3.3 V common-mode voltage
as the AD9050.
Pin VREF requires a voltage of 1.25 V to 2.5 V, with gain
scaling between 40 dB/V and 20 dB/V, respectively. Voltage
VGN controls the gain; its nominal operating range is from
0.25 V to 2.65 V for 20 dB/V gain scaling, and 0.125 V to
1.325 V for 40 dB/V scaling. When this pin is taken to ground,
the channel will power down and disable its output.
Connecting Two Amplifiers to Double the Gain Range
Figure 5 shows the two channels of the AD605 connected in
series to provide a total gain range of 96.8 dB. When R1 and R2
are shorts, the gain range will be from 28 dB to +68.8 dB with
a slightly reduced bandwidth of about 30 MHz. The reduction
in bandwidth is due to two identical low-pass circuits being
connected in series; in the case of two identical single-pole low-
pass filters, the bandwidth would be reduced by exactly
2. If
R1 and R2 are replaced by open circuits, i.e., Pins FBK1 and
FBK2 are left unconnected, then the gain range will shift up by
28 dB to 0 dB to +96.8 dB. As noted earlier, the bandwidth of
each individual channel will be reduced by a factor of 5 to
about 8 MHz since the gain increased by 14 dB. In addition,
there is still the
2 reduction because of the series connection of
the two channels which results in a final bandwidth of the higher
gain version of about 6 MHz.
14
13
12
11
16
15
10
9
8
1
2
3
4
7
6
5
VREF
GND1
+IN1
IN1
VGN1
OUT1
FBK1
VPOS
IN2
+IN2
GND2
VPOS
FBK2
OUT2
VOCM
VGN2
AD605
C2
0.1 F
VGN
V
IN
R1
5V
OUT
2.500V
C1
0.1 F
C3
0.1 F
C4
0.1 F
C6
0.1 F
R2
C5
0.1 F
Figure 5. Doubling the Gain Range with Two Amplifiers
AD605
11
REV. C
Two other easy combinations are possible to provide a gain
range of 14 dB to +82.8 dB: (1) make R1 a short and R2 an
open; or (2) make R1 an open and R2 a short. The bandwidth
for both of these cases will be dominated by the channel that is
set to the higher gain and will be about 8 MHz. From a noise
standpoint, the second choice is the best since by increasing the
gain of the first amplifier, the second amplifier's noise will have
less of an impact on the total output noise. One further observa-
tion regarding noise is that by increasing the gain the output
noise will increase proportionally; therefore, there is no increase
in signal-to-noise ratio. It will actually stay fixed.
It should be noted that by selecting the appropriate values of R1
and R2, any gain range between 28 dB to +68.8 dB and 0 dB
to +96.8 dB can be achieved with the circuit in Figure 5. When
using any value other than shorts and opens for R1 and R2, the
final value of the gain range will depend on external resistors
matching on-chip resistors. Since the internal resistors can vary
by as much as
20%, the actual values for a particular gain have
to be determined empirically. Note that the two channels within
one part will match quite well; therefore, R1 will track R2 in
Figure 5.
C3 is not required since the common-mode voltage at Pin OUT1
should be identical to the one at Pins +IN2 and IN2. However,
since only 1 mV of offset at the output of the first DSX will
introduce an offset of 53 mV when the second DSX is set to the
maximum gain of the lowest gain range (34.4 dB), and 263 mV
when set to the maximum gain of the highest gain range (48.4 dB),
it is important to include ac coupling to get the maximum dy-
namic range at the output of the cascaded amplifiers. C5 is
necessary if the output signal needs to be referenced to any
common-mode level other than half of the supply as is provided
by Pin OUT2.
Figure 6 shows the gain versus VGN for the circuit in Figure 5
at 1 MHz and the lowest gain range (14 dB to +34.4 dB). Note
that the gain scaling is 40 dB/V, double the 20 dB/V of an indi-
vidual DSX; this is the result of the parallel connection of the
gain control inputs, VGN1 and VGN2. One could of course
also sequentially increase the gain by first increasing the gain of
Channel 1 and then Channel 2. In that case VGN1 and VGN2
will have to be driven from separate voltage sources, for instance
two separate DACs. Figure 7 shows the gain error of Figure 5.
VGN (V)
GAIN (dB)
80
40
0.1
0.5
2.9
f = 1MHz
THEORETICAL
ACTUAL
0
0.9
1.3
1.7
2.1
2.5
70
20
10
20
30
50
30
60
40
10
Figure 6. Gain vs. VGN for the Circuit in Figure 5
VGN (V)
GAIN ERROR (dB)
4
3
4
0.2
0.7
2.7
1.2
1.7
2.2
0
1
2
3
2
1
f = 1MHz
Figure 7. Gain Error vs. VGN for the Circuit in Figure 5
AD605
12
REV. C
C0054107/04(C)
16-Lead Plastic Dual In-Line Package [PDIP]
(N-16)
Dimensions shown in inches and (millimeters)
16
1
8
9
0.295 (7.49)
0.285 (7.24)
0.275 (6.99)
0.100 (2.54)
BSC
SEATING
PLANE
0.015 (0.38)
MIN
0.180 (4.57)
MAX
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.150 (3.81)
0.130 (3.30)
0.110 (2.79)
0.060 (1.52)
0.050 (1.27)
0.045 (1.14)
0.150 (3.81)
0.135 (3.43)
0.120 (3.05)
0.015 (0.38)
0.010 (0.25)
0.008 (0.20)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MO-095AC
0.785 (19.94)
0.765 (19.43)
0.745 (18.92)
16-Lead Standard Small Outline Package [SOIC]
Narrow Body
(R-16)
Dimensions shown in millimeters and (inches)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MS-012AC
16
9
8
1
4.00 (0.1575)
3.80 (0.1496)
10.00 (0.3937)
9.80 (0.3858)
1.27 (0.0500)
BSC
6.20 (0.2441)
5.80 (0.2283)
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0039)
0.51 (0.0201)
0.31 (0.0122)
1.75 (0.0689)
1.35 (0.0531)
8
0
0.50 (0.0197)
0.25 (0.0098)
1.27 (0.0500)
0.40 (0.0157)
COPLANARITY
0.10
45
0.25 (0.0098)
0.17 (0.0067)
OUTLINE DIMENSIONS
Revision History
Location
Page
7/04--Data Sheet Changed from REV. B to REV. C.
Edits to GENERAL DESCRIPTION ..............................................................................................................................................1
Edits to SPECIFICATIONS ...........................................................................................................................................................2
Edits to ORDERING GUIDE .........................................................................................................................................................3
Change to TPC 22 ..........................................................................................................................................................................6
Updated OUTLINE DIMENSIONS.............................................................................................................................................12
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