REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
Low Noise, Low Drift
FET Op Amp
AD645
FEATURES
Improved Replacement for Burr-Brown
OPA-111 and OPA-121 Op Amp
LOW NOISE
2 V p-p max, 0.1 Hz to 10 Hz
10 nV/
Hz max at 10 kHz
11 fA p-p Current Noise 0.1 Hz to 10 Hz
HIGH DC ACCURACY
250 V max Offset Voltage
1 V/ C max Drift
1.5 pA max Input Bias Current
114 dB Open-Loop Gain
Available in Plastic Mini-DIP, 8-Pin Header Packages, or
Chip Form
APPLICATIONS
Low Noise Photodiode Preamps
CT Scanners
Precision I-V Converters
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
PRODUCT DESCRIPTION
The AD645 is a low noise, precision FET input op amp. It of-
fers the pico amp level input currents of a FET input device
coupled with offset drift and input voltage noise comparable to a
high performance bipolar input amplifier.
The AD645 has been improved to offer the lowest offset drift in
a FET op amp, 1
V/
C. Offset voltage drift is measured and
trimmed at wafer level for the lowest cost possible. An inher-
ently low noise architecture and advanced manufacturing tech-
niques result in a device with a guaranteed low input voltage
noise of 2
V p-p, 0.1 Hz to 10 Hz. This level of dc performance
along with low input currents make the AD645 an excellent
choice for high impedance applications where stability is of
prime concern.
1k
100
1.0
10
10k
1k
1
10
100
VOLTAGE NOISE SPECTRAL DENSITY
nV/ Hz
FREQUENCY Hz
Figure 1. AD645 Voltage Noise Spectral Density vs.
Frequency
CONNECTION DIAGRAMS
TO-99 (H) Package
8-Pin Plastic Mini-DIP
(N) Package
IMPROVED
DRIFT
The AD645 is available in six performance grades. The AD645J
and AD645K are rated over the commercial temperature range
of 0
C to +70
C. The AD645A, AD645B, and the ultra-
precision AD645C are rated over the industrial temperature
range of 40
C to +85
C. The AD645S is rated over the military
temperature range of 55
C to +125
C and is available
processed to MIL-STD-883B.
The AD645 is available in an 8-pin plastic mini-DIP, 8-pin
header, or in die form.
PRODUCT HIGHLIGHTS
1. Guaranteed and tested low frequency noise of 2
V p-p max
and 20 nV/
Hz
at 100 Hz makes the AD645C ideal for low
noise applications where a FET input op amp is needed.
2. Low V
OS
drift of 1
V/
C max makes the AD645C an excel-
lent choice for applications requiring ultimate stability.
3. Low input bias current and current noise (11 fA p-p 0.1 Hz to
10 Hz) allow the AD645 to be used as a high precision
preamp for current output sensors such as photodiodes, or as
a buffer for high source impedance voltage output sensors.
INPUT OFFSET VOLTAGE DRIFT
V/
C
0.5
2.0
1.0
1.5
2.5
2.5
1.5
1.0
0.5
2.0
0.0
NUMBER OF UNITS
0
15
5
10
30
25
20
Figure 2. Typical Distribution of Average Input Offset
Voltage Drift (196 Units)
OUTPUT
V
NOTE: CASE IS CONNECTED
TO PIN 8
OFFSET
NULL
IN
+
IN
CASE
3
4
5
6
7
8
AD645
1
2
OFFSET
NULL
+V
8
7
6
5
TOP VIEW
AD645
1
4
2
3
NC = NO CONNECT
OFFSET
NULL
IN
NC
OUTPUT
OFFSET
NULL
VS
+IN
+VS
AD645SPECIFICATIONS
Model
AD645J/A
AD645K/B
AD645C
AD645S
Conditions
1
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Units
INPUT OFFSET VOLTAGE
1
Initial Offset
100
500
50
250
50
250
100
500
V
Offset
T
MIN
T
MAX
300
1000
100
400
75
300
500
1500
V
Drift (Average)
3
10/5
1
5/2
0.5
1
4
10
V/
C
vs. Supply (PSRR)
90
110
94
110
94
110
90
110
dB
vs. Supply
T
MIN
T
MAX
100
90
100
90
100
86
95
dB
INPUT BIAS CURRENT
2
Either Input
V
CM
= 0 V
0.7/1.8
3/5
0.7/1.8 1.5/3
1.8
3
1.8
5
pA
Either Input
@ T
MAX
V
CM
= 0 V
16/115
16/115
115
1800
pA
Either Input
V
CM
= +10 V
0.8/1.9
0.8/1.9
1.9
1.9
pA
Offset Current
V
CM
= 0 V
0.1
1.0
0.1
0.5
0.1
0.5
0.1
1.0
pA
Offset Current
@ T
MAX
V
CM
= 0 V
2/6
2/6
6
100
pA
INPUT VOLTAGE NOISE
0.1 to 10 Hz
1.0
3.0
1.0
2.5
1
2
1.0
3.3
V p-p
f = 10 Hz
20
50
20
40
20
40
20
50
nV/
Hz
f = 100 Hz
10
30
10
20
10
20
10
30
nV/
Hz
f = 1 kHz
9
15
9
12
9
12
9
15
nV/
Hz
f = 10 kHz
8
10
8
10
8
10
8
10
nV/
Hz
INPUT CURRENT NOISE
f = 0.1 to 10 Hz
11
20
11
15
11
15
11
20
fA p-p
f = 0.1 thru 20 kHz
0.6
1.1
0.6
0.8
0.6
0.8
0.6
1.1
fA/
Hz
FREQUENCY RESPONSE
Unity Gain, Small Signal
2
2
2
2
MHz
Full Power Response
V
O
= 20 V p-p
R
LOAD
= 2 k
16
32
16
32
16
32
16
32
kHz
Slew Rate, Unity Gain
V
OUT
= 20 V p-p
R
LOAD
= 2 k
1
2
1
2
1
2
1
2
V/
s
SETTLING TIME
3
To 0.1%
6
6
6
6
s
To 0.01%
8
8
8
8
s
Overload Recovery
4
50% Overdrive
5
5
5
5
s
Total Harmonic
f = 1 kHz
Distortion
R
LOAD
2 k
V
O
= 3 V rms
0.0006
0.0006
0.0006
0.0006
%
INPUT IMPEDANCE
Differential
V
DIFF
=
1 V
10
12
1
10
12
1
10
12
1
10
12
1
pF
Common-Mode
10
14
2.2
10
14
2.2
10
14
2.2
10
14
2.2
pF
INPUT VOLTAGE RANGE
Differential
5
20
20
20
20
V
Common-Mode Voltage
10
+11, 10.4
10
+11, 10.4
10
+11, 10.4
10
+11, 10.4
V
Over Max Oper. Range
10
10
10
10
V
Common-Mode
Rejection Ratio
V
CM
=
10 V
90
110
94
110
94
110
90
110
dB
T
MIN
T
MAX
100
90
100
90
100
86
100
dB
OPEN-LOOP GAIN
V
O
=
10 V
R
LOAD
2 k
114
130
120
130
120
130
114
130
dB
T
MIN
T
MAX
114
114
110
dB
OUTPUT CHARACTERISTICS
Voltage
R
LOAD
2 k
10
11
10
11
10
11
10
11
V
T
MIN
T
MAX
10
10
10
10
V
Current
V
OUT
=
10 V
5
10
5
10
5
10
5
10
mA
Short Circuit
15
15
15
15
mA
POWER SUPPLY
Rated Performance
15
15
15
15
V
Operating Range
5
18
5
18
5
18
5
18
V
Quiescent Current
3.0
3.5
3.0
3.5
3.0
3.5
3.0
3.5
mA
Transistor Count
# of Transistors
62
62
62
62
NOTES
1
Input offset voltage specifications are guaranteed after 5 minutes of operation at T
A
= +25
C.
2
Bias current specifications are guaranteed maximum at either input after 5 minutes of operation at T
A
= +25
C. For higher temperature, the current doubles every 10
C.
3
Gain = 1, R
LOAD
= 2 k
.
4
Defined as the time required for the amplifier's output to return to normal operation after removal of a 50% overload from the amplifier input.
5
Defined as the maximum continuous voltage between the inputs such that neither input exceeds
10 V from ground.
All min and max specifications are guaranteed.
Specifications subject to change without notice.
REV. B
2
(@ +25 C, and 15 V dc, unless otherwise noted)
AD645
3
REV. B
ORDERING GUIDE
Model
1
Temperature Range
Package Option
2
AD645JN
0
C to +70
C
N-8
AD645KN
0
C to +70
C
N-8
AD645AH
40
C to +85
C
H-08A
AD645BH
40
C to +85
C
H-08A
AD645CH
40
C to +85
C
H-08A
AD645SH/883B
55
C to +125
C
H-08A
NOTES
1
Chips are also available.
2
N = Plastic Mini-DIP; H = Metal Can.
ABSOLUTE MAXIMUM RATINGS
1
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18 V
Internal Power Dissipation
2
(@ T
A
= +25
C)
8-Pin Header Package . . . . . . . . . . . . . . . . . . . . . . 500 mW
8-Pin Mini-DIP Package . . . . . . . . . . . . . . . . . . . . 750 mW
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
V
S
Output Short Circuit Duration . . . . . . . . . . . . . . . . Indefinite
Differential Input Voltage . . . . . . . . . . . . . . . . . . +V
S
and V
S
Storage Temperature Range (H) . . . . . . . . . 65
C to +150
C
Storage Temperature Range (N) . . . . . . . . . 65
C to +125
C
Operating Temperature Range
AD645J/K . . . . . . . . . . . . . . . . . . . . . . . . . . . 0
C to +70
C
AD645A/B/C . . . . . . . . . . . . . . . . . . . . . . . 40
C to +85
C
AD645S . . . . . . . . . . . . . . . . . . . . . . . . . . 55
C to +125
C
Lead Temperature Range
(Soldering 60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . +300
C
NOTES
1
Stresses above those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational section of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device
reliability.
2
Thermal Characteristics:
8-Pin Plastic Mini-DIP Package:
JA
= 100
C/Watt
8-Pin Header Package:
JA
= 200
C/Watt
800
700
600
400
300
200
100
0
500
NUMBER OF UNITS
INPUT OFFSET VOLTAGE mV
1.0
0.8
0.4 0.2 0.0
0.4
0.6
1.0
0.6
0.2
0.8
Figure 4. Typical Distribution of Input
Offset Voltage (1855 Units)
NUMBER OF UNITS
120
110
100
90
80
70
60
50
40
30
10
20
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
INPUT BIAS CURRENT pA
Figure 5. Typical Distribution of Input
Bias Current (576 Units)
INPUT VOLTAGE NOISE
V p-p
25
20
15
10
5
0
NUMBER OF UNITS
0.4
1.0
1.2
1.4
1.6
1.8
0.6
0.8
Figure 6. Typical Distribution of 0.1 Hz
to 10 Hz Voltage Noise (202 Units)
WARNING!
ESD SENSITIVE DEVICE
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD645 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
METALIZATION PHOTOGRAPH
Dimensions shown in inches and (mm).
Contact factory for latest dimensions.
AD645
10k
5
1
6
V ADJUST
OS
3
+V
S
7
2
V
S
4
Figure 3. AD645 Offset Null Configuration
REV. B
4
AD645Typical Characteristics
(@ +25 C, 15 V unless otherwise noted)
CURRENT NOISE SPECTRAL DENSITY fA/
Hz
100
1k
10k
100k
1.0
10
100
FREQUENCY Hz
10
1M
0.1
1
Figure 7. Current Noise Spectral
Density vs. Frequency
1.0
10
100
SOURCE RESISTANCE
1k
10
9
10
8
10
7
10
6
10
5
10
3
10
4
NOISE BANDWIDTH: 0.1 to 10Hz
INPUT VOLTAGE NOISE
V p-p
Figure 10. Input Voltage Noise vs.
Source Resistance
0
1
2
3
4
5
WARM-UP TIME Minutes
CHANGE IN INPUT OFFSET VOLTAGE
V
50
25
0
25
50
T = +25 C
A
V =
15V
S
Figure 13. Change in Input Offset
Voltage vs. Warmup Time
1k
100
10
0
1
10
100
1k
10k
100k
FREQUENCY Hz
VOLTAGE NOISE SPECTRAL DENSITY nV/ Hz
Figure 8. Voltage Noise Spectral
Density vs. Frequency
VOLTAGE NOISE
nV/
Hz
10
15
20
25
5
CURRENT NOISE fA/
Hz
100
10
0.1
0.01
CURRENT NOISE
VOLTAGE NOISE
TEMPERATURE C
60
0
40
20
20
40
60
80
100 120 140
f = 1kHz
o
1
Figure 11. Voltage and Current
Noise Spectral Density vs.
Temperature
0
1
2
3
4
5
TIME FROM THERMAL SHOCK Minutes
CHANGE IN INPUT OFFSET VOLTAGE
V
150
75
0
150
75
T
A
= 25
C TO T
A
= 85
C
Figure 14. Change in Input Offset
Voltage vs. Time from Thermal
Shock
10
100
1k
10k
10
100
1000
FREQUENCY Hz
1.0
100k
1
0.1
R = 10M
S
R = 1M
S
R = 100k
S
R = 100
S
Hz
VOLTAGE NOISE SPECTRAL DENSITY nV
Figure 9. Voltage Noise Spectral
Density vs. Frequency for Various
Source Resistances
VOLTAGE NOISE SPECTRAL DENSITY @ 1kHz nV/
Hz
100
1k
10k
100k
1.0
10
100
SOURCE RESISTANCE
1M
10M
100M
1k
SOURCE
RESISTANCE
NOISE OF AD645
AND RESISTOR
RESISTOR NOISE
ONLY
Figure 12. Voltage Noise Spectral
Density @ 1 kHz vs. Source
Resistance
INPUT BIAS CURRENT Amps
INPUT OFFSET CURRENT Amps
60
40
20
0
20
40
60
80
100
120 140
TEMPERATURE C
10
9
10
10
10
11
10
12
10
13
10
14
10
9
10
10
10
11
10
12
10
13
10
14
INPUT
BIAS
CURRENT
INPUT
OFFSET
CURRENT
Figure 15. Input Bias and Offset
Currents vs. Temperature
AD645
5
REV. B
INPUT BIAS CURRENT pA
0.1
1.0
10
0
COMMON MODE VOLTAGE Volts
T
A
= +25
C
V
S
=
15V
H PACKAGE
20
15
10
5
5
10
15
Figure 16. Input Bias Current vs.
Common-Mode Voltage
10
5
0
5
10
COMMON-MODE REJECTION dB
COMMON MODE VOLTAGE Volts
15
15
70
110
90
100
80
120
Figure 19. Common-Mode
Rejection vs. Input Common-Mode
Voltage
SL
EW
RAT
E
Vo
l
t
s
/
s
1.0
2.0
3.0
4.0
4.0
3.0
2.0
G
A
I
N
-
BANDW
I
D
T
H
PRO
DUCT
M
H
z
SUPPLY VOLTAGE Volts
0
5
10
15
20
GAIN-BANDW IDTH
SLEW RATE
Figure 22. Gain-Bandwidth and
Slew Rate vs. Supply Voltage
100
1k
10k
100k
FREQUENCY Hz
1M
10M
POWER SUPPLY REJECTION dB
100
80
60
40
20
0
120
10
1
PSRR
+
PSRR
Figure 17. Power Supply Rejection
vs. Frequency
100
1k
10k
100k
FREQUENCY Hz
1M
10M
OP
E
N
-
L
OOP
GA
I
N
d
B
PHASE SHI
F
T
De
g
r
e
e
s
10
0
20
40
60
80
100
110
20
45
90
135
180
GAIN
PHASE
Figure 20. Open-Loop Gain and
Phase Shift vs. Frequency
OPEN-LOOP GAIN dB
60
40
20
0
20
40
60
80
100
120 140
100
120
140
160
150
130
110
TEMPERATURE C
V =
15V
V =
10V
RL = 2k
S
O
Figure 23. Open-Loop Gain vs.
Temperature
100
1k
10k
100k
FREQUENCY Hz
1M
10M
100
80
60
40
20
0
120
10
1
COMMON-MODE REJECTION dB
Figure 18. Common-Mode
Rejection vs. Frequency
SLEW RATE Volts/
s
60
40
20
0
20
40
60
80
100
120
140
1.0
2.0
3.0
4.0
3.0
2.0
1.0
GAIN-BANDWIDTH PRODUCT MHz
0
TEMPERATURE C
GAIN-BANDWIDTH
SLEW RATE
Figure 21. Gain-Bandwidth Product
and Slew Rate vs. Temperature
35
30
25
20
15
10
5
0
OUTPUT VOLTAGE Volts p-p
FREQUENCY Hz
1M
1k
10k
100k
Figure 24. Large Signal Frequency
Response
AD645
REV. B
6
1.0
SETTLING TIME s
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10
8
6
4
2
0
2
4
6
8
10
OUTPUT SWING FROM 0V TO VOLTS
0.1%
0.01%
0.01%
ERROR
0.1%
Figure 25. Output Swing and Error
vs. Settling Time
AD645
RL
2k
C
10pF
L
V
S
V
S
+
0.1F
0.1F
2
V
IN
V
OUT
4
3
7
6
Figure 28a. Unity-Gain Follower
AD645
RL
2k
C
10pF
L
V
S
V
S
+
0.1F
0.1F
2
4
3
V
IN
V
OUT
7
6
5k
5k
Figure 29a. Unity-Gain Inverter
100
SETTLING TIME s
50
90
80
70
60
40
30
20
10
0
CLOSED-LOOP VOLTAGE GAIN (V/V)
10
100
1k
1
FOR 10V STEP
0.1%
0.01%
Figure 26. Settling Time vs. Closed-
Loop Voltage Gain
Figure 28b. Unity-Gain Follower
Large Signal Pulse Response
Figure 29b. Unity-Gain Inverter
Large Signal Pulse Response
60
40
20
0
20
40
60
80
100
120
140
0
1
2
3
4
SUPPLY CURRENT mA
TEMPERATURE C
Figure 27. Supply Current vs.
Temperature
Figure 28c. Unity-Gain Follower
Small Signal Pulse Response
Figure 29c. Unity-Gain Inverter
Small Signal Pulse Response
AD645Typical Characteristics
AD645
7
REV. B
AD645
2
3
6
8
FILTERED
OUTPUT
OPTIONAL 26Hz
FILTER
PHOTODIODE
GUARD
OUTPUT
10pF
10
9
Figure 30. The AD645 Used as a Sensitive Preamplifier
Preamplifier Applications
The low input current and offset voltage levels of the AD645 to-
gether with its low voltage noise make this amplifier an excellent
choice for preamplifiers used in sensitive photodiode applica-
tions. In a typical preamp circuit, shown in Figure 30, the out-
put of the amplifier is equal to:
V
OUT
= I
D
(Rf) = Rp (P) Rf
where:
I
D
= photodiode signal current (Amps)
Rp = photodiode sensitivity (Amp/Watt)
Rf = the value of the feedback resistor, in ohms.
P = light power incident to photodiode surface, in watts.
An equivalent model for a photodiode and its dc error sources is
shown in Figure 31. The amplifier's input current, I
B
, will con-
tribute an output voltage error which will be proportional to the
value of the feedback resistor. The offset voltage error, V
OS
, will
cause a "dark" current error due to the photodiode's finite
shunt resistance, Rd. The resulting output voltage error, V
E
, is
equal to:
V
E
= (1 + Rf/Rd) V
OS
+ Rf I
B
A shunt resistance on the order of 10
9
ohms is typical for a
small photodiode. Resistance Rd is a junction resistance which
will typically drop by a factor of two for every 10
C rise in tem-
perature. In the AD645, both the offset voltage and drift are
low, this helps minimize these errors.
PHOTODIODE
OUTPUT
10pF
10
9
I
D
OS
V
I
B
Rd
50pF
Cd
Cf
Rf
Figure 31. A Photodiode Model Showing DC Error
Sources
Minimizing Noise Contributions
The noise level limits the resolution obtainable from any pream-
plifier. The total output voltage noise divided by the feedback
resistance of the op amp defines the minimum detectable signal
current. The minimum detectable current divided by the photo-
diode sensitivity is the minimum detectable light power.
Sources of noise in a typical preamp are shown in Figure 32.
The total noise contribution is defined as:
V OUT
=
in2
+
i f 2
+
is 2
Rf
1
+
s (Cf ) Rf
2
+
en2
1
+
Rf
Rd
1
+
s (Cd ) Rd
1
+
s (Cf ) Rf
2
Figure 33, a spectral density versus frequency plot of each
source's noise contribution, shows that the bandwidth of the
amplifier's input voltage noise contribution is much greater than
its signal bandwidth. In addition, capacitance at the summing
junction results in a "peaking" of noise gain in this configura-
tion. This effect can be substantial when large photodiodes with
large shunt capacitances are used. Capacitor Cf sets the signal
bandwidth and also limits the peak in the noise gain. Each
source's rms or root-sum-square contribution to noise is ob-
tained by integrating the sum of the squares of all the noise
sources and then by obtaining the square root of this sum. Mini-
mizing the total area under these curves will optimize the
preamplifier's overall noise performance.
PHOTODIODE
OUTPUT
10
9
50pF
i
S
i
S
Rd
Cd
10pF
Cf
Rf
i f
in
en
Figure 32. Noise Contributions of Various Sources
FREQUENCY Hz
100
1k
10k
100k
10
1
10nV
100nV
1
V
10
V
SIGNAL BANDWIDTH
NO FILTER
WITH FILTER
e n
is & if
in
en
OUTPUT VOLTAGE NOISE Volts/ Hz
Figure 33. Voltage Noise Spectral Density of the Circuit of
Figure 32 With and Without an Output Filter
An output filter with a passband close to that of the signal can
greatly improve the preamplifier's signal to noise ratio. The pho-
todiode preamplifier shown in Figure 32--without a bandpass
filter--has a total output noise of 50
V rms. Using a 26 Hz
single pole output filter, the total output noise drops to 23
V
rms, a factor of 2 improvement with no loss in signal bandwidth.
Using a "T" Network
A "T" network, shown in Figure 34, can be used to boost the ef-
fective transimpedance of an I to V converter, for a given feed-
back resistor value. Unfortunately, amplifier noise and offset
voltage contributions are also amplified by the "T" network
gain. A low noise, low offset voltage amplifier, such as the
AD645, is needed for this type of application.
AD645
REV. B
8
C1398a249/91
PRINTED IN U.S.A.
V = I R (1 )
PHOTODIODE
AD645
10pF
V
OUT
R
G
10
8
10k
OUT
+
D
f
Rf
1.1k
R
i
R
G
R
i
Figure 34. A Photodiode Preamp Employing a "T"
Network for Added Gain
A pH Probe Buffer Amplifier
A typical pH probe requires a buffer amplifier to isolate its 10
6
to 10
9
source resistance from external circuitry. Just such an
amplifier is shown in Figure 35. The low input current of the
AD645 allows the voltage error produced by the bias current
and electrode resistance to be minimal. The use of guarding,
shielding, high insulation resistance standoffs, and other such
standard methods used to minimize leakage are all needed to
maintain the accuracy of this circuit.
The slope of the pH probe transfer function, 50 mV per pH unit
at room temperature, has a +3300 ppm/
C temperature coeffi-
cient. The buffer of Figure 35 provides an output voltage equal
to 1 volt/pH unit. Temperature compensation is provided by
resistor RT which is a special temperature compensation resis-
tor, part number Q81, 1 k
, 1%, +3500 ppm/
C, available from
Tel Labs Inc.
GUARD
8
1
4
6
7
3
2
5
AD645
V
S
V ADJUST
100k
OS
pH
PROBE
V
+
S
OUTPUT
1VOLT/pH UNIT
19.6k
RT
1k
+3500ppm/
C
0.1
F
0.1
F
+15V
COM
15V
V
S
+V
S
Figure 35. A pH Probe Amplifier
Circuit Board Notes
The AD645 is designed for through hole mount into PC boards.
Maintaining picoampere level resolution in that environment
requires a lot of care. Since both the printed circuit board and
the amplifier's package have a finite resistance, the voltage dif-
ference between the amplifier's input pin and other pins (or
traces on the PC board) will cause parasitic currents to flow into
(or out of) the signal path. These currents can easily exceed the
1.5 pA input current level of the AD645 unless special precau-
tions are taken. Two successful methods for minimizing leakage
are: guarding the AD645's input lines and maintaining adequate
insulation resistance.
Guarding the input lines by completely surrounding them with a
metal conductor biased near the input lines' potential has two
major benefits. First, parasitic leakage from the signal line is
reduced, since the voltage between the input line and the guard
is very low. Second, stray capacitance at the input terminal is
minimized which in turn increases signal bandwidth. In the
header or can package, the case of the AD645 is connected to
Pin 8 so that it may be tied to the input potential (when operat-
ing as a follower) or tied to ground (when operating as an in-
verter). The AD645's positive input (Pin 3) is located next to
the negative supply voltage pin (Pin 4). The negative input (Pin
2) is next to the balance adjust pin (Pin 1) which is biased at a
potential close to that of the negative supply voltage. Note that
any guard traces should be placed on both sides of the board. In
addition, the input trace should be guarded along both of its
edges, along its entire length.
Contaminants such as solder flux, on the board's surface and on
the amplifier's package, can greatly reduce the insulation resis-
tance and also increase the sensitivity to atmospheric humidity.
Both the package and the board must be kept clean and dry. An
effective cleaning procedure is to: first, swab the surface with
high grade isopropyl alcohol, then rinse it with deionized water,
and finally, bake it at 80
C for 1 hour. Note that if either poly-
styrene or polypropylene capacitors are used on the printed cir-
cuit board that a baking temperature of 70
C is safer, since both
of these plastic compounds begin to melt at approximately
+85
C.
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
TO-99 Header (H) Package
45
BSC
0.100
(2.54)
BSC
0.034 (0.86)
0.027 (0.69)
0.045 (1.14)
0.027 (0.69)
0.160 (4.06)
0.110 (2.79)
0.100
(2.54)
BSC
0.200
(5.08)
BSC
6
8
5
7
1
4
2
3
REFERENCE PLANE
BASE & SEATING PLANE
0.335 (8.51)
0.305 (7.75)
0.370 (9.40)
0.335 (8.51)
0.750 (19.05)
0.500 (12.70)
0.045 (1.14)
0.010 (0.25)
0.050
(1.27)
MAX
0.040 (1.02) MAX
0.019 (0.48)
0.016 (0.41)
0.021 (0.53)
0.016 (0.41)
0.185 (4.70)
0.165 (4.19)
0.250 (6.35)
MIN
Plastic Mini-DIP (N) Package
PIN 1
0.280 (7.11)
0.240 (6.10)
4
5
8
1
SEATING
PLANE
0.060 (1.52)
0.015 (0.38)
0.130
(3.30)
MIN
0.210
(5.33)
MAX
0.160 (4.06)
0.115 (2.93)
0.430 (10.92)
0.348 (8.84)
0.022 (0.558)
0.014 (0.356)
0.070 (1.77)
0.045 (1.15)
0.100
(2.54)
BSC
0.325 (8.25)
0.300 (7.62)
0.015 (0.381)
0.008 (0.204)
0.195 (4.95)
0.115 (2.93)
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