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Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
AD6620
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
Analog Devices, Inc., 1998
65 MSPS Digital Receive
Signal Processor
FUNCTIONAL BLOCK DIAGRAM
REAL,
DUAL REAL,
OR COMPLEX
INPUTS
SERIAL OR
PARALLEL
OUTPUTS
CIC
FILTERS
OUTPUT
FORMAT
COMPLEX
NCO
P
OR SERIAL
CONTROL
I
Q
SIN
COS
FIR
FILTER
EXTERNAL
SYNC
CIRCUITRY
JTAG
PORT
I
I
Q
Q
FEATURES
High Input Sample Rate
65 MSPS Single Channel Real
32.5 MSPS Diversity Channel Real
32.5 MSPS Single Channel Complex
NCO Frequency Translation
Worst Spur Better than 100 dBc
Tuning Resolution Better than 0.02 Hz
2nd Order Cascaded Integrator Comb FIR Filter
Linear Phase, Fixed Coefficients
Programmable Decimation Rates: 2, 3 . . . 16
5th Order Cascaded Integrator Comb FIR Filter
Linear Phase, Fixed Coefficients
Programmable Decimation Rates: 1, 2, 3 . . . 32
Programmable Decimating RAM Coefficient FIR Filter
Up to 130 Million Taps per Second
256 20-Bit Programmable Coefficients
Programmable Decimation Rates: 1, 2, 3 . . . 32
Bidirectional Synchronization Circuitry
Phase Aligns NCOs
Synchronizes Data Output Clocks
Serial or Parallel Baseband Outputs
Pin Selectable Serial or Parallel
Serial Works with SHARC, ADSP-21xx, Most Other
DSPs
16-Bit Parallel Port, Interleaved I and Q Outputs
Two Separate Control and Configuration Ports
Generic P Port, Serial Port
3.3 V Optimized CMOS Process
JTAG Boundary Scan
GENERAL DESCRIPTION
The AD6620 is a digital receiver with four cascaded signal-
processing elements: a frequency translator, two fixed-
coefficient decimating filters, and a programmable coefficient
decimating filter. All inputs are 3.3 V LVCMOS compatible.
All outputs are LVCMOS and 5 V TTL compatible.
As ADCs achieve higher sampling rates and dynamic range, it
becomes increasingly attractive to accomplish the final IF stage
of a receiver in the digital domain. Digital IF Processing is less
expensive, easier to manufacture, more accurate, and more
flexible than a comparable highly selective analog stage.
The AD6620 diversity channel decimating receiver is designed
to bridge the gap between high speed ADCs and general pur-
pose DSPs. The high resolution NCO allows a single carrier to
be selected from a high speed data stream. High dynamic range
decimation filters with a wide range of decimation rates allow
both narrowband and wideband carriers to be extracted. The
RAM-based architecture allows easy reconfiguration for multi-
mode applications.
The decimating filters remove unwanted signals and noise from
the channel of interest. When the channel of interest occupies
less bandwidth than the input signal, this rejection of out-of-
band noise is called "processing gain." By using large decima-
tion factors, this "processing gain" can improve the SNR of the
ADC by 36 dB or more. In addition, the programmable RAM
Coefficient filter allows antialiasing, matched filtering, and
static equalization functions to be combined in a single, cost-
effective filter.
The input port accepts a 16-bit Mantissa, a 3-bit Exponent,
and an A/B Select pin. These allow direct interfacing with the
AD6600, AD6640, AD9042 and most other high speed ADCs.
Three input modes are provided: Single Channel Real, Single
Channel Complex, and Diversity Channel Real.
When paired with an interleaved sampler such as the AD6600,
the AD6620 can process two data streams in the Diversity
Channel Real input mode. Each channel is processed with co-
herent frequency translation and output sample clocks. In addi-
tion, external synchronization pins are provided to facilitate
coherent frequency translation and output sample clocks among
several AD6620s. These features can ease the design of systems
with diversity antennas or antenna arrays.
Units are packaged in an 80-lead PQFP (plastic quad flatpack)
and specified to operate over the industrial temperature range
(40
C to +85
C).
AD6620
2
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I-RAM
256 20
C-RAM
256 20
Q-RAM
256 20
M
RCF
RCF
M
CICS
CIC5
SCALING
INTERLEAVE
DE-
INTERLEAVE
MULTI-
PLEXER
M
CICS
CIC2
SCALING
MULTI-
PLEXER
EXP
SCALING
FREQUENCY
TRANSLATOR
3
18
18
I
Q
16
INPUT
DATA
3
EXP[2:0]
16
IN[15:0]
COMPLEX
NCO
f
SAMP5
EXPLNV,
EXPOFF
TIMING
SYNC
I/O
CLK
A/B
RESET
SYNC RCF
SYNC CIC
SYNC NCO
PHASE
OFFSET
f
SAMP2
f
SAMP
MULTIPLEXER
SCALING, S
OUT
SERIAL
PARALLEL
16
23
23
DV
OUT
I/Q
OUT
A/B
OUT
PARALLEL
OUTPUTS
AND
SERIAL I/O
16
OUT[15:0]
SCLK
SDI
SDO
SDFS
SDFE
SBM
WL[1:0]
AD
SDIV[3:0]
RCF COEFFICIENTS
NUMBER OF TAPS
DECIMATE FACTOR
ADDRESS OFFSET
CIC2, CIC5
DECIMATE FACTORS
SCALE FACTORS
NCO FREQUENCY
PHASE OFFSET
DITHER
SYNC MASK
INPUT MODE
REAL, DUAL, COMPLEX
FIXED OR WITH EXPONENT
SYNC M/S
OUTPUT
SCALE
FACTOR
JTAG
TRST
TCK
TMS
TDI
TDO
MICROPROCESSOR INTERFACE
DS
D[7:0] A[2:0]
R/W
DTACK
CS
MODE PAR/SER
CONTROL REGISTERS
MICROPORT AND
SERIAL ACCESS
(
W/R
)
(RDY)
(
R/D
)
OUTPUT
Figure 1. Block Diagram
TABLE OF CONTENTS
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 1
ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
SPECIFICATIONS/TIMING . . . . . . . . . . . . . . . . . . . . . . . 4
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . 11
EXPLANATION OF TEST LEVELS . . . . . . . . . . . . . . . . 11
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . 12
PIN CONFIGURATIONS . . . . . . . . . . . . . . . . . . . . . . . . . 13
INPUT DATA PORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
OUTPUT DATA PORT . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
FREQUENCY TRANSLATOR . . . . . . . . . . . . . . . . . . . . . 20
2ND ORDER CASCADED INTEGRATOR
COMB FILTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5TH ORDER CASCADED INTEGRATOR
COMB FILTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
RAM COEFFICIENT FILTER . . . . . . . . . . . . . . . . . . . . . 25
CONTROL REGISTERS AND ON-CHIP RAM . . . . . . . 27
PROGRAMMING THE AD6620 . . . . . . . . . . . . . . . . . . . 29
MICROPORT CONTROL . . . . . . . . . . . . . . . . . . . . . . . . 31
SERIAL PORT CONTROL . . . . . . . . . . . . . . . . . . . . . . . . 34
JTAG BOUNDARY SCAN . . . . . . . . . . . . . . . . . . . . . . . . 36
APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . 43
ARCHITECTURE
As shown in Figure 1, the AD6620 has four main signal pro-
cessing stages: a Frequency Translator, two Cascaded Integrator
Comb FIR Filters (CIC2, CIC5), and a RAM Coefficient FIR
Filter (RCF). Multiple modes are supported for clocking data
into and out of the chip. Programming and control is accom-
plished via serial and microprocessor interfaces.
Input data to the chip may be real or complex. If the input data
is real, it may be clocked in as a single channel or interleaved
with a second channel. The two-channel input mode, called
Diversity Channel Real, is typically used in diversity receiver
applications. Input data is clocked in 16-bit parallel words,
IN[15:0]. This word may be combined with exponent input bits
EXP[2:0] when the AD6620 is being driven by floating-point or
gain-ranging analog-to-digital converters such as the AD6600.
Frequency translation is accomplished with a 32-bit complex
Numerically Controlled Oscillator (NCO). Real data entering
this stage is separated into in-phase (I) and quadrature (Q)
components. This stage translates the input signal from a digital
intermediate frequency (IF) to baseband. Phase and amplitude
dither may be enabled on-chip to improve spurious performance
of the NCO. A phase offset word is available to create a known
phase relationship between multiple AD6620s.
Following frequency translation is a fixed coefficient, high speed
decimating filter that reduces the sample rate by a program-
mable ratio between 2 and 16. This is a second order, cascaded
integrator comb FIR filter shown as CIC2 in Figure 1. (Note:
Decimation of 1 in CIC2 requires 2
or greater clock into
AD6620). The data rate into this stage equals the input data
rate, f
SAMP
. The data rate out of CIC2, f
SAMP2
, is determined by
the decimation factor, M
CIC2
.
AD6620
3
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Following CIC2 is the second fixed-coefficient decimating filter.
This filter, CIC5, further reduces the sample rate by a program-
mable ratio from 1 to 32. The data rate out of CIC5, f
SAMP5
, is
determined by the decimation factors of M
CIC5
and M
CIC2
.
Each CIC stage is a FIR filter whose response is defined by the
decimation rate. The purpose of these filters is to reduce the
data rate of the incoming signal so that the final filter stage, a
FIR RAM coefficient sum-of-products filter (RCF), can calcu-
late more taps per output. As shown in Figure 1, on-chip multi-
plexers allow both CIC filters to be bypassed if a multirate clock
is used.
The fourth stage is a sum-of-products FIR filter with program-
mable 20-bit coefficients, and decimation rates programmable
from 1 to 32. The RAM Coefficient FIR Filter (RCF in Figure
1) can handle a maximum of 256 taps.
The overall filter response for the AD6620 is the composite of
all three cascaded decimating filters: CIC2, CIC5, and RCF.
Each successive filter stage is capable of narrower transition
bandwidths but requires a greater number of CLK cycles to
calculate the output. More decimation in the first filter stage will
minimize overall power consumption. Data comes out via a
parallel port or a serial interface.
Figure 2 illustrates the basic function of the AD6620: to select
and filter a single channel from a wide input spectrum. The
frequency translator "tunes" the desired carrier to baseband.
CIC2 and CIC5 have fixed order responses; the RCF filter
provides the sharp transitions. More detail is provided in later
sections of the data sheet.
f
S
/2
3f
S
/8
5f
S
/16
f
S
/4
3f
S
/16
f
S
/8
f
S
/16
DC
f
S
/16
f
S
/8
3f
S
/16
f
S
/4
5f
S
/16
f
S
/2
3f
S
/8
SIGNAL OF
INTEREST
SIGNAL OF INTEREST "IMAGE"
WIDEBAND INPUT SPECTRUM
(f
samp/
2 TO f
samp/
2)
D'
C'
B'
A'
A
C
B
D
Figure 2a. Wideband Input Spectrum (e.g., 30 MHz from High Speed ADC)
f
S
/2
3f
S
/8
5f
S
/16
f
S
/4
3f
S
/16
f
S
/8
f
S
/16
DC
f
S
/16
f
S
/8
3f
S
/16
f
S
/4
5f
S
/16
f
S
/2
3f
S
/8
AFTER FREQUENCY TRANSLATION
NCO "TUNES" SIGNAL TO BASEBAND
A
B
C
D
D'
C'
B'
A'
Figure 2b. Frequency Translation (e.g. Single 1 MHz Channel Tuned to Baseband)
0
10
20
30
40
50
60
70
80
90
100
110
120
130
CIC2, CIC5, AND RCF
dBc
FREQUENCY
Figure 2c. Baseband Signal is Decimated and Filtered by CIC2, CIC5, RCF
4
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AD6620SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
Test
AD6620AS
Parameter
Level
Min
Typ
Max
Units
VDD
I
3.0
3.3
3.6
V
T
AMBIENT
IV
40
+25
+85
C
ELECTRICAL CHARACTERISTICS
Test
AD6620AS
Parameter (Conditions)
Temp
Level
Min
Typ
Max
Units
LOGIC INPUTS
1, 2, 3, 4, 5, 6, 7
(NOT 5 V TOLERANT)
Logic Compatibility
Full
3.3 V CMOS
Logic "1" Voltage
Full
I
2.0
VDD + 0.3
V
Logic "0" Voltage
Full
I
0.3
0.8
V
Logic "1" Current
Full
I
1
10
A
Logic "0" Current
Full
I
1
10
A
Input Capacitance
+25
C
V
4
pF
LOGIC OUTPUTS
2, 4, 7, 8, 9, 10, 11
Logic Compatibility
Full
3.3 V CMOS/TTL
Logic "1" Voltage (I
OH
= 0.5 mA)
Full
I
2.4
VDD 0.2
V
Logic "0" Voltage (I
OL
= 1.0 mA)
Full
I
0.2
0.4
V
IDD SUPPLY CURRENT
CLK = 20 MHz
12
Full
V
52
mA
CLK = 65 MHz
13
Full
I
167
227
mA
Reset Mode
14
Full
I
1
mA
POWER DISSIPATION
CLK = 20 MHz
12
Full
V
170
mW
CLK = 65 MHz
13
Full
I
550
750
mW
Reset Mode
14
Full
I
3.3
mW
NOTES
1
Input-Only Pins: CLK,
RESET, IN[15:0], EXP[2:0], A/B, PAR/SEL.
2
Bidirectional Pins: SYNC_NCO, SYNC_CIC, SYNC_RCF.
3
Microinterface Input Pins:
DS (RD), R/W (WR), CS.
4
Microinterface Bidirectional Pins: A[2:0], D[7:0].
5
JTAG Input Pins:
TRST, TCK, TMS, TDI.
6
Serial Mode Input Pins: SDI, SBM, WL[1:0], AD, SDIV[3:0].
7
Serial Mode Bidirectional Pins: SCLK, SDFS.
8
Output Pins: OUT[15:0], DV
OUT
, A/B
OUT
, I/Q
OUT
.
9
Microinterface Output Pins:
DTACK (RDY).
10
JTAG Output Pins: TDO.
11
Serial Mode Output Pins: SDO, SDFE.
12
Conditions for IDD @ 20 MHz. M
CIC2
= 2, M
CIC5
= 2, M
RCF
= 1, 4 RCF taps of alternating positive and negative full scale.
13
Conditions for IDD @ 65 MHz. M
CIC2
= 2, M
CIC5
= 2, M
RCF
= 1, 4 RCF taps of alternating positive and negative full scale.
14
Conditions for IDD in Reset (
RESET = 0).
Specifications subject to change without notice.
AD6620
5
REV. 0
TIMING CHARACTERISTICS
(C
LOAD
= 40 pF All Outputs)
Test
AD6620AS
Parameter (Conditions)
Temp
Level
Min
Typ
Max
Units
CLK Timing Requirements:
t
CLK
CLK Period
Full
I
15.4
ns
t
CLKL
CLK Width Low
Full
IV
7.0
0.5
t
CLK
ns
t
CLKH
CLK Width High
Full
IV
7.0
0.5
t
CLK
ns
Reset Timing Requirements:
t
RESL
RESET Width Low
Full
I
30.0
ns
Input Data Timing Requirements:
t
SI
Input
1
to CLK Setup Time
Full
IV
1.0
ns
t
HI
Input
1
to CLK Hold Time
Full
IV
6.5
ns
Parallel Output Switching Characteristics:
t
DPR
CLK to OUT[15:0] Rise Delay
Full
IV
8.0
19.5
ns
t
DPF
CLK to OUT[15:0] Fall Delay
Full
IV
7.5
19.5
ns
t
DPR
CLK to DV
OUT
Rise Delay
Full
IV
6.5
19.0
ns
t
DPF
CLK to DV
OUT
Fall Delay
Full
IV
5.5
11.5
ns
t
DPR
CLK to I
QOUT
Rise Delay
Full
IV
7.0
19.5
ns
t
DPF
CLK to I
QOUT
Fall Delay
Full
IV
6.0
13.5
ns
t
DPR
CLK to A
BOUT
Rise Delay
Full
IV
7.0
19.5
ns
t
DPF
CLK to A
BOUT
Fall Delay
Full
IV
5.5
13.5
ns
SYNC Timing Requirements:
t
SY
SYNC
2
to CLK Setup Time
Full
IV
1.0
ns
t
HY
SYNC
2
to CLK Hold Time
Full
IV
6.5
ns
SYNC Switching Characteristics:
t
DY
CLK to SYNC
3
Delay Time
Full
V
7.0
23.5
ns
Serial Input Timing:
t
SSI
SDI to SCLK
t Setup Time
Full
IV
1.0
ns
t
HSI
SDI to SCLK
t Hold Time
Full
IV
2.0
ns
t
HSRF
SDFS to SCLK
u Hold Time
Full
IV
4.0
ns
t
SSF
SDFS to SCLK
t Setup Time
4
Full
IV
1.0
ns
t
HSF
SDFS to SCLK
t Hold Time
4
Full
IV
2.0
ns
Serial Frame Output Timing:
t
DSE
SCLK
u to SDFE Delay Time
Full
IV
3.5
11.0
ns
t
SDFEH
SDFE Width High
Full
V
t
SCLK
ns
t
DSO
SCLK
u to SDO Delay Time
Full
IV
4.5
11.0
ns
SCLK Switching Characteristics, SBM = "1":
t
SCLK
SCLK Period
3
Full
I
2
t
CLK
ns
t
SCLKL
SCLK Width Low
Full
V
0.5
t
SCLK
ns
t
SCLKH
SCLK Width High
Full
V
0.5
t
SCLK
ns
t
SCLKD
CLK to SCLK Delay Time
Full
V
6.5
13.0
ns
Serial Frame Timing, SBM = "1":
t
DSF
SCLK
u to SDFS Delay Time
Full
IV
1.0
4.0
ns
t
SDFSH
SDFS Width High
Full
V
t
SCLK
ns
SCLK Timing Requirements, SBM = "0":
t
SCLK
SCLK Period
Full
I
15.4
ns
t
SCLKL
SCLK Width Low
Full
IV
0.4
t
SCLK
0.5
t
SCLK
ns
t
SCLKH
SCLK Width High
Full
IV
0.4
t
SCLK
0.5
t
SCLK
ns
NOTES
1
Specification pertains to: IN[15:0], EXP[2:0], A/B.
2
Specification pertains to: SYNC_NCO, SYNC_CIC, SYNC_RCF.
3
SCLK period will be
2
t
CLK
when AD6620 is Serial Bus Master (SBM = 1) depending on the SDIV word.
4
SDFS setup and hold time must be met, even when configured as outputs, since internally the signal is sampled at the pad.
Specifications subject to change without notice.
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