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Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

AD6644

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700

World Wide Web Site: http://www.analog.com

Fax: 781/326-8703

© Analog Devices, Inc., 2000

14-Bit, 40 MSPS/65 MSPS

A/D Converter

FUNCTIONAL BLOCK DIAGRAM

ADC2

DAC2

TH4

TH3

TH5

ADC3

ADC1

DAC1

TH2

TH1

DIGITAL

ERROR

CORRECTION

LOGIC

2.4V

INTERNAL

TIMING

AIN

REF

ENCODE

GND

D10

D11

D12

D13

DRY

OVR

DMID

MSB

LSB

AD6644

FEATURES
65 MSPS Guaranteed Sample Rate
40 MSPS Version Available
Sampling Jitter < 300 fs
100 dB Multitone SFDR
1.3 W Power Dissipation
Differential Analog Inputs
Digital Outputs

Two's Complement Format
3.3 V CMOS-Compatible
Data Ready for Output Latching

APPLICATIONS
Multichannel, Multimode Receivers
AMPS, IS-136, CDMA, GSM, Third Generation
Single Channel Digital Receivers
Antenna Array Processing
Communications Instrumentation
Radar, Infrared Imaging
Instrumentation

PRODUCT DESCRIPTION

The AD6644 is a high-speed, high-performance, monolithic
14-bit analog-to-digital converter. All necessary functions,
including track-and-hold (T/H) and reference, are included on-
chip to provide a complete conversion solution. The AD6644
provides CMOS-compatible digital outputs. It is the third genera-
tion in a wideband ADC family, preceded by the AD9042 (12-bit
41 MSPS) and the AD6640 (12-bit 65 MSPS, IF sampling.)

Designed for multichannel, multimode receivers, the AD6644 is
part of ADI's new SoftCellTM transceiver chipset. The AD6644
achieves 100 dB multitone, spurious-free dynamic range (SFDR)
through the Nyquist band. This breakthrough performance eases
the burden placed on multimode digital receivers (software radios)
which are typically limited by the ADC. Noise performance is
exceptional; typical signal-to-noise ratio is 74 dB.

The AD6644 is also useful in single channel digital receivers
designed for use in wide-channel bandwidth systems (CDMA,
W-CDMA). With oversampling, harmonics can be placed out-
side the analysis bandwidth. Oversampling also facilitates the use of
decimation receivers (such as the AD6620), allowing the noise
floor in the analysis bandwidth to be reduced. By replacing tradi-
tional analog filters with predictable digital components, modern
receivers can be built using fewer "RF" components, resulting
in decreased manufacturing costs, higher manufacturing yields,
and improved reliability.

The AD6644 is built on Analog Devices' high-speed complemen-
tary bipolar process (XFCB) and uses an innovative, multipass
circuit architecture. Units are packaged in a 52-terminal Low-
Profile Quad Plastic Flatpack (LQFP) specified from 25

°C

to +85

°C.

PRODUCT HIGHLIGHTS

1. Guaranteed sample rate is 65 MSPS.

2. Fully differential analog input stage.

3. Digital outputs may be run on 3.3 V supply for easy interface

to digital ASICs.

4. Complete Solution: reference and track-and-hold.

5. Packaged in small, surface-mount, plastic, 52-terminal LQFP.

SoftCell is a trademark of Analog Devices, Inc.

REV. 0

AD6644SPECIFICATIONS

DC SPECIFICATIONS

Test

AD6644AST-40

AD6644AST-65

Parameter

Temp

Level

Min

Typ

Max

Min

Typ

Max

Unit

RESOLUTION

Bits

ACCURACY

No Missing Codes

Full

Guaranteed

Offset Error

Full

+10

Gain Error

Full

+10

% FS

Differential Nonlinearity (DNL)

Full

1.0

±0.25

+1.5

1.0

±0.25

+1.5

LSB

Integral Nonlinearity (INL)

Full

±0.50

LSB

TEMPERATURE DRIFT

Offset Error

Full

ppm/

°C

Gain Error

Full

ppm/

°C

POWER SUPPLY REJECTION (PSRR)

Full

±1.0

mV/V

REFERENCE OUT (V

REF

)

Full

2.4

ANALOG INPUTS (AIN, AIN)

Differential Input Voltage Range

Full

2.2

V p-p

Differential Input Resistance

Full

Differential Input Capacitance

°C

1.5

POWER SUPPLY

Supply Voltage

Full

4.85

5.0

5.25

4.85

5.0

5.25

Full

3.0

3.3

3.6

3.0

3.3

3.6

Supply Current

VCC

(AV

= 5.0 V)

Full

245

276

245

276

VCC

(DV

= 3.3 V)

Full

POWER CONSUMPTION

Full

1.3

1.5

1.3

1.5

NOTES

may be varied from 4.85 V to 5.25 V. However, rated ac (harmonics) performance is valid only over the range AV

= 5.0 V to 5.25 V.

Specifications subject to change without notice.

DIGITAL SPECIFICATIONS

Test

AD6644AST-40

AD6644AST-65

Parameter

Temp

Level

Min

Typ

Max

Min

Typ

Max

Unit

ENCODE INPUTS (ENC, ENC)

Differential Input Voltage

Full

0.4

V p-p

Differential Input Resistance

°C

Differential Input Capacitance

°C

2.5

LOGIC OUTPUTS (D13D0, DRY, OVR)

Logic Compatibility

CMOS

Logic "1" Voltage

Full

2.5

Logic "0" Voltage

Full

0.4

Output Coding

Two's Complement

DMID

Full

NOTES

All ac specifications tested by driving ENCODE and ENCODE differentially. Reference Figure 22 for performance versus encode power.

Digital output logic levels: DV

= 3.3 V, C

LOAD

= 10 pF. Capacitive loads >10 pF will degrade performance.

Specifications subject to change without notice.

SWITCHING SPECIFICATIONS

Test

AD6644AST-40

AD6644AST-65

Parameter

Temp

Level

Min

Typ

Max

Min

Typ

Max

Unit

Maximum Conversion Rate

Full

MSPS

Minimum Conversion Rate

Full

MSPS

ENCODE Pulsewidth High

Full

6.5

ENCODE Pulsewidth Low

Full

6.5

Specifications subject to change without notice.

(AV

= 5 V, DV

= 3.3 V; T

MIN

= 25 C, T

MAX

= +85 C)

(AV

= 5 V, DV

= 3.3 V; T

MIN

= 25 C, T

MAX

= +85 C)

(AV

= 5 V, DV

= 3.3 V; ENCODE and ENCODE = Maximum Conversion Rate MSPS; T

MIN

25 C, T

MAX

= +85 C)

REV. 0

AD6644

AC SPECIFICATIONS

Test

AD6644AST-40

AD6644AST-65

Parameter

Temp

Level

Min

Typ

Max

Min

Typ

Max

Unit

SNR

Analog Input

2.2 MHz

°C

74.5

@ 1 dBFS

15.5 MHz

°C

74.0

30.5 MHz

°C

73.5

SINAD

Analog Input

2.2 MHz

°C

74.5

@ 1 dBFS

15.5 MHz

°C

74.0

30.5 MHz

°C

73.0

WORST HARMONIC

or 3

)

Analog Input

2.2 MHz

°C

dBc

@ 1 dBFS

15.5 MHz

°C

dBc

30.5 MHz

°C

dBc

WORST HARMONIC (4

or Higher)

Analog Input

2.2 MHz

°C

dBc

@ 1 dBFS

15.5 MHz

°C

dBc

30.5 MHz

°C

dBc

TWO-TONE SFDR

3, 4

Full

100

dBFS

TWO-TONE IMD REJECTION

2, 4

F1, F2 @ 7 dBFS

Full

dBc

ANALOG INPUT BANDWIDTH

°C

250

MHz

NOTES

All ac specifications tested by driving ENCODE and ENCODE differentially.

= 5 V to 5.25 V for rated ac performance.

Analog input signal power swept from 7 dBFS to 100 dBFS.

F1 = 15 MHz, F2 = 15.5 MHz.

Specifications subject to change without notice.

SWITCHING SPECIFICATIONS

Test

AD6644AST-40/65

Parameter

Name

Temp

Level

Min

Typ

Max

Unit

ENCODE INPUT PARAMETERS

Encode Period

@ 65 MSPS

ENC

Full

15.4

Encode Period

@ 40 MSPS

ENC

Full

Encode Pulsewidth High

@ 65 MSPS

ENCH

Full

6.2

7.7

9.2

Encode Pulsewidth Low @ 65 MSPS

ENCL

Full

6.2

7.7

9.2

ENCODE/DATA READY

Encode Rising to Data Ready Falling

Full

2.6

3.4

4.6

Encode Rising to Data Ready Rising

E_DR

ENCH

+ t

@ 65 MSPS (50% Duty Cycle)

Full

10.3

11.1

12.3

@ 40 MSPS (50% Duty Cycle)

Full

15.1

15.9

17.1

ENCODE/DATA (D13:0), OVR

ENC to DATA Falling Low

E_FL

Full

3.8

5.5

9.2

ENC to DATA Rising Low

E_RL

Full

3.0

4.3

6.4

ENCODE to DATA Delay (Hold Time)

H_E

Full

3.0

4.3

6.4

ENCODE to DATA Delay (Setup Time)

S_E

ENC

E_FL

Encode = 65 MSPS (50% Duty Cycle)

Full

6.2

9.8

11.6

Encode = 40 MSPS (50% Duty Cycle)

Full

15.9

19.4

21.2

(AV

= 5 V, DV

= 3.3 V; ENCODE and ENCODE = Maximum Conversion Rate MSPS; T

MIN

= 25 C, T

MAX

= +85 C)

(AV

= 5 V, DV

= 3.3 V; ENCODE and ENCODE = Maximum Conversion Rate MSPS; T

MIN

25 C, T

MAX

= +85 C, C

LOAD

= 10 pF)

REV. 0

AD6644SPECIFICATIONS

ENC,

ENC

D[13:0], OVR

DRY

N1

H_DR

S_DR

N2

N3

S_E

H_E

E_DR

E_FL

E_RL

ENC

ENCH

ENCL

N 1

N 2

N 3

N 4

AIN

N 1

N 2

N 3

N 4

Figure 1. Timing Diagram

Test

AD6644AST-40/65

Parameter

Name

Temp

Level

Min

Typ

Max

Unit

DATA READY (DRY

)/DATA, OVR

Data Ready to DATA Delay (Hold Time)

H_DR

Note 6

Encode = 65 MSPS (50% Duty Cycle)

Full

8.0

8.6

9.4

Encode = 40 MSPS (50% Duty Cycle)

Full

12.8

13.4

14.2

Data Ready to DATA Delay (Setup Time)

S_DR

Note 6

@ 65 MSPS (50% Duty Cycle)

Full

3.2

5.5

6.5

@ 40 MSPS (50% Duty Cycle)

Full

8.0

10.3

11.3

APERTURE DELAY

°C

100

APERTURE UNCERTAINTY (JITTER)

°C

0.2

ps rms

NOTES

Several timing parameters are a function of t

ENC

and t

ENCH

To compensate for a change in duty cycle for t

H_DR

and t

S_DR

use the following equation:

Newt

H_DR

= (t

H_DR

% Change(t

ENCH

))

× t

ENC

Newt

S_DR

= (t

S_DR

% Change(t

ENCH

))

× t

ENC

/2.

ENCODE to DATA Delay (Hold Time) is the absolute minimum propagation delay through the analog-to-digital converter.

ENCODE to DATA Delay (Setup Time) is calculated relative to 65 MSPS (50% duty cycle). In order to calculate t

S_E

for a given encode use the following equation:

Newt

S_E

= t

ENC(NEW)

ENC

+ t

S_E

(i.e., for 40 MSPS: Newt

S_E(TYP)

= 25

× 10

15.38

× 10

+ 9.8

× 10

= 19.4

× 10

DRY is an inverted and delayed version of the encode clock. Any change in the duty cycle of the clock will correspondingly change the duty cycle of DRY.

Data Ready to DATA Delay(t

H_DR

and t

S_DR

) is calculated relative to 65 MSPS (50% duty cycle) and is dependent on t

ENC

and duty cycle. In order to calculate t

H_DR

and t

S_DR

for a given encode use the following equations:

Newt

H_DR

= t

ENC(NEW)

/2 t

ENCH

+ t

H_DR

(i.e., for 40 MSPS: Newt

H_DR(TYP)

= 12.5

× 10

7.69

× 10

+ 8.6

× 10

= 13.4

× 10

Newt

S_DR

= t

ENC(NEW)

/2 t

ENCH

+ t

S_DR

(i.e., for 40 MSPS: Newt

S_DR(TYP)

= 12.5

× 10

7.69

× 10

+ 5.5

× 10

= 10.3

× 10

Specifications subject to change without notice.

AD6644

REV. 0

ABSOLUTE MAXIMUM RATINGS

Parameter

Min

Max

Unit

ELECTRICAL

Voltage

Analog Input Voltage

Analog Input Current

Digital Input Voltage

Digital Output Current

ENVIRONMENTAL

Operating Temperature Range

(Ambient)

+85

°C

Maximum Junction Temperature

150

°C

Lead Temperature (Soldering, 10 sec)

300

°C

Storage Temperature Range (Ambient)

+150

°C

NOTES

Absolute maximum ratings are limiting values to be applied individually, and

beyond which the serviceability of the circuit may be impaired. Functional
operability is not necessarily implied. Exposure to absolute maximum rating
conditions for an extended period of time may affect device reliability.

Typical thermal impedances (52-terminal LQFP);

= 33

°C/W;

= 11

°C/W.

These measurements were taken on a 6 layer board in still air with a solid ground

plane.

EXPLANATION OF TEST LEVELS
Test Level

100% production tested.

100% production tested at 25

°C, and guaranteed by

design and characterization at temperature extremes.

III Sample tested only.
IV Parameter is guaranteed by design and characterization

testing.

Parameter is a typical value only.

ORDERING GUIDE

Model

Temperature Range

Package Description

Package Option

AD6644AST-40

°C to +85°C (Ambient)

52-Terminal LQFP (Low-Profile Quad Plastic Flatpack)

ST-52

AD6644AST-65

°C to +85°C (Ambient)

52-Terminal LQFP (Low-Profile Quad Plastic Flatpack)

ST-52

AD6644ST/PCB

Evaluation Board with AD6644AST65

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD6644 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recom-
mended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

AD6644

REV. 0

PIN FUNCTION DESCRIPTIONS

Pin No.

Name

Function

1, 33, 43

3.3 V Power Supply (Digital) Output Stage Only.

2, 4, 7, 10, 13, 15, 17, 19, 21, 23,

GND

Ground.

25, 27, 29, 34, 42

REF

2.4 V (Analog Reference). Bypass to ground with 0.1

µF microwave

chip capacitor.

ENCODE

Encode Input; conversion initiated on rising edge.

ENCODE

Complement of ENCODE; differential input.

8, 9, 14, 16, 18, 22, 26, 28, 30

5 V Analog Power Supply.

AIN

Analog Input.

AIN

Complement of AIN; Differential Analog Input.

Internal Voltage Reference; bypass to ground with 0.1

µF microwave

chip capacitor.

Internal Voltage Reference; bypass to ground with 0.1

µF microwave

chip capacitor.

DNC

Do not connect this pin.

OVR

Overrange Bit; high indicates analog input exceeds

±FS.

DMID

Output Data Voltage Midpoint; approximately equal to (DVCC)/2.

D0 (LSB)

Digital Output Bit (Least Significant Bit); Two's Complement

3741, 4450

D1D5, D6D12

Digital Output Bits in Two's Complement.

D13 (MSB)

Digital Output Bit (Most Significant Bit); Two's Complement.

DRY

Data Ready Output.

PIN CONFIGURATION

14 15 16 17 18 19 20 21 22 23 24 25 26

PIN 1
IDENTIFIER

TOP VIEW

(Not to Scale)

DNC = DO NOT CONNECT

DRY

D13 (MSB)

D12

D11

D10

GND

REF

GND

ENCODE

GND

AIN
AIN

GND

D3
D2

D0 (LSB)

DMID

GND

OVR

DNC

GND

AD6644

REV. 0

DEFINITIONS OF SPECIFICATIONS
Analog Bandwidth

The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.

Aperture Delay

The delay between the 50% point of the rising edge of the
ENCODE command and the instant at which the analog input
is sampled.

Aperture Uncertainty (Jitter)

The sample-to-sample variation in aperture delay.

Differential Analog Input Resistance, Differential Analog Input
Capacitance, and Differential Analog Input Impedance

The real and complex impedances measured at each analog
input port. The resistance is measured statically and the capaci-
tance and differential input impedances are measured with a
network analyzer.

Differential Analog Input Voltage Range

The peak-to-peak differential voltage that must be applied to the
converter to generate a full-scale response. Peak differential voltage
is computed by observing the voltage on a single pin and sub-
tracting the voltage from the other pin, which is 180 degrees out
of phase. Peak-to-peak differential is computed by rotating the
inputs phase 180 degrees and taking the peak measurement again.
The difference is then computed between both peak measurements.

Differential Nonlinearity

The deviation of any code width from an ideal 1 LSB step.

Encode Pulsewidth/Duty Cycle

Pulsewidth high is the minimum amount of time that the
ENCODE pulse should be left in Logic 1 state to achieve rated
performance; pulsewidth low is the minimum time ENCODE
pulse should be left in low state. See timing implications of
changing t

ENCH

in text. At a given clock rate, these specs define

an acceptable ENCODE duty cycle.

Full-Scale Input Power

Expressed in dBm. Computed using the following equation:

Power

Full Scale

Full Scale rms

Input

0 001

log

| |

Harmonic Distortion, 2nd

The ratio of the rms signal amplitude to the rms value of the
second harmonic component, reported in dBc.

Harmonic Distortion, 3rd

The ratio of the rms signal amplitude to the rms value of the
third harmonic component, reported in dBc.

Integral Nonlinearity

The deviation of the transfer function from a reference line
measured in fractions of 1 LSB using a "best straight line"
determined by a least-square curve fit.

Minimum Conversion Rate

The encode rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaranteed limit.

Maximum Conversion Rate

The encode rate at which parametric testing is performed.

Output Propagation Delay

The delay between a differential crossing of ENCODE and
ENCODE and the time when all output data bits are within
valid logic levels.

Noise (For Any Range Within the ADC)

NOISE

Signal

dBm

dBFS

| |

0 001 10

Where Z is the input impedance, FS is the full scale of the device
for the frequency in question, SNR is the value for the particular
input level and Signal is the signal level within the ADC reported
in dB below full scale. This value includes both thermal and
quantization noise.

Power Supply Rejection Ratio

The ratio of a change in input offset voltage to a change in power
supply voltage.

Signal-to-Noise-and-Distortion (SINAD)

The ratio of the rms signal amplitude (set 1 dB below full scale)
to the rms value of the sum of all other spectral components,
including harmonics, but excluding dc.

Signal-to-Noise Ratio (Without Harmonics)

The ratio of the rms signal amplitude (set at 1 dB below full scale)
to the rms value of the sum of all other spectral components,
excluding the first five harmonics and dc.

Spurious-Free Dynamic Range (SFDR)

The ratio of the rms signal amplitude to the rms value of the peak
spurious spectral component. The peak spurious component may
or may not be a harmonic. May be reported in dBc (i.e., degrades
as signal level is lowered), or dBFS (always related back to con-
verter full scale).

Two-Tone Intermodulation Distortion Rejection

The ratio of the rms value of either input tone to the rms value
of the worst third order intermodulation product; reported in dBc.

Two-Tone SFDR

The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an IMD product. May be reported in dBc
(i.e., degrades as signal level is lowered), or in dBFS (always
related back to converter full scale).

Worst Other Spur

The ratio of the rms signal amplitude to the rms value of the worst
spurious component (excluding the 2nd and 3rd harmonic)
reported in dBc.

AD6644

REV. 0

Typical Performance Characteristics

FREQUENCY MHz

120

130

110

100

90

80

70

60

50

40

30

20

10

ENCODE = 65MSPS
AIN = 2.2MHz @ 1dBFS
SNR = 74.5dB
SFDR = 92dBc

Figure 8. Single Tone at 2.2 MHz

FREQUENCY MHz

120

130

110

100

90

80

70

60

50

40

30

20

10

ENCODE = 65MSPS
AIN = 15.5MHz @ 1dBFS
SNR = 74dB
SFDR = 90dBc

Figure 9. Single Tone at 15.5 MHz

FREQUENCY MHz

120

130

110

100

90

80

70

60

50

40

30

20

10

ENCODE = 65MSPS
AIN = 30MHz @ 1dBFS
SNR = 73.5dB
SFDR = 85dBc

Figure 10. Single Tone at 30 MHz

FREQUENCY MHz

SNR

74.5

73.5

72.5

72.0

74.0

T = 25 C

73.0

75.0

ENCODE = 65MSPS, AIN = 1dBFS

TEMP = 25 C, 25 C, 85 C

T = 85 C

Figure 11. Noise vs. Analog Frequency (Nyquist)

ANALOG INPUT FREQUENCY MHz

WORST-CASE HARMONIC

dBc

T = 25 C

T = 25 C, 85 C

ENCODE = 65MSPS, AIN = 1dBFS

TEMP = 25 C, 25 C, 85 C

Figure 12. Harmonics vs. Analog Frequency (Nyquist)

ANALOG FREQUENCY MHz

100

SNR

AIN = 1dBFS
ENCODE = 65MSPS

PHASE NOISE OF ANALOG SOURCE
DEGRADES PERFORMANCE

LOW NOISE ANALOG SOURCE

Figure 13. Noise vs. Analog Frequency (IF)

AD6644

REV. 0

HARMONICS (2

, 3

)

ANALOG FREQUENCY MHz

100

HARMONICS

dBc

100

WORST OTHER SPUR

ENCODE = 65MSPS
AIN = 1dBFS

Figure 14. Harmonics vs. Analog Frequency (IF)

ANALOG INPUT POWER LEVEL dBFS

80

WORST-CASE SPURIOUS

dBFS and dBc

70

40

20

10

100

120

60

50

30

110

SFDR = 90dB
REFERENCE LINE

ENCODE = 65MSPS
AIN = 15.5MHz

dBc

dBFS

Figure 15. Single Tone SFDR

FREQUENCY MHz

120

130

110

100

90

80

70

60

50

40

30

20

10

ENCODE = 65MSPS
AIN = 19MHz,
19.5MHz @ 7dBFS
NO DITHER

Figure 16. Two Tones at 19 MHz and 19.5 MHz

FREQUENCY MHz

120

130

110

100

90

80

70

60

50

40

30

20

10

ENCODE = 65MSPS
AIN = 15MHz,
15.5MHz @ 7dBFS
NO DITHER

Figure 17. Two Tones at 15 MHz and 15.5 MHz

INPUT POWER LEVEL (F1 = F2) dBFS

77

WORST-CASE SPURIOUS

dBFS and dBc

67

27

17

100

57

47

37

110

ENCODE = 65MSPS
F1 = 15MHz
F2 = 15.5MHz

SFDR = 90dB
REFERENCE LINE

dBFS

dBc

Figure 18. Two-Tone SFDR

ENCODE FREQUENCY MHz

SNR, WORST SPURIOUS

dB and dBc

100

WORST SPUR

SNR

AIN = 2.2MHz @ 1dBFS

Figure 19. SNR, Worst Spurious vs. Encode

AD6644

REV. 0

FREQUENCY MHz

120

130

110

100

90

80

70

60

50

40

30

20

10

ENCODE = 65MSPS
AIN = 15.5MHz @ 29.5dBFS
NO DITHER

Figure 20. 1M FFT Without Dither

90

WORST-CASE SPURIOUS

dBc

80

30

10

70

50

40

100

ENCODE = 65MSPS
AIN = 15.5MHz
NO DITHER

60

20

ANALOG INPUT POWER LEVEL dBFS

SFDR = 90dB
REFERENCE LINE

Figure 21. SFDR Without Dither

ENCODE = 65MSPS

30.5MHz

ENCODE INPUT POWER dBm

15.0

SNR, WORST SPURIOUS

dB and dBc

10.0

5.0

10.0

WORST SPUR

2.2MHz

30.5MHz

SNR

Figure 22. SNR, Worst Spurious vs. Clamped Encode
Power (See Figure 25)

FREQUENCY MHz

120

130

110

100

90

80

70

60

50

40

30

20

10

ENCODE = 65MSPS
AIN = 15.5MHz @ 29.5dBFS
DITHER @ 19dBm

Figure 23. 1M FFT with Dither

90

WORST-CASE SPURIOUS

dBc

80

30

10

70

50

40

100

ENCODE = 65MSPS
AIN = 15.5MHz
DITHER = 19dBm

60

20

ANALOG INPUT POWER LEVEL dBFS

SFDR = 90dB
REFERENCE LINE

SFDR = 100dB
REFERENCE LINE

Figure 24. SFDR with Dither

AD6644

REV. 0

THEORY OF OPERATION

The AD6644 analog-to-digital converter (ADC) employs a three
stage subrange architecture. This design approach achieves the
required accuracy and speed while maintaining low power and
small die size.

As shown in the functional block diagram, the AD6644 has
complementary analog input pins, AIN and AIN . Each analog
input is centered at 2.4 V and should swing

± 0.55 V around

this reference (Figure 2). Since AIN and AIN are 180 degrees
out of phase, the differential analog input signal is 2.2 V peak-
to-peak.

Both analog inputs are buffered prior to the first track-and-hold,
TH1. The high state of the ENCODE pulse places TH1 in hold
mode. The held value of TH1 is applied to the input of a 5-bit
coarse ADC1. The digital output of ADC1 drives a 5-bit digital-
to-analog converter, DAC1. DAC1 requires 14 bits of precision
which is achieved through laser trimming. The output of DAC1
is subtracted from the delayed analog signal at the input of TH3
to generate a first residue signal. TH2 provides an analog pipe-
line delay to compensate for the digital delay of ADC1.

The first residue signal is applied to a second conversion stage
consisting of a 5-bit ADC2, 5-bit DAC2, and pipeline TH4.
The second DAC requires 10 bits of precision which is met by
the process with no trim. The input to TH5 is a second residue
signal generated by subtracting the quantized output of DAC2
from the first residue signal held by TH4. TH5 drives a final
6-bit ADC3.

The digital outputs from ADC1, ADC2, and ADC3 are added
together and corrected in the digital error correction logic to
generate the final output data. The result is a 14-bit parallel
digital CMOS-compatible word, coded as two's complement.

APPLYING THE AD6644
Encoding the AD6644

The AD6644 encode signal must be a high quality, extremely low
phase noise source to prevent degradation of performance. Main-
taining 14-bit accuracy places a premium on encode clock phase
noise. SNR performance can easily degrade by 3 dB to 4 dB
with 70 MHz input signals when using a high-jitter clock source.
See Analog Devices' Application Note AN-501, "Aperture Uncer-
tainty and ADC System Performance" for complete details.

For optimum performance, the AD6644 must be clocked
differentially. The encode signal is usually ac-coupled into the
ENCODE and ENCODE pins via a transformer or capacitors.
These pins are biased internally and require no additional bias.

Shown below is one preferred method for clocking the AD6644.
The clock source (low jitter) is converted from single-ended to
differential using an RF transformer. The back-to-back Schottky
diodes across the transformer secondary limit clock excursions
into the AD6644 to approximately 0.8 V p-p differential. This
helps prevent the large voltage swings of the clock from feeding
through to the other portions of the AD6644, and limits the noise
presented to the ENCODE inputs. A crystal clock oscillator can
also be used to drive the RF transformer if an appropriate limiting
resistor (typically 100

) is placed in the series with the primary.

ENCODE

AD6644

T14T

HSMS2812

DIODES

CLOCK

SOURCE

0.1 F

100

Figure 25. Crystal Clock Oscillator Differential Encode

If a low jitter ECL/PECL clock is available, another option is to
ac-couple a differential ECL/PECL signal to the encode input pins
as shown below. A device that offers excellent jitter performance
is the MC100LVEL16 (or same family) from Motorola.

ENCODE

AD6644

0.1 F

ECL/

PECL

Figure 26. Differential ECL for Encode

Analog Input

As with most new high-speed, high dynamic range analog-to-
digital converters, the analog input to the AD6644 is differential.
Differential inputs allow much improvement in performance
on-chip as signals are processed through the analog stages. Most
of the improvement is a result of differential analog stages having
high rejection of even order harmonics. There are also benefits
at the PCB level. First, differential inputs have high common-
mode rejection to stray signals such as ground and power noise.
Also, they provide good rejection to common-mode signals such as
local oscillator feedthrough.

The AD6644 input voltage range is offset from ground by 2.4 V.
Each analog input connects through a 500

resistor to a 2.4 V

bias voltage and to the input of a differential buffer (Figure 2). The
resistor network on the input properly biases the followers for maxi-
mum linearity and range. Therefore, the analog source driving the
AD6644 should be ac-coupled to the input pins. Since the differ-
ential input impedance of the AD6644 is 1 k

, the analog input

power requirement is only 2 dBm, simplifying the driver amplifier
in many cases. To take full advantage of this high-input imped-
ance, a 20:1 transformer would be required. This is a large ratio
and could result in unsatisfactory performance. In this case, a
lower step-up ratio could be used. The recommended method for
driving the analog input of the AD6644 is to use a 4:1 RF trans-
former. For example, if R

were set to 60.4

and R

were set

to 25

, along with a 4:1 transformer, the input would match

to a 50

source with a full-scale drive of 4.8 dBm. Series resis-

tors (R

) on the secondary side of the transformer should be

used to isolate the transformer from A/D. This will limit the
amount of dynamic current from the A/D flowing back into
the secondary of the transformer. The terminating resistor (RT)
should be placed on the primary side of the transformer.

AIN

AD6644

T14T

ANALOG INPUT

SIGNAL

0.1 F

Figure 27. Transformer-Coupled Analog Input Circuit

AD6644

REV. 0

In applications where dc-coupling is required, a new differential
output op amp from Analog Devices, the AD8138, can be used
to drive the AD6644 (Figure 28). The AD8138 op amp provides
single-ended-to-differential conversion, which reduces overall
system cost and minimizes layout requirements.

AD8138

499

AD6644

AIN

499

0.1 F

499

AIN

REF

DIGITAL
OUTPUTS

OCM

Figure 28. DC-Coupled Analog Input Circuit

Power Supplies

Care should be taken when selecting a power source. Linear
supplies are strongly recommended. Switching supplies tend to
have radiated components that may be "received" by the AD6644.
Each of the power supply pins should be decoupled as closely to
the package as possible using 0.1

µF chip capacitors.

The AD6644 has separate digital and analog power supply pins.
The analog supplies are denoted AV

and the digital supply

pins are denoted DV

. AV

and DV

should be separate

power supplies. This is because the fast digital output swings
can couple switching current back into the analog supplies. Note
that AV

must be held within 5% of 5 V. The AD6644 is speci-

fied for DV

= 3.3 V as this is a common supply for digital ASICs.

Output Loading

Care must be taken when designing the data receivers for the
AD6644. It is recommended that the digital outputs drive a
series resistor (e.g. 100

) followed by a gate like 74LCX574.

To minimize capacitive loading, there should only be one gate
on each output pin. An example of this is shown in the evaluation
board schematic shown in Figure 30. The digital outputs of the
AD6644 have a constant output slew rate of 1 V/ns. A typical
CMOS gate combined with a PCB trace will have a load of
approximately 10 pF. Therefore, as each bit switches, 10 mA
(10 pF 1 V 1 ns) of dynamic current per bit will flow in or out
of the device. A full scale transition can cause up to 140 mA
(14 bits 10 mA/bit) of current to flow through the output stages.
The series resistors should be placed as close to the AD6644 as
possible to limit the amount of current that can flow into the out-
put stage. These switching currents are confined between ground
and the DV

pin. Standard TTL gates should be avoided since

they can appreciably add to the dynamic switching currents of
the AD6644. It should also be noted that extra capacitive loading
will increase output timing and invalidate timing specifications.
Digital output timing is guaranteed with 10 pF loads.

Layout Information

The schematic of the evaluation board (Figure 30) represents a
typical implementation of the AD6644. A multilayer board is
recommended to achieve the best results. It is highly recom-
mended that high-quality, ceramic chip capacitors be used to
decouple each supply pin to ground directly at the device. The
pinout of the AD6644 facilitates ease of use in the implementa-

tion of high frequency, high resolution design practices. All of
the digital outputs are segregated to two sides of the chip, with
the inputs on the opposite side for isolation purposes.

Care should be taken when routing the digital output traces.
To prevent coupling through the digital outputs into the analog
portion of the AD6644, minimal capacitive loading should be
placed on these outputs. It is recommended that a fan-out of
only one gate be used for all AD6644 digital outputs.

The layout of the Encode circuit is equally critical. Any noise
received on this circuitry will result in corruption in the digi-
tization process and lower overall performance. The Encode clock
must be isolated from the digital outputs and the analog inputs.

Jitter Considerations

The signal-to-noise ratio (SNR) for an ADC can be predicted.
When normalized to ADC codes, Equation 1 accurately predicts
the SNR based on three terms. These are jitter, average DNL
error, and thermal noise. Each of these terms contributes to the
noise within the converter.

SNR

ANALOG

RMS

NOISE RMS

+ × ×

log

(

)

(

)

1 2

(1)

ANALOG

= analog input frequency.

J RMS

= rms jitter of the encode (rms sum of encode
source and internal encode circuitry).

= average DNL of the ADC (typically 0.41 LSB).

= Number of bits in the ADC.

NOISE RMS

= V rms thermal noise referred to the analog input

of the ADC (typically 2.5 LSB).

For a 14-bit analog-to-digital converter like the AD6644, aper-
ture jitter can greatly affect the SNR performance as the analog
frequency is increased. The chart below shows a family of curves
that demonstrates the expected SNR performance of the AD6644
as jitter increases. The chart is derived from the above equation.

For a complete discussion of aperture jitter, please consult
Analog Devices' Application Note AN-501, "Aperture
Uncertainty and ADC System Performance."

JITTER ps

SNR

0.1

0.2

0.3

0.4

0.5

0.6

AIN = 190MHz

AIN = 150MHz

AIN = 110MHz

AIN = 30MHz

AIN = 70MHz

Figure 29. SNR vs. Jitter

AD6644

REV. 0

AD6644ST/PCB Bill of Material

Item

Quantity

Reference

Description

C1, C2

Tantalum Chip Capacitor 10

µF

C3, C7, C8, C9, C10, C11, C16, C30, C31,

Ceramic Chip Capacitor 0508, 0.1

µF

C32, C4, C22, C23, C24, C25, C26, C27,
C28, C29

C12, C13, C14, C17, C18, C19, C20, C21

Ceramic Chip Capacitor 0508, 0.01

µF

CR1

HSMS2812 Surface Mount Diode

E3, E4, E5

3-Pin Header

F1, F2, F3, F4

Ferrite (Optional)

J1, J6

PCTB2

50-Pin Double Row Header

SMA Connector

J4, J5

BNC Connector

Surface-Mount Resistor 1206, 100

Surface-Mount Resistor 1206, 60.4

R3, R4, R5, R8

Surface-Mount Resistor 0805, 499

(Optional,

DC-Coupling Only)

R6, R7

Surface-Mount Resistor 0805, 25

Surface-Mount Resistor 0805, 348

R10

Surface-Mount Resistor 0805, 615

R35

Surface-Mount Resistor 0805, 49.9

R36, R37, R38, R39, R40, R41, R42, R43,

Surface-Mount Resistor 0402, 100

R44, R45, R46, R47, R48, R49, R50, R51,
R52, R53, R54, R55, R56, R57, R58, R59,
R60, R61, R62, R63, R64, R65

T2, T3

Surface-Mount Transformer Mini-Circuits T41, 1:4 Ratio

AD6644AST 14-Bit 65 MSPS A/D Converter

U2, U7

74LCX574 Octal Latch

AD8138 Single-to-Differential Amplifier (Optional DC
Coupling Only)

U4, U6

NC7SZ32 Two Input OR Gate

CTS Reeves Full-Size MX045 Crystal Clock Oscillator

EVALUATION BOARD

The evaluation board for the AD6644 is straightforward,
containing all required circuitry for evaluating the device. The
only external connections required are power supplies, clock,
and the analog inputs. The evaluation board includes the option
for an onboard clock oscillator for ENCODE.

Power to the analog supply pins of the AD6644 is connected via
the power terminal block (PCTB2). Power for the digital interface
is supplied via pin 1 of J6. The J2 connector mates directly with
SoftCell

Receive Signal Processor (AD6620, AD6624) evaluation

boards, allowing complete evaluation of system performance.

The analog input is connected via a BNC connector AIN, which
is transformer-coupled to the AD6644 inputs. The transformer
has a turns ratio of 1:4 to reduce the amount of input power
required to drive the AD6644.

The Encode signal may be generated using an onboard crystal
oscillator, U5. The on-board oscillator may be replaced by an
external encode source via the SMA connector labeled OPT_CLK
or BNC connector labeled ENCODE. If an external source is
used, it must be a high-quality and very low-phase noise source.

The AD6644 output data is latched using 74LCX574 (U7, U2)
latches. The clock for these latches is determined by selecting
jumper E3E4 or E4E5. E3 to E5 is a just a gate delayed ver-
sion of the clock, while connecting E4 to E5 utilizes the Data
Ready of the AD6644 to latch the output data. A clock is also
distributed with the output data (J2) that is labeled BUFLAT
(Pin 19 and 20, J2).

AD6644

REV. 0

OPT_CLK

SMA

348

R10

615

100nF

3P3V

GND

OUT

C22

100nF

FERRITE

5VA

GND

3P3VD

NC7SZ32

OPT_LAT

DR_OUT

BUFLAT

K1115

GND

5VA

GND

5VA

GND

100nF

5VA

GND

5VA

100nF

GND

AD6644ST

DR_OUT

3P3V

GND

5VA

GND

5VA

GND

PREF

3P3V

AIN

GND

AIN

GND

5VA

GND

3P3V

DRY

D13

D12

D11

D10

GND

DMID

GND

OVR

DNC

GND

REF

GND

ENC

GND

AIN

GND

100

R41

100

R40

100

R39

100

R38

100

R36

GND

100

R42

100

R43

OUT_EN

GND

CLOCK

74LCX574

AD8138

REF

GND

499

1:4

C30

100nF

60.4

BNC

499

5VA

499

AIN

ENC

CR1

C28

100nF

C27

100nF

C29

100nF

R35

49.9

ENC

BNC

100

100nF

1:4

HSMS2812

C32

100NF

REF

R61

100

R60

100

R59

100

R58

100

R37

100

BUFLAT

3P3VD

R62

100

R63

100

OVR

B02

B03

B04

B05

GND

B00

B01

GND

3P3VD

NC7SZ32

BUFLAT

B08

B07

B06

B10

B09

B11

B13

B12

100

R47

100

R48

100

R49

100

R50

100

R51

GND

100

R46

100

R45

OUT_EN

GND

CLOCK

74LCX574

R53

100

R54

100

R55

100

R56

100

R57

100

BUFLAT

3P3VD

R52

100

R65

100

R64

100

R44

HEADR50

GND

FERRITE

3P3V

GND

PCTB2

FERRITE

5VA

GND

PCTB2

C16

100nF

C17

10nF

C18

10nF

C19

10nF

C20

10nF

C21

10nF

100nF

C10

100nF

C11

100nF

C12

10nF

C13

10nF

C14

10nF

3P3V

FERRITE

C23

100nF

C24

100nF

C25

100nF

C26

100nF

3P3VD

MOUNTING HOLES

NOTE: THE DOTTED LINE REPRESENTS AN OPTIONAL ANALOG DRIVE INPUT

Figure 30. AD6644ST/PCB Schematic (GS02357D Schematic)

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