Äîêóìåíòàöèÿ è îïèñàíèÿ www.docs.chipfind.ru

REV. B

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

CMOS, ADC /4 DQPSK

Baseband Transmit Port

AD7011

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700

Fax: 617/326-8703

FEATURES
Single +5 V Supply

On-Chip /4 DQPSK Modulator

Modulator Bypass Analog Mode
Root-Raised Cosine Tx Filters, = 0.35
Two 10-Bit D/A Converters
4th Order Reconstruction Filters
Differential Analog Outputs
On-Chip Ramp Up/Down Power Control
On-Chip Tx Offset Calibration
Dual Mode Operation, Analog and Digital
Very Low Power Dissipation, 30 mW typical

Power Down Mode < 10

On-Chip Voltage Reference
24-Pin SSOP

APPLICATIONS
American Digital Cellular Telephony
American Analog Cellular Telephony

GENERAL DESCRIPTION

The AD7011 is a complete low power, CMOS,

/4 DQPSK

modulator with single +5 V power supply. The part is designed
to perform the baseband conversion of I and Q transmit wave-
forms in accordance with the American Digital Cellular Tele-
phone system (TIA IS-54).

The on-chip

/4 Differential Quadrature Phase Shift Keying

(DQPSK) digital modulator, which includes the root raised
cosine filters, generates I and Q data in response to the transmit
data stream. The AD7011 also contains ramp control envelope
logic to shape the I and Q output waveforms when ramping up
or down at the beginning or end of a transmit burst.

Besides providing all the necessary logic to perform

/4 DQPSK

modulation, the part also provides reconstruction filters to
smooth the DAC outputs, providing continuous time analog
outputs. The AD7011 generates differential analog outputs for
both the I and Q signals.

As it is a necessity for all digital mobile systems to use the lowest
possible power, the device has transmit and receive power-down
options. The AD7011 is housed in a space efficient 24-pin
SSOP (Shrink Small Outline Package).

FUNCTIONAL BLOCK DIAGRAM

Tx CLK (FRAME)

BOUT

QTx

MODE1

AD7011

ITx

10-BIT

I-DAC

RECONSTRUCTION

FILTERS

2.46V

REFERENCE

POWER

QTx

CALIBRATION CIRCUITRY

MODULATOR

BYPASS

10-BIT

Q-DAC

Tx DATA (I DATA)

DGND

MODE2

AGND

BYPASS

BIN (Q DATA)

RECONSTRUCTION

FILTERS

READY

ANALOG MODE

SERIAL

INTERFACE

/4 DQPSK

DIGITAL

MODULATOR

MCLK

REV. B

AD7011SPECIFICATIONS

= V

= +5 V 10%; Test = AGND = DGND = 0 V; Digital Mode,

MCLK

= 3.1104 MHz; Analog Mode, f

MCLK

= 2.56 MHz, POWER = V

. All specifications are T

MIN

to T

MAX

unless otherwise noted.)

Parameter

AD7011ARS

Units

Test Conditions/Comments

DIGITAL MODE TRANSMIT SPECIFICATIONS

Number of Channels

(ITx ITx) and (QTx QTx)

Output Signal Range

REF

+ V

REF

Volts

For Each Analog Output

Differential Output Range

REF

Volts

I Channel = (ITx ITx) and
Q Channel = (QTx QTx)

Signal Vector Magnitude

0.875

7.5%

Volts max

Measured Differentially

Error Vector Magnitude

% rms typ

2.5

% rms max

Offset Vector Magnitude

0.5

% typ

2.5

% max

IS-54 Spurious Power

2, 3

@ 30 kHz

dB typ

dB max

@ 60 kHz

dB typ

dB max

@ 90 kHz, 120 kHz

dB typ

dB max

ANALOG MODE SPECIFICATIONS

No. of Channels

(ITx ITx) and (QTx QTx)

Resolution

Bits

Output Signal Range

REF

Volts

For Each Analog Output

Differential Output Range

REF

Volts

I Channel = (ITx ITx) and
Q Channel = (QTx QTx)

DAC Update Rate

160

kHz

MCLK/16; f

MCLK

= 2.56 MHz

SNR

dB typ

Generating a 10 kHz Sine Wave

dB min

Differential Offset Error

mV max

Post Calibration

Group Delay Matching Between I & Q Outputs

ns typ

Coding

Twos Complement

Maximum and Minimum DAC Codes

+450/450

max/min

REFERENCE & CHANNEL SPECIFICATIONS

Reference, V

REF

2.46

Volts

Reference Accuracy

I and Q Gain Matching

0.2

dB max

Measured @ 10 kHz

Power-Down Option

Yes

Power = 0 V

LOGIC INPUTS

INH

, Input High Voltage

0.9

V min

INL

, Input Low Voltage

0.9

V max

INH

, Input Current

FA max

, Input Capacitance

pF max

LOGIC OUTPUTS

Output High Voltage

0.4

V min

OUT

Output Low Voltage

0.4

V max

OUT

1.6 mA

POWER SUPPLIES

4.5/5.5

V min/V max

Transmit Section Active

mA max

POWER = V

mA typ

Transmit Section Powered Down

A max

MCLK Active

A max

MCLK Inactive

NOTES

Operating temperature ranges as follows: A Version: 40

C to +85

See terminology.

Measured in continuous transmission and Burst Mode with the I and Q channels ramping up and down at the beginning and end of a burst.

Headroom must be allowed for the transmit DACs such that offsets in I & Q transmit channels can be calibrated out. Therefore, the full range of the I and Q DACs

are not available to the user. The user should ensure that binary codes greater than or less than the maximum or minimum are not loaded into the I or Q DACs.

Measured while the digital inputs to the transmit interface are static and equal to 0 V or V

Specifications subject to change without notice.

AD7011

REV. B

TRANSMIT SECTION TIMING

Parameter

Limit at T

= 40 C to +85 C

Units

Description

ns min

Power Setup Time.

ns max

4097t

+ 70

ns max

MCLK rising edge, after Power high, to READY rising edge.

ns min

BIN Setup Time.

ns max

+ 70

ns max

MCLK to READY propagation delay.

+ 70

MCLK rising edge, after BIN high, to first TxCLK rising edge.

64t

TxCLK Cycle Time.

32t

TxCLK High Time.

32t

TxCLK Low Time.

ns min

TxCLK falling edge to TxDATA setup time.

ns min

TxCLK falling edge to TxDATA hold time.

ns max

BIN low setup to Last transmitted symbol after ramp down.

124t

ns max

BIN low hold to Last transmitted symbol after ramp down.

7.5t

Ramp Down cycle time after the last transmitted symbol.

30t

ns max

Last TxCLK falling edge to READY rising edge.

ns max

Digital Output Rise Time.

ns max

Digital Output Fall Time.

MCLK

READY

BIN

TxCLK

TxDATA

POWER

Figure 4. Transmit Timing at the Start of a Tx Burst

MCLK

READY

BIN

TxCLK

TxDATA

N+4

N+5

N+8

POWER

Figure 5. Transmit Timing at the End of a Tx Burst

= V

= +5 V 10%; AGND = DGND = 0 V, f

MCLK

= 3.1104 MHz. All specifications are

MIN

to T

MAX

unless otherwise noted.)

AD7011

REV. B

ANALOG MODE TIMING

Parameter

Limit at T

= 40

C to +85

Units

Description

ns min

MCLK Rising Edge to FRAME Setup Time.

ns min

MCLK Rising Edge to FRAME Hold Time.

15t

ns max

16t

FRAME Cycle Time.

ns min

MCLK Rising Edge to Data Setup Time.

ns min

MCLK Rising Edge to Data Hold Time.

= V

= +5 V

10%. AGND = DGND = 0 V. All specifications are T

MIN

to T

MAX

unless

otherwise noted.)

MCLK

FRAME

I DATA

DB9

DB8

DB1

DB0

DB9

DB8

DB7

Q DATA

DB9

DB8

DB1

DB0

DB9

DB8

DB7

Figure 6. Analog Mode Serial Interface Timing

MODULAR OUTPUT

DURING FTEST

Figure 7. Modulator State During FTEST

Table I.

MODE 1

MODE 2

Operation

Digital TIA Mode

Analog Mode

FTEST

Factory Test, Reserved

Table II.

Mode of Operation

MODE 1

MODE 2

MCLK

Digital Bit Rate

DAC Update Rate

Digital Mode

3.1104 MHz

48.6 kHz

N/A

Analog Mode

2.56 MHz

N/A

160 kHz

AD7011

REV. B

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . +150

SSOP

Thermal Impedance . . . . . . . . . . . . . . . . +122

C/W

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . +215

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . +220

*Stresses above those listed under "Absolute Maximum Ratings" may cause

permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

ABSOLUTE MAXIMUM RATINGS*

= +25

C unless otherwise noted)

Tx, V

Rx to AGND . . . . . . . . . . . . . . . 0.3 V to +7 V

AGND to DGND . . . . . . . . . . . . . . . . . . . . 0.3 V to +0.3 V
Digital I/O Voltage to DGND . . . . . . . 0.3 V to V

+ 0.3 V

Analog I/O Voltage to AGND . . . . . . . 0.3 V to V

+ 0.3 V

Operating Temperature Range

Industrial (A Version) . . . . . . . . . . . . . . . 40

C to +85

Storage Temperature Range . . . . . . . . . . . 65

C to + 150

WARNING!

ESD SENSITIVE DEVICE

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although this device features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

ORDERING GUIDE

Model

Temperature Range

Package Description

Package Option

AD7011ARS

C to +85

Shrink Small Outline Package

RS-24

SSOP PIN CONFIGURATION

POWER

BIN (QDATA)

TxCLK (FRAME)

TxDATA (IDATA)

DGND

MCLK

MODE1

BOUT

AGND

QTx

AGND

ITx

AGND

BYPASS

TOP VIEW

(Not to Scale)

AD7011

MODE2

READY

NC = NO CONNECT

AD7011

REV. B

PIN FUNCTION DESCRIPTION

SSOP Pin
Number

Mnemonic

Function

POWER SUPPLY
19

Positive power supply for analog section.

Positive power supply for digital section.

14, 18, 23

AGND

Analog ground for transmit section.

DGND

Digital ground for transmit section.

ANALOG SIGNAL AND REFERENCE
13

BYPASS

Reference decoupling output. A decoupling capacitor should be connected between this pin and AGND.

16, 17

ITx, ITx

Differential analog outputs for the I channel, representing true and complementary outputs of the I
waveform.

21, 20

QTx, QTx

Differential analog outputs for the Q channel, representing true and complementary outputs of the Q
waveform.

TRANSMIT INTERFACE AND CONTROL
7

MCLK

Master clock, digital input. When operating in Mode 0 (TIA Digital mode), this pin should be driven by a
3.1104 MHz CMOS compatible clock source in digital mode and by 2.56 MHz CMOS compatible clock
source for analog mode.

TxCLK

This is a dual function digital input/output. When operating in Mode 0 (TIA Digital mode), this pin is

(FRAME)

configured as a digital output, transmit clock. This may be used to clock in transmit data at 48.6 kHz. When
operating in Mode 1 (analog mode), this pin is configured as a digital input, FRAME. This is used to frame
the clocking in of 16-bit words when bypassing the

/4 DQPSK modulator and directly loading the I and Q

10-bit DACs.

TxDATA

This is a dual function digital input. When operating in Mode 0 (TIA Digital mode), this pin is used to

(IDATA)

clock in transmit data on the falling edge of TxCLK at a rate of 48.6 kHz. When operating in Mode 1
(Analog mode), I data is clocked in on the rising edge of MCLK. This data bypasses the

/4 DQPSK modu-

lator and is loaded into the 10-bit I DAC.

BIN (QDATA) This is a dual function digital input. When operating in Mode 0 (TIA Digital mode), this input is used to ini-

tiate the ramping up (BIN high) or down (BIN low) of the I and Q waveforms. When operating in Mode 1
(Analog mode), Q data is clocked in on the rising edge of MCLK. This data bypasses the

/4 DQPSK modu-

lator and is loaded into the 10-bit Q DAC.

BOUT

Burst Out, digital output. This is the BIN input delayed by the pipeline delay, both digital and analog, of the
AD7011. This can be used to turn on and off the RF amplifiers in synchronization with the I and Q waveforms.

POWER

Transmit sleep mode, digital input. When this goes low, the AD7011 goes into sleep mode, drawing minimal
current. When this pin goes high, the AD7011 is brought out of sleep mode and initiates a self-calibration
routine to eliminate the offset between ITx & ITx and the offset between QTx & QTx.

READY

Transmit ready, digital output. This output goes high once the self-calibration routine is complete.

9, 11

MODE1,

Mode control, digital inputs. These are used to enter the AD7011 into three different operating modes,

MODE2

see Table I.

8, 10, 15, 22

No Connects. These pins are no connects and should not be used as routes for other circuit signals.

AD7011

REV. B

TERMINOLOGY
Error Vector Magnitude

This is a measure of the rms error vector introduced by the
AD7011 where signal error vector is defined as the rms devia-
tion of a transmitted symbol from its ideal position when filtered
by an Ideal RRC Receive filter, as illustrated in Figure 8.

Gain Matching Between Channels

The is the gain matching between the I and Q outputs, measured
when transmitting all zeros.

Offset Vector Magnitude

This is a measure of the offset vector introduced by the AD7011
as illustrated in Figure 8. The offset vector is calculated so as to
minimize the rms error vector for each of the constellation
points.

Output Signal Range and Different Output Range

The output signal range is the output voltage swing and dc bias
level for each of the analog outputs. The different output range
is the difference between ITx and ITx for the I channel and the
difference between QTx and QTx for the Q Channel.

IS-54 Spurious Power

This is the rms sum of the spurious power measured at multiples
of 30 kHz, in a root raised cosine window of

16.4 kHz, relative

to twice the rms power in a RRC window in the 0 to 16.4 kHz
band.

Signal Vector Magnitude

This is the radius of the IQ constellation diagram as illustrated
in Figure 8.

Signal to (Noise + Distortion) Ratio

This is the measured ratio of signal to (noise + distortion) at the
output of the transmit I and Q DACs. The signal is the rms
amplitude of the fundamental. Noise is the rms sum of all non-
fundamental signals up to half the sampling frequency (f

/2),

excluding dc. The ratio is dependent upon the number of
quantization levels in the digitization process; the more levels,
the smaller the quantization noise. The theoretical signal to
(noise distortion) ratio for a sine wave is given by:

SNR = (6.02N + 1.76) dB

where N is the number of bits. Thus for an ideal 10-bit con-
verter, SNR = 61.96 dB.

ERROR VECTOR

OFFSET

VECTOR

0,0

SIGNAL VECTOR

Figure 8.

AD7011

REV. B

Figure 10.

/4 DQPSK Constellation Diagram

Figure 10 illustrates the

/4 DQPSK constellation diagram as

described above, showing the eight possible states for [I

, Q

The I

and Q

impulses are then filtered by FIR raised root

cosine filters (

= 0.35), generating 10-bit I and Q data. The

FIR root raised cosine filters have an impulse response of

symbols.

Transmit Calibration

When the transmit section is brought out of sleep mode
(POWER high), the transmit section initiates a self-calibration
routine to remove the offset between ITx and ITx and an offset
between QTx and QTx. READY goes high on the completion
of the self-calibration routine. Once READY goes high, BIN
(Burst In) can be brought high to initiate a transmit burst.

Ramp-Up/Down Envelope Logic

The AD7011 provides on-chip envelope shaping logic, providing
power shaping control for the beginning and end of a transmit
burst. When BIN (Burst In) is brought high, the modulator is
reset to a transmitting all zeros state (i.e., X

= Y

= 0) and

continues to transmit all zeros for the first three symbols, during
which the ramp-up envelope goes from zero to full scale as
illustrated in Figure 11. The next symbol to be transmitted is
[I

, Q

], which represents the first two data bits clocked in after

BIN going high, i.e., [X

, Y

 COS

1
2

 + COS

1
2

3 SYMBOLS

Figure 11. Ramp Envelope

When BIN is brought low, indicating the end of a transmit
burst, the current Di-bit symbol [X

N+4

, Y

N+4

] that the AD7011

is receiving will be the last symbol to be computed for the four
symbol ramp-down sequence. Also the N

symbol is the last

active symbol prior to ramping down.

However, because the impulse response is equal to

4 symbols,

four additional symbols are required to fully compute the analog
outputs when transmitting the (N+4)

symbol. Hence there will

be eight subsequent TxCLKs, latching four additional Di-bit
symbols: [X

N + 5

, Y

N + 5

] to [X

N + 8

, Y

N + 8

CIRCUIT DESCRIPTION

TRANSMIT SECTION
The transmit section of the AD7011 generates

/4 DQPSK I

and Q waveforms in accordance with TIA specification. This is
accomplished by a digital

/4 DQPSK modulator, which

includes the root-raised cosine filters (

= 0.35), followed by

two 10-bit DACs and on-chip reconstruction filters. The

DQPSK (Differential Quadrature Phase Shift Keying) digital
modulator generates 10-bit I and Q data in response to the
transmit data stream. The 10-bit I and Q DACs are filtered by
on-chip reconstruction filters, which also generate differential
analog outputs for both I and Q channels.

The AD7011 transmit channel also provides an analog mode,
where direct access to the I and Q DACs is provided, bypassing
the

/4 DQPSK modulator. This is provided so that the

AD7011 transmit channel can also be used to perform the
conversion and filtering of the analog waveforms required to
emulate the existing analog cellular system.

/4 DQPSK Modulator

The

/4 DQPSK modulator generates 10-bit I and Q data

(Inphase and Quadrature) which are loaded into the I and Q
10-bit transmit DACs.

Figure 9 shows the functional block diagram of the

/4 DQPSK

modulator. The transmit serial data (TxDATA) is first con-
verted into Di-bit symbols [X

, Y

], using a 2-bit serial to parallel

converter. The data is then differentially encoded; symbols are
transmitted as changes in phase rather than absolute phases.
Each symbol represents a phase change, as illustrated in Table
III, and this along with the previously transmitted symbol
determines the next symbol to be transmitted. The differential
phase encoder generates I and Q impulses [I

, Q

] in response to

the Di-bit symbols according to:

= COS [

]

= SIN [

]

DIFFERENTIAL

PHASE

ENCODER

ROOT-RAISED

COSINE FILTER

I DATA

Q DATA

2-BIT

SERIAL TO
PARALLEL

CONVERTER

/4 DQPSK DIGITAL

MODULATOR

ROOT-RAISED

COSINE FILTER

TxDATA

Figure 9.

/4 DQPSK Modulator Functional Block Diagram

Table III.

AD7011

REV. B

As Figure 12 illustrates, the ramp-down envelope reaches zero
after three symbols, hence the fourth symbol does not actually
get transmitted.

Reconstruction Filters

The reconstruction filters smooth the DAC output signals,
providing continuous time I and Q waveforms at the output
pins. These are 4th order Bessel low-pass filters with a 3 dB
frequency of approximately 25 kHz. The filters are designed to
have a linear phase response in the passband and due to the
reconstruction filters being on-chip, the phase mismatch
between the I and Q transmit channels is kept to a minimum.

Transmit Section Digital Interface

MODE1 = MODE2 = DGND: Digital

/4 DQPSK Mode

Figures 4 and 5 shows the timing diagrams for the transmit
interface when operating in TIA

/4 DQPSK mode. POWER is

sampled on the rising edge of MCLK. When POWER is
brought high, the transmit section is brought out of sleep mode
and initiates a self-calibration routine as described above. Once
the self-calibration is complete, the READY signal goes high to
indicate that a transmit burst can now begin. BIN (Burst in) is
brought high to initiate a transmit burst and should only be
brought high if the READY signal is already high.

When BIN goes high, the READY signal goes low on the next
rising edge of MCLK and TxCLK becomes active after a
further three MCLK cycles. TxCLK can be used to clock out
the transmit data from the ASIC or DSP on the rising edge of
TxCLK and the AD7011 will latch TxDATA on the falling
edge of TxCLK.

When BIN is brought low, the AD7011 will continue to clock in
the current Di-bit symbol (X

N + 4

, Y

N + 4

) and will continue for a

further 8 TxCLK cycles (four symbols). After the final TxCLK,
READY goes high waiting for BIN to be brought high to begin
the next transmit burst.

N+1

N+2

N+3

N+4

3 SYMBOL

RAMP-UP ENVELOPE

3 SYMBOL

RAMP-DOWN ENVELOPE

N+1

N+2

N+3

N+4

SYMBOL

PHASE MAX

EFFECT

= 480

BIN

TxCLK

TxDATA

BOUT

(ITxITx),

(QTxQTx)

N+5

N+6

N+7

N+8

Figure 12. Transmit Burst

When POWER is brought low this puts the transmit section into
a low power sleep mode, drawing minimal current. The analog
outputs go high impedance while in low power sleep mode.

MODE1 = V

; MODE2 = DGND: Analog Mode

Figure 6 shows the timing diagram for the transmit interface
when operating in analog mode. In this mode the

/4 DQPSK

modulator is bypassed and direct access to the I and Q 10-bit
DACs is provided. Loading of the I and Q DACs is accom-
plished using a 4 wire 16-bit serial interface. The pins TxCLK,
TxDATA and BIN are all reconfigured as inputs, with the
functions of FRAME, IDATA and QDATA respectively.

I and Q data are loaded via the IDATA and QDATA pins and
FRAME synchronizes the loading of the 16-bit I and Q words.
FRAME should be brought high one clock cycle prior to the I
and Q MSBs. Data is latched on the rising edge of MCLK,
MSB first, where only the first 10 data bits are significant. Con-
tinuous updating of the I and Q DACs is required at a rate of
MCLK/16.

MODE1 = DGND; MODE2 = V

: Frequency Test Mode

A special FTEST (Frequency TEST) mode is provided for the
customer, where no phase modulation takes place and the mod-
ulator outputs remain static. ITx is set to zero and QTx is set to
full scale as Figure 7 illustrates. However, the normal ramp-up/
down envelope is still applied during the beginning and end of a
burst.

MODE1 = MODE2 = V

: Factory Test Mode

This mode is reserved for factory test only and should not be
used by the customer for correct device operation.

AD7011

REV. B

40

80

1000

100

0.1

60

20

30

50

70

10

FREQUENCY kHz

MAGNITUDE dBs

Figure 13. Reconstruction Filter Frequency Response for
the I and Q DACs, MCLK = 2.56 MHz

I Channel Volts

Q Channel Volts

1.2

0.8

0.4

1.2

0.8

0.4

0.8

0.4

I Channel Volts

Q Channel Volts

1.2

0.8

0.4

1.2

0.8

0.4

0.8

0.4

Figure 14. AD7011 I vs. Q Waveforms When Transmitting
Random Data

I Channel Volts

Q Channel Volts

1.2

0.8

0.4

1.2

0.8

0.4

0.8

0.4

Figure 15. AD7011 Transmit Constellation Diagram

40

80

1000

100

0.1

60

20

30

50

70

10

FREQUENCY kHz

MAGNITUDE dBs

Figure 16. Reconstruction Filter Frequency Response for
the I and Q DACs, MCLK = 3.1104 MHz

I Channel Volts

Q Channel Volts

1.2

0.8

0.4

1.2

0.8

0.4

0.8

0.4

Figure 17. AD7011 I vs. Q Waveforms Filtered by an Ideal
Root Raised Cosine Receive Filter

I Channel Volts

Q Channel Volts

1.2

0.8

0.4

1.2

0.8

0.4

0.8

0.4

Figure 18. AD7011 Constellation Diagram When Filtered
by an Ideal Root Raised Cosine Receive Filter

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: AD7011ARS

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: AD7011ARS