AD7142/AD7142-1 Programmable Capacitance-to-Digital Converter with Environmental Compensation Preliminary Data Sheet (Rev. PrD)

Programmable Capacitance-to-Digital

Converter with Environmental

Compensation

Preliminary Technical Data

AD7142/AD7142-1

Rev. PrD

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700

www.analog.com

Fax: 781.461.3113

FEATURES

Programmable capacitance-to-digital converter

30 Hz update rate (@ maximum sequence length)
Better than one femto Farad resolution
14 capacitance sensor input channels
No external RC tuning components required
Automatic conversion sequencer

On-chip automatic calibration logic

Automatic compensation for environmental changes
Automatic adaptive threshold and sensitivity levels

On-chip RAM to store calibration data
SPI®- or I

C®- (AD7142-1) compatible serial interface

Separate V

DRIVE

level for serial interface

Interrupt output and GPIO
32-lead, 5 mm x 5 mm LFCSP
2.7 V to 3.3 V supply voltage
Low operating current

Full power mode: less than1 mA
Low power mode: 50 A

APPLICATIONS

Personal music and multimedia players
Cell phones
Digital still cameras
Smart hand-held devices
Television, A/V and remote controls
Gaming consoles

FUNCTIONAL BLOCK DIAGRAM

TEST

REF+

REF

SDO/

SDA

SDI/

ADD0

SCLK CS/

ADD1

INT

SHIELD

SRC

DRIVE

SWI

MATRIX

16-BIT

CDC

CALIBRATION

ENGINE

AD7142

CONTROL

AND

DATA

REGISTERS

CALIBRATION

RAM

240kHz

EXCITATION

SOURCE

SERIAL INTERFACE

AND CONTROL LOGIC

INTERRUPT

AND GPIO

LOGIC

POWER-ON

RESET

LOGIC

AGND

DGND1

DGND2

GPIO

CIN0

CIN1

CIN2

CIN3

CIN4

CIN5

CIN6

CIN7

CIN8

CIN9

CIN10

CIN11

CIN12

CIN13

05702-

001

Figure 1.

GENERAL DESCRIPTION

The AD7142 and AD7142-1 are integrated capacitance-to-
digital converters (CDCs) with on-chip environmental
calibration for use in systems requiring a novel user input
method. The AD7142 and AD7142-1 can interface to external
capacitance sensors implementing functions such as capacitive
buttons, scroll bars, or joypads.

The CDC has 14 inputs, channeled through a switch matrix to a
16-bit, 240 kHz sigma-delta (-) capacitance-to-digital
converter. The CDC is capable of sensing changes in the
capacitance of the external sensors and uses this information to
register a sensor activation. The external sensors can be
arranged as a series of buttons, as a scroll bar or wheel, or as a
combination of sensor types. By programming the registers, the
user has full control over the CDC setup. High resolution scroll
bar sensors require software to run on the host processor.

The AD7142 and AD7142-1 have on-chip calibration logic to
account for

changes in the ambient environment. The calibration

sequence is performed automatically and at continuous intervals,
while the sensors are not touched. This ensures that there are no
false or nonregistering touches on the external sensors due to a
changing environment.

The AD7142 has an SPI-compatible serial interface, and the
AD7142-1 has an I

C-compatible serial interface. Both versions

of AD7142 have an interrupt output, as well as a general-purpose
input output (GPIO).

The AD7142 and AD7142-1 are available in a 32-lead, 5 mm ×
5 mm LFCSP package and operate from a 2.7 V to 3.3 V supply.
The operating current consumption is less than 1 mA, falling
to 50 A in low power mode (conversion interval of 400 ms).

AD7142/AD7142-1

Preliminary Technical Data

Rev. PrD | Page 2 of 64

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General

Description......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

SPI Timing Specifications AD7142............................................ 4

C Timing Specifications AD7142-1 ........................................ 5

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

Pin Configuration

and Functional Descriptions......................... 7

Typical Performance Characteristics ............................................. 8

Theory of Operation ........................................................................ 9

Capacitance Sensing Theory....................................................... 9

Operating Modes........................................................................ 10

Capacitance Sensor Input Configuration.................................... 11

CIN Input Multiplexer Setup .................................................... 11

Capacitiance-to-Digital Converter............................................... 12

Oversampling the CDC Output ............................................... 12

Capacitance Sensor Offset Control.......................................... 12

Conversion Sequencer ............................................................... 12

CDC Conversion Time .............................................................. 13

CDC Conversion Results........................................................... 14

Non-Contact Proximity Detection............................................... 15

Environmental Calibration ........................................................... 19

Adaptive Threshold and Sensitivity ............................................. 20

Interrupt Output............................................................................. 21

CDC Conversion Complete Interrupt..................................... 21

Sensor Threshold Interrupt ...................................................... 21

GPIO INT Output Control ....................................................... 22

Outputs ............................................................................................ 24

Excitation Source........................................................................ 24

SHIELD

Output ............................................................................. 24

GPIO ............................................................................................ 24

Serial Interface ................................................................................ 25

SPI Interface ................................................................................ 25

C Interface ................................................................................ 27

DRIVE

Input ................................................................................. 29

PCB Design Guidelines ................................................................. 30

Capacitive Sensor Board Mechanical Specifications ............. 30

Chip Scale Packages ................................................................... 30

Power-Up Sequence ....................................................................... 31

Typical Application Circuits ......................................................... 32

Detailed Register Descriptions ..................................................... 34

Bank 1 Registers ......................................................................... 34

Bank 2 Registers ......................................................................... 44

Bank 3 Registers ......................................................................... 47

Outline Dimensions ....................................................................... 62

Ordering Guide .......................................................................... 62

REVISION HISTORY

12/05--Preliminary Version D

7/05--Preliminary Version C

2/05--Preliminary Version B

1/05--Preliminary Version A

Preliminary Technical Data

AD7142/AD7142-1

Rev. PrD | Page 3 of 64

SPECIFICATIONS

= 2.7 V to 3.3 V, T

= -40

C to +85°C, unless otherwise noted.

Table 1.

Parameter Min

Typ

Max

Unit

Test

Conditions/Comments

CAPACITANCE-TO-DIGITAL

CONVERTER

Update Rate

Maximum programmed sequence length

Resolution

Bit

Range

±2

No Missing Codes

Bit

Guaranteed by design, but not production
tested

Total Unadjusted Error

TBD

Power Supply Rejection

500

aF/V

Output Noise (Peak-to-Peak)

aF/Hz

Parasitic Capacitance

Parasitic capacitance to ground, guaranteed
by characterization

EXCITATION

SOURCE

Frequency

TBD 240

TBD kHz

Output Voltage

Short-Circuit

Current

Maximum Output Load

500

Capacitance load on source to ground

SHIELD

Output Drive

SHIELD

Bias Level

LOGIC INPUTS (SDI, SCLK, CS, SDA, GPI, TEST)

Input High Voltage

0.7 x V

DRIVE

Input Low Voltage

0.3 x V

DRIVE

Input High Voltage

-1

Input Low Voltage

Hysteresis

150

OPEN-DRAIN OUTPUTS (SDO, SDA, INT)

Output Low Voltage

0.4

SINK

= -1 mA

Output High Leakage Current

0.1

OUT

= V

DRIVE

LOGIC OUTPUTS

Output Low Voltage

0.4

SINK

= 1 mA, V

DRIVE

= 1.6 V to DV

+ 0.3 V

Output High Voltage

DRIVE

- 0.6

SOURCE

= 1 mA

Floating State Leakage Current

±10

Pin tri-stated

POWER

CC,

2.7 3.6 V

DRIVE

1.65 DV

+ 0.3

Serial interface operating voltage

TBD

Full power mode

TBD

Low power mode (conversion delay = 400 ms)

TBD

Full

shutdown

AD7142/AD7142-1

Preliminary Technical Data

Rev. PrD | Page 4 of 64

SPI TIMING SPECIFICATIONS AD7142

= -40°C to +105°C; V

DRIVE

= 1.8 V to 3.6 V; AV

, DV

= 2.7 V to 3.6 V, unless otherwise noted. Sample tested at 25°C to ensure

compliance. All input signals are specified with t

= t

= 5 ns (10% to 90% of V

) and timed from a voltage level of 1.6 V.

Table 2. SPI Timing Specifications

Parameter

Limit at T

MIN

, T

MAX

Unit Description

SCLK

kHz min

MHz max

ns min

CS falling edge to first SCLK falling edge

ns min

SCLK high pulse width

ns min

SCLK low pulse width

ns min

SDI set-up time

ns min

SDI hold time

ns max

SDO access time after SCLK falling edge

ns max

CS rising edge to SDO high impedance

TBD ns

SCLK rising edge to CS high

Mark/space ratio (duty cycle) for the DCLK input is 40/60 to 60/40.

SCLK

SDI

SDO

MSB

LSB

MSB

LSB

05702-002

Figure 2. SPI Detailed Timing Diagram

Preliminary Technical Data

AD7142/AD7142-1

Rev. PrD | Page 5 of 64

C TIMING SPECIFICATIONS AD7142-1

= -40°C to +105°C; V

DRIVE

= 1.8 V to 3.6 V; AV

, DV

= 2.7 V to 3.6 V, unless otherwise noted.

Sample tested at 25°C to ensure compliance. All input signals timed from a voltage level of 1.6 V.

Table 3. I

C Timing Specifications

Parameter

Limit

Unit

Description

SCLK

400

kHz max

0.6

s min

Start condition hold time, t

HD; STA

1.3

s min

Clock low period, between 10% points, t

LOW

0.6

s min

Clock high period, between 90% points, t

HIGH

100

ns min

Data setup time , t

SU; DAT

ns min

Data hold time, t

HD; DAT

0.6

s min

Stop condition setup time, t

SU; STO

0.6

s min

Start condition setup time, t

SU; STA

1.3

s min

Bus free time between stop and start conditions, t

BUF

300

ns max

Clock/data rise time

300

ns max

Clock/data fall time

Guaranteed by design, but not production tested.

05702-003

SCLK

SDATA

STOP START

STOP

START

Figure 3. I

C Detailed Timing Diagram

AD7142/AD7142-1

Preliminary Technical Data

Rev. PrD | Page 6 of 64

ABSOLUTE MAXIMUM RATINGS

Table 4.

Parameter Rating

to AGND, DV

to DGND

-0.3 V to +3.6 V

Analog Input Voltage to AGND

-0.3 V to AV

+ 0.3 V

Digital Input Voltage to DGND

-0.3 V to V

DRIVE

+ 0.3 V

Digital Output Voltage to DGND

-0.3 V to V

DRIVE

+ 0.3 V

Input Current to Any Pin Except
Supplies

10 mA

ESD Rating

2.5 kV

Operating Temperature Range

-40°C to +105°C

Storage Temperature Range

-65°C to +150°C

Junction Temperature

150°C

LFCSP Package

Power Dissipation

450 mW

Thermal Impedance

135.7°C/W

IR Reflow Peak Temperature

260°C (±0.5°C)

Lead Temperature (Soldering 10 sec)

300°C

Transient currents of up to 100 mA do not cause SCR latch-up.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

200

1.6V

TO OUTPUT

PIN

50pF

05702-004

Figure 4. Load Circuit for Digital Output Timing Specifications

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Preliminary Technical Data

AD7142/AD7142-1

Rev. PrD | Page 7 of 64

PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS

05702-005

PIN 1
INDICATOR

CIN3

CIN4

CIN5

CIN6

CIN7

CIN8

CIN9

CIN10

24 CS
23 SCLK
22 SDI
21 SDO
20 V

DRIVE

19 DGND2
18 DGND1
17 DV

I
N

1
0

I
N

1
1

I
N

1
2

I
E

1
3

1
4

I
N

2
9

I
O

I
N

TOP VIEW

(Not to Scale)

AD7142

Figure 5. AD7142, 32-Lead LFCSP Pin Configuration

PIN 1
INDICATOR

CIN3

CIN4

CIN5

CIN6

CIN7

CIN8

CIN9

CIN10

24 ADD1
23 SCLK
22 ADD0
21 SDA
20 V

DRIVE

19 DGND2
18 DGND1
17 DV

I
N

1
2

I
N

1
3

I
E

3
2

I
N

3
0

I
N

2
6

I
O

2
5

I
N

TOP VIEW

(Not to Scale)

AD7142-1

05702-044

Figure 6. AD7142-1, 32-Lead LFCSP Pin Configuration

Table 5. Pin Function Descriptions

Pin No.

Name

Description

CIN3

Capacitance Sensor Input.

CIN4

Capacitance Sensor Input.

CIN5

Capacitance Sensor Input.

CIN6

Capacitance Sensor Input.

CIN7

Capacitance Sensor Input.

CIN8

Capacitance Sensor Input.

CIN9

Capacitance Sensor Input.

CIN10

Capacitance Sensor Input.

CIN11

Capacitance Sensor Input.

CIN12

Capacitance Sensor Input.

CIN13

Capacitance Sensor Input.

12 C

SHIELD

CDC Shield Potential Output. Requires 10 nF capacitor to ground. Connect to external shield.

13 AV

CDC Supply Voltage.

AGND

Analog Ground Reference Point for All CDC Circuitry. Tie to analog ground plane.

SRC

CDC Excitation Source Output.

SRC

Inverted Excitation Source Output.

17 DV

Digital Core Supply Voltage.

18 DGND1

Digital

Ground.

19 DGND2

Digital

Ground.

20 V

DRIVE

Serial Interface Operating Voltage Supply.

SDO

AD7142 SPI Serial Data Output.

SDA AD7142-1

C Serial Data Input/Output. SDA requires pull-up resistor.

SDI

AD7142 SPI Serial Data Input.

ADD0

AD7142-1

C Address Bit 0.

SCLK

Clock Input for Serial Interface.

AD7142 SPI Chip Select Signal.

ADD1

AD7142-1

C Address Bit 1.

INT

General Purpose Interrupt Output. Programmable polarity. Requires pull-up resistor.

26 GPIO Programmable

GPIO.

TEST

Factory Test Pin. Tie to ground.

28 V

REF+

CDC Positive Reference Input. Normally tied to analog power.

29 V

REF-

CDC Negative Reference Input. Tie to analog ground.

CIN0

Capacitance Sensor Input.

CIN1

Capacitance Sensor Input.

CIN2

Capacitance Sensor Input.

Preliminary Technical Data

AD7142/AD7142-1

Rev. PrD | Page 9 of 64

THEORY OF OPERATION

The AD7142 and AD7142-1 are capacitance-to-digital
converters (CDCs) with on-chip environmental compensation,
intended for use in portable systems requiring high resolution
user input. The internal circuitry consists of a 16-bit, - con-
verter that converts a capacitive input signal into a digital value.
There are 14 input pins on the AD7142 and AD7142-1, CIN0 to
CIN13. A switch matrix routes the input signals to the CDC.
The result of each capacitance-to-digital conversion is stored in
on-chip registers. The host subsequently reads the results over
the serial interface. The AD7142 contains an SPI interface and
the AD7142-1 has an I

C interface ensuring that the parts are

compatible with a wide range of host processors. Because the
AD7142 and AD7142-1 are identical parts, with the exception of
the serial interface, AD7142 refers to both the AD7142 and
AD7142-1 throughout this data sheet.

The AD7142 interfaces with to up to 14 external capacitance
sensors. These sensors can be arranged as buttons, scroll bars,
joypads, or as a combination of sensor types. The external
sensors consist of electrodes on a 2- or 4-layer PCB that
interfaces directly to the AD7142.

The AD7142 can be set up to implement any set of input
sensors by programming the on-chip registers. The registers
can also be programmed to control features such as averaging,
offsets, and gains for each of the external sensors. There is a
sequencer on-chip to control how each of the capacitance
inputs is polled.

The AD7142 has on-chip digital logic and 528 words of RAM
that are used for environmental compensation. The effects of
humidity, temperature, and other environmental factors can
effect the operation of capacitance sensors. Transparent to the
user, the AD7142 performs continuous calibration to
compensate for these effects, allowing the AD7142 to give
error-free results at all times.

The AD7142 requires some minor companion software that
runs on the host or other microcontroller to implement sensor
functions such as a scroll bar or joypad. However, no companion
software is required to implement buttons, including 8-way
button functionality. The algorithms required for button
sensors are implemented in digital logic on-chip.

The AD7142 can be programmed to operate in either always
powered mode, or in an automatic wake-up mode. The auto
wake-up mode is particularly suited for portable devices that
require low power operation giving the user significant power
savings coupled with full functionality.

The AD7142 has a general interrupt output, INT, to indicate
when new data has been placed into the registers. INT is used
to interrupt the host on sensor activation. The AD7142 oper-
ates from a 2.7 V to 3.6 V supply, and is available in a 32-lead,
5 mm × 5 mm LFCSP.

CAPACITANCE SENSING THEORY

The AD7142 uses a method of sensing capacitance known as
the shunt method. Using this method, an excitation source is
connected to a transmitter generating an electric field to a
receiver. The field lines measured at the receiver are translated
into the digital domain by a - converter. When a finger, or
other grounded object, interferes with the electric field, some of
the field lines are shunted to ground and do not reach the
receiver (see Figure 8). Therefore, the total capacitance
measured at the receiver decreases when an object comes close
to the induced field.

EXCITATION
SIGNAL
240KHz

ADC

16-BIT

DATA

05702-007

Figure 8. Sensing Capacitance Method

In practice, the excitation source and - ADC are implemented
on the AD7142, while the transmitter and receiver are constructed
on a PCB that makes up the external sensor.

Registering a Sensor Activation

When a sensor is approached, the total capacitance associated
with that sensor, measured by the AD7142, changes. When the
capacitance changes to such an extent that a set threshold is
exceeded, the AD7142 registers this as a sensor touch.

For example, consider the case of two button sensors that are
connected to the AD7142 in a differential manner. When one
button is activated, the AD7142 registers an increase in capacitance;
if the other button is activated, the AD7142 registers a decrease
in capacitance. If neither of the buttons are activated, the AD7142
measures the background or ambient capacitance level.

AD7142/AD7142-1

Preliminary Technical Data

Rev. PrD | Page 10 of 64

Preprogrammed threshold levels are used to determine if a
change in capacitance is due to a button being activated. If the
capacitance exceeds one of the threshold limits, the AD7142
registers this as a true button activation.

The same thresholds principle is used to determine if other
types of sensors, such as sliders or joypads, are activated.

Complete Solution for Capacitance Sensing

Analog Devices provides a complete solution for capacitance
sensing. The two main elements to the solution are the sensor
PCB and the AD7142.

If the application requires sensors in the shape of a slider or
joypad, software is required that runs on the host processor.
(No software is required for button sensors.) The software
typically requires 3 kB of code and 500 bytes of data memory
for a slider sensor.

HOST PROCESSOR

1 MIPS

3kB ROM

500BYTES RAM

AD7142

SPI or I

SENSOR PCB

05702-008

Figure 9. 3-Part Capacitance Sensing Solution

Analog Devices supplies the sensor PCB design to the customer
based on the customer's specifications, and supplies any necessary
software on an open-source basis. Standard sensor designs are
also available as PCB library components.

OPERATING MODES

The AD7142 has three operating modes. Full power mode,
where the device is always fully powered, is suited for applications
where power is not a concern, for example game consoles that
have an ac power supply. Low power mode, where the part
automatically powers down, is tailored to give significant power
savings over full power mode, and is suited for mobile applications
where power must be conserved. The AD7142 also has a com-
plete shutdown mode.

The POWER_MODE bits (Bit 0 and Bit 1) of the control
register set the operating mode on the AD7142. The control
register is at Address 0x000.

Table 6. POWER_MODE Settings

POWER_MODE Bits

Operating Mode

Full power mode

Full shutdown mode

Low power mode

Full shutdown mode

Table 6 shows the POWER_MODE settings for each operating
mode. To put the AD7142 into shutdown mode, set the
POWER_MODE bits to either 01 or 11.

The power-on default setting of the POWER_MODE bits is 00,
full power mode.

Full Power Mode

In full power mode, all sections of the AD7142 remain fully
powered at all times. While a sensor is being touched, the
AD7142 processes the sensor data. If no sensor is touched, the
AD7142 measures the ambient capacitance level and uses this
data for the on-chip compensation routines. In full power
mode, the AD7142 converts at a constant rate. See the CDC
Conversion Time section for more information.

Low Power Mode

When in low power mode, the AD7142 POWER_MODE bits
are set to 10 upon device initialization. If the external sensors
are not touched, the AD7142 reduces its conversion frequency,
thereby greatly reducing its power consumption. The part
remains in a low power state while the sensors are not touched.
Every 400 ms, the AD7142 performs a conversion and uses this
data to update the compensation logic. When an external
sensor is touched, the AD7142 begins a conversion sequence
every 40 ms to read back data from the sensors. In low power
mode, the total current consumption of the AD7142 is an
average of the current used during a conversion, and the
current used while the AD7142 is waiting for the next
conversion to begin. For example, when the low power mode
conversion interval is 400 ms, the AD7142 uses typically 0.9 mA
current for 40 ms, and 15 A for 360 ms of the conversion
interval. (Note that these conversion timings can be altered
through the register settings. See the CDC Conversion Time
section for more information.)

ANY

SENSOR

TOUCHED?

AD7142 SETUP

AND INITIALIZATION

POWER_MODE = 10

YES

SEQUENCER-CONTROLLED

CONVERSIONS ON ALL SENSORS

EVERY 40ms

YES

PROXIMITY

TIMER

COUNT DOWN

TIMEOUT

CONVERSIONS EVERY 400ms

UPDATE COMPENSATION

LOGIC DATA PATH

ANY

SENSOR

TOUCHED?

ANY

SENSOR

TOUCHED?

05702-009

Figure 10. Low Power Mode Operation

Preliminary Technical Data

AD7142/AD7142-1

Rev. PrD | Page 11 of 64

CAPACITANCE SENSOR INPUT CONFIGURATION

Each stage of the AD7142 capacitance sensors can be uniquely
configured by using the registers in Table 53 and Table 54. These
registers are used to configure input pin connection set ups,
sensor offsets, sensor sensitivities, and sensor limits for each
stage. Apply this feature to optimize the function of each sensor
to the application. For example, a button sensor connected to
STAGE0 may require a different sensitivity and offset values
than a button with a different function that is connected to a
different stage.

CIN INPUT MULTIPLEXER SETUP

The CIN_CONNECTION_SETUP registers in Table 53 list the
different options that are provided for connecting the sensor
input pin to the CDC converter.

The AD7142 has an on-chip multiplexer to route the input
signals from each pin to the input of the converter. Each input
pin can be tied to either the negative or the positive input of the
CDC, or it can be left floating. Each input can also be internally
connected to the C

SHIELD

signal to help prevent cross coupling. If

an input is not used, always connect it to C

SHIELD.

For each input pin, CIN0 to CIN13, the multiplexer settings can
be set on a per sequencer stage basis. For example, CIN0 is
connected to the negative CDC input for conversion STAGE1,
left floating for sequencer STAGE1, and so on for all twelve
conversion stages.

Two bits in each register control the mux setting for the input pin.

CIN0

CIN1

CIN2

CIN3

CIN4

CIN5

CIN6

CIN7

CIN8

CIN9

CIN10

CIN11

CIN SETTING

CIN_CONNECTION
_SETUP BITS

CINX FLOATING

CINX CONNECTED TO

NEGATIVE CDC INPUT

CINX CONNECTED TO

POSITIVE CDC INPUT

CINX CONNECTED TO

SHIELD

CDC

05702-010

CIN12

CIN13

Figure 11. Input Mux Configuration Options

AD7142/AD7142-1

Preliminary Technical Data

Rev. PrD | Page 12 of 64

CAPACITIANCE-TO-DIGITAL CONVERTER

The capacitance-to-digital converter on the AD7142 has a
sigma-delta (-) architecture with 16-bit resolution. There are
14 possible inputs to the CDC that are connected to the input of
the converter through a switch matrix. The sampling frequency
of the CDC is 240 kHz.

OVERSAMPLING THE CDC OUTPUT

It is possible to sample the result of any CDC conversion at a
rate less than 240 kHz. The decimation rate, or oversampling
ratio, is determined by Bits[9:8] of the control register, as listed
in Table 7.

Table 7. CDC Decimation Rate

Decimation Bit Value

Decimation Rate

CDC Sample Rate

00 256

312.5

01 128

625

10 64

1.25

kHz

11 64

1.25

kHz

The decimation process on the AD7142 is an averaging process
where a number of samples are taken and the averaged result is
output. The amount of samples taken is set equal to the
decimation rate, so 256, 128, or 64 samples are averaged to
obtain the CDC output.

The decimation process reduces the amount of noise present in
the final CDC result. However, the higher the decimation rate,
the lower the sampling frequency, thus, a tradeoff is required
between a noise-free signal and speed of sampling.

CAPACITANCE SENSOR OFFSET CONTROL

Apply the STAGE_OFFSET registers to null any capacitance
sensor offsets associated with printed circuit board parasitic
capacitance, or capacitance due to any other source, such as
connectors. This is only required once during the initial
capacitance sensor characterization.

A simplified block diagram in Figure 12 shows how to apply the
STAGE_OFFSET registers to null the offsets. The 7-bit
POS_AFE_OFFSET and NEG_AFE_OFFSET registers provide
0.16 pF resolution offset adjustment over a range of 20 pF. Apply
the positive and negative offsets to either the positive or the
negative CDC input using the NEG_AFE_OFFSET and
POS_AFE_OFFSET registers.

POS_AFE_OFFSET

REGISTER

16-BIT

CDC

NEG_AFE_OFFSET

REGISTER

+DAC

(20pF RANGE)

POS_AFE_OFFSET_SWAP

REGISTER

NEG_AFE_OFFSET_SWAP

REGISTER

CIN

EXT

CIN_CONNECTION_SETUP

REGISTER

SEN

SOR

DAC

(20pF RANGE)

05702-011

Figure 12. Analog Front End Offset Control

CONVERSION SEQUENCER

The AD7142 has an on-chip sequencer to implement
conversion control for the input channels. Up to 12 conversion
stages can be performed in sequence. By using the Bank 2
registers, each stage can be uniquely configured to support
multiple capacitance sensor interface requirements. For
example, a slider sensor can be assigned to STAGE1 with a
button sensor assigned to STAGE2.

The AD7142 on-chip sequencer controller provides conversion
control beginning with STAGE0. Figure 13 shows a block diagram
of the CDC conversion stages and CIN inputs. A conversion
sequence is defined as a sequence of CDC conversion starting at
STAGE0 and ending at the stage determined by the value pro-
grammed in the SEQUENCE_STAGE_NUM register. In Figure 14,
the conversion sequence is from STAGE0 through STAGE5.
Depending on the number and type of capacitance sensors that are
used, not all conversion stages are required. Use the
SEQUENCE_STAGE_NUM register to set the number of
conversions in one sequence, depending on the sensor interface
requirements. For example, this register would be set to 5 if the
CIN inputs were mapped to only six stages as shown in Figure 14.
In addition, set the STAGE_CAL_EN registers according to the
number of stages that are used.

Preliminary Technical Data

AD7142/AD7142-1

Rev. PrD | Page 13 of 64

CIN0
CIN1
CIN2
CIN3
CIN4
CIN5
CIN6
CIN7
CIN8
CIN9

CIN10
CIN1 1
CIN12
CIN13

STAGE 0

STAGE 1

STAGE 2

STAGE 3

STAGE 4

STAGE 5

STAGE 6

STAGE 7

STAGE 8

STAGE 9

STAGE 10

STAGE 11

SWITCH MATRIX

16-BIT

ADC

05702-012

Figure 13. AD7142 CDC Conversion Stages

CIN0
CIN1
CIN2
CIN3
CIN4
CIN5
CIN6
CIN7
CIN8
CIN9

CIN10
CIN1 1
CIN12
CIN13

STAGE 0

STAGE 1

STAGE 2

STAGE 3

STAGE 4

STAGE 5

STAGE 6

STAGE 7

STAGE 8

STAGE 9

STAGE 10

STAGE 11

SWITCH MATRIX

16-BIT

ADC

NOTES
1. SEQUENCE_STAGE_NUM = 5.
2. FF_SKIP_CNT = 3 (VALUE SELECTED FROM TABLE 8
FOR DECIMATION = 128).

SEQUENCE_CONV_NUM

FF_SKIP_CNT

05702-013

Figure 14. Example Using SEQUENCE_CON_NUM and

FF_SKIP_CNT Registers

The number of required conversion stages depends wholly on
the number of sensors attached to the AD7142. Figure 15 shows
how many conversion stages are required for each sensor, and
how many inputs to the AD7142 each sensor requires.

BUT

STAGE 0

CIN1

CIN2

CDC

STAGE 2

CDC

STAGE 1

SLIDER

8-WAY SWITCH

CDC

STAGE 3

CDC

CIN3

CIN5

STAGE 4

CDC

CIN4

CIN6

CIN7

STAGE 5

CDC

CIN8

AD7142 SEQUENCER

05702-014

Figure 15. Sequencer Setup for Sensors

A button sensor generally requires one sequencer stage;
however, it is possible to configure two button sensors to
operate differentially. Only one button from the pair can be
activated at a time; pressing both buttons together results in
neither button being activated. This configuration requires one
conversion stage.

A slider sensor requires two stages: one stage for sensor
activation; the other stage for measuring positional data from
the slider. In Figure 15, the slider activation uses STAGE2, while
the positional data uses STAGE3.

The 8-way switch is made from two pairs of differential buttons.
It, therefore, requires two conversion stages, one for each of the
differential button pairs. The buttons are orientated so that one
pair makes up the top and bottom portions of the 8-way switch;
the other pair makes up the left and right portions of the 8-way
switch.

CDC CONVERSION TIME

The time required for one complete measurement by the CDC
is defined as the CDC conversion time. For optimal system per-
formance, configure the AD7142 CDC conversion time within a
range of 35 ms to 40 ms. The SEQUENCE_STAGE_NUM,
FF_SKIP_CNT, and DECIMATION registers determine the
conversion time as listed in Table 8.

AD7142/AD7142-1

Preliminary Technical Data

Rev. PrD | Page 14 of 64

Table 8. CDC Conversion Times for Full Power Mode

DECIMATION = 64

DECIMATION = 128

DECIMATION = 256

SEQUENCE_STAGE_NUM

FF_SKIP_CNT

CDC Conversion
Time (ms)

FF_SKIP_CNT

CDC Conversion
Time (ms)

FF_SKIP_CNT

CDC Conversion
Time (ms)

0 11

9.2

18.4

36.5

1 11

18.4

36.8

36.5

2 11

27.6

36.8

36.5

3 11

36.8

36.5

4 9

38.4

46.0

5 7

36.8

6 6

37.6

32.2

43.0

7 5

36.8

49.1

8 4

34.5

41.4

27.6

9 4

38.4

30.7

10 3

33.8

33.7

11 3

36.8

For example, while operating with a decimation rate of 128,
if the SEQUENCE_STAGE_NUM register is set to 5 for the
conversion of six stages in a sequence, the FF_SKIP_CNT
register should be set to 3 resulting in a conversion time of
36.8 ms. This example is shown in Figure 14.

Determining the FF_SKIP_CNT value is only required one time
during the initial setup of the capacitance sensor interface. This
value determines which CDC samples are not used (skipped) in
the proximity detection fast FIFO.

Full Power Mode CDC Conversion Time

The full power mode CDC conversion time is set by
configuring the SEQUENCE_STAGE_NUM, FF_SKIP_CNT
and DECIMATION registers as outlined in Table 8.

Figure 16 shows a simplified timing diagram of the full power
CDC conversion time. The full power mode CDC conversion
time t

CONV_FP

is set using Table 8.

NOTES
1.

CONV_FP

= VALUE SET FROM TABLE 8.

CONV_FP

CONVERSION

N + 1

CDC

CONVERSION

N + 2

05702-015

Figure 16. Full Power Mode CDC Conversion Time

Low Power Mode CDC Conversion Time with Delay

The frequency of each CDC conversion while operating in the
low power automatic wake up mode is controlled by using the
LP_CONV_DELAY register bits (Bits[3:2] in Register 0x00), in
addition to the registers listed in Table 8. This feature provides
some flexibility for optimizing the conversion time to meet
system requirements vs. AD7142 power consumption. For
example, maximum power savings is achieved when the

LP_CONV_DELAY is set to 3. With a setting of 3, the AD7142
automatically wakes up, performing a conversion every 400 ms.

Table 9. LP_CONV_DELAY Settings

LP_CONV_DELAY BITS

Delay Between Conversions

100 ms

200 ms

300 ms

400 ms

Figure 17 shows a simplified timing example of the low power
CDC conversion time. As shown, the low power CDC
conversion time is set by t

CONV_FP

and the LP_CONV_DELAY

NOTES
1.

CONV_LP

= t

CONV_FP

+ LP_CONV_DELAY

CONV_LP

CONVERSION N

CONVERSION N + 1

CDC

CONVERSION

05702-016

Figure 17. Low Power Mode CDC Conversion Time CDC Conversion Results

CDC CONVERSION RESULTS

Certain applications, such as a slider function, require reading
back the CDC conversion results for host processing. The
registers required for host processing are located in Register
Bank 3. The host processes the data read back from these
registers to determine relative position information.

In addition to the results registers in Bank 3, the AD7142
provides the 16-bit CDC output data directly starting at
Address 0x00B of Register Bank 1. Reading back the CDC
16-bit conversion data register allows for customer specific
application data processing.

Preliminary Technical Data

AD7142/AD7142-1

Rev. PrD | Page 15 of 64

NON-CONTACT PROXIMITY DETECTION

The AD7142 internal signal processing continuously monitors
all capacitance sensors for non-contact proximity detection.
This feature provides the ability to detect when a user is
approaching a sensor, at which time all internal calibration is
immediately disabled while the AD7142 is automatically
configured to detect a valid contact.

The proximity control register bits are described in Table 10.
The FP_PROXIMITY_CNT and LP_PROXIMITY_CNT register
bits control how long the calibration disable period is after
proximity is detected. The calibration is disabled during this
time and enabled again at the end of this period provided that
the user is no longer approaching, or in contact with, the sensor.
Figure 18 and Figure 19 show examples of how these registers
are used to set the full and low power mode calibration disable
periods.

Recalibration

In the event of a very long proximity detection event, such as a
user hovering over a sensor for a long period of time, the
FP_PROXIMITY_RECAL and LP_PROXIMITY_RECAL bits
in register 0x004 can be applied to force a recalibration. This
feature ensures that the ambient values are recalibrated
regardless of how long the user may be hovering over a sensor.
A recalibration ensures maximum AD7142 sensor performance.
Figure 20 and Figure 21 show examples of using the
FP_PROXIMITY_RECAL and LP_PROXIMITY_RECAL

register bits to force a recalibration while operating in the full
and low power modes. These figures show a user approaching a
sensor followed by the user leaving the sensor while the
proximity detection remained active after the user left the
sensor. This situation could occur if the user interaction created
some moisture on the sensor for example thus causing the new
sensor value to be different from the expected value. In this
case, the internal recalibration would be applied to
automatically recalibrate the sensor. The force calibration event
takes two interrupt cycles: nothing should be read from or
written to the AD7142 during the recalibration period.

Proximity Sensitivity

There are two conditions that set the internal proximity
detection signal as described in Figure 22 with Comparator 1
and Comparator 2. Comparator 1 detects when a user is
approaching a sensor. The sensitivity of Comparator 1 is
controlled by PROXIMITY_DETECTION_RATE. For example,
if PROXIMITY_DETECTION_RATE is set to 4, the Proximity
1 signal is set when the absolute difference between WORD1
and WORD3 exceed four LSB codes. Comparator 2 detects
when a user is hovering over a sensor or approaches a sensor
very slowly. The sensitivity of Comparator 2 is controlled by the
PROXIMITY_RECAL_LVL in

PROXIMITY_RECAL_LVL is set to 75, the Proximity 2 signal
is set when the absolute difference between the fast filter
average value and the ambient value exceeds 75 LSB codes.

Table 10. Proximity Control Registers (Refer to Figure 22)

Register

Length
(Bits)

Register Address

Description

FP_PROXIMITY_CNT

0x002

Full power mode proximity control

LP_PROXIMITY_CNT

0x002

Low power mode proximity control

FP_PROXIMITY_RECAL

0x004

Full power mode proximity recalibration control

LP_PROXIMITY_RECAL

0x004

Low power mode proximity recalibration control

PROXIMITY_RECAL_LVL

0x003

Proximity recalibration level

PROXIMITY_DETECTION_RATE

0x003

Proximity detection rate

CALIBRATION ENABLED

CALIBRATION DISABLED

PROXIMITY DETECTION

(INTERNAL)

CALIBRATION

(INTERNAL)

CALDIS

CONV_FP

USER APPROCHES
SENSOR HERE

USER LEAVES SENSOR

AREA HERE

1 2 3 4 5 6 7 8 9 10 11 1213 14 15 16

CDC CONVERSIONS

(INTERNAL)

05702-017

Figure 18. Full Power Mode Proximity Detection Example with FP_PROXIMITY = 1

AD7142/AD7142-1

Preliminary Technical Data

Rev. PrD | Page 16 of 64

NOTES
1. CONVERSION TIME

CONV_LP

= (

CONV_FP

+ LP_CONV_DELAY).

2. PROXIMITY IS SET WHEN USER APPROACHES THE SENSOR AT WHICH TIME THE INTERNAL CALIBRATION IS DISABLED.
3.

CALDIS

= (

CONV_LP

LP_PROXIMITY_CNT

4) + LP_CONV_DELAY.

CALIBRATION ENABLED

CALIBRATION DISABLED

PROXIMITY DETECTION

(INTERNAL)

CALIBRATION

(INTERNAL)

CALDIS

CONV_FP

USER APPROCHES
SENSOR HERE

USER LEAVES SENSOR

AREA HERE

1 2 3 4 5 6 7 8 9 10 11 1213 14 15 16

CDC CONVERSIONS

(INTERNAL)

05702-018

Figure 19. Low Power Mode Proximity Detection with LP_PROXIMITY = 4 and LP_CONV_DELAY = 0

CALIBRATION ENABLED

CALIBRATION DISABLED

DISCAL

USER APPROCHES

SENSOR HERE

USER LEAVES SENSOR

AREA HERE

RECAL

CONV_FP

USER IN CONTACT WITH SENSOR

CDC CONVERSION VALUES EXCEED
PROXIMITY_RECALIBRATION _LVL

RECALIBRATION PERIOD

PROXIMITY DETECTION

(INTERNAL)

CALIBRATION

(INTERNAL)

CDC CONVERSIONS

(INTERNAL)

RECALIBRATION

(INTERNAL)

05702-

019

NOTES
1. CONVERSION TIME

CONV_FP

DETERMINED FROM TABLE 8

DISCAL

CONV_FP

FP_PROXIMITY_CNT)

RECAL

= (

CONV_FP

FP_PROXIMITY_RECAL)

Figure 20. Full Power Mode Proximity Detection with Forced Recalibration Example with FP_PROXIMITY = 1 and FP_PROXIMITY_RECAL = 40

AD7142/AD7142-1

Preliminary Technical Data

Rev. PrD | Page 18 of 64

16-BIT

CDC

STAGE_FF_WORD0

N = 0

PROXIMITY_DETECTION_RATE

REGISTER 0x003

PROXIMITY_RECAL_LVL

REGISTER 0x003

BANK 3 REGISTERS

PROXIMITY

AVERAGE AMBIENT

XIMITY

SLOW_FILTER_UPDATE_LVL

REGISTER 0x003

WORD 0 WORD 3

BANK 3 REGISTERS

SLOW

FIL

SW1

NOTES
1. SLOW FILTER EN IS SET AND SW1 IS CLOSED WHEN /WORD 0WORD 3/ EXCEEDS THE VALUE PROGRAMMED IN THE SLOW_FILTER_UPDATE REGISTER PROVIDING
PROXIMITY IS NOT SET.
2. PROXIMITY 1 IS SET WHEN /WORD 0WORD 3/ EXCEEDS THE VALUE PROGRAMMED IN THE PROXIMITY_DETECTION_RATE REGISTER.
3. PROXIMITY 2 IS SET WHEN /AVERAGEAMBIENT/ EXCEEDS THE VALUE PROGRAMMED IN THE PROXIMITY_RECAL_LVL REGISTER.
4. DESCRIPTION OF COMPARATOR FUNCTIONS:
COMPARATOR 1: USED TO DETECT WHEN A USER IS APPROACHING OR LEAVING A SENSOR.
COMPARATOR 2: USED TO DETECT WHEN A USER IS HOVERING OVER A SENSOR, OR APPROACHING A SENSOR VERY SLOWLY.
ALSO USED TO DETECT IF THE SENSOR AMBIENT LEVEL HAS CHANGED AS A RESULT OF THE USER INTERACTION.
FOR EXAMPLE, HUMIDITY OR DIRT LEFT BEHIND ON SENSOR.
COMPARATOR 3: USED TO ENABLE THE SLOW FILTER UPDATE RATE. THE SLOW FILTER IS UPDATED WHEN SLOW FILTER EN IS SET AND PROXIMITY IS NOT SET.

STAGE_SF_WORD0

CONTROL

LOGIC

FP_PROXIMITY_RECAL

REGISTER 0x004

LP_PROXIMITY_RECAL

REGISTER 0X004

COMPARATOR 3

PROXIMITY

AMBIENT VALUE

STAGE_SF_WORDX

CDC OUT

CODE

TIME

SENSOR

CONTACT

STAGE_SF_AMBIENT

BANK 3 REGISTERS

STAGE_FF_AVG

BANK 3 REGISTERS

STAGE_MAX_WORD0
STAGE_MAX_WORD1
STAGE_MAX_WORD2
STAGE_MAX_WORD3

STAGE_MAX_AVG

BANK 3 REGISTERS

STAGE_HIGH_THRESHOLD

BANK 3 REGISTERS

STAGE_MAX_TEMP

BANK 3 REGISTERS

MAX LEVEL
DETECTION

LOGIC

BANK 3 REGISTERS

STAGE_MIN_WORD0
STAGE_MIN_WORD1
STAGE_MIN_WORD2
STAGE_MIN_WORD3

STAGE_MIN_AVG

BANK 3 REGISTER3

STAGE_LOW_THRESHOLD

BANK 3 REGISTERS

STAGE_MIN_TEMP

BANK 3 REGISTERS

MIN LEVEL

DETECTION

LOGIC

BANK 3 REGISTERS

FP_PROXIMITY_CNT

REGISTER 0x004

LP_PROXIMITY_CNT

REGISTER 0X004

PROXIMITY 1

PROXIMITY TIMING

CONTROL LOGIC

WORD 0 WORD 3

COMPARATOR 1

COMPARATOR 2

WORD(N)

05702-

021

STAGE_SF_WORD2

STAGE_SF_WORD1

STAGE_SF_WORD4

STAGE_SF_WORD3

STAGE_SF_WORD5

STAGE_SF_WORD7

STAGE_SF_WORD6

STAGE_FF_WORD7

STAGE_FF_WORD6

STAGE_FF_WORD5

STAGE_FF_WORD4

STAGE_FF_WORD3

STAGE_FF_WORD2

STAGE_FF_WORD1

STAGE_FF_WORDX

Figure 22. AD7142 Proximity Detection and Environmental Calibration

Preliminary Technical Data

AD7142/AD7142-1

Rev. PrD | Page 19 of 64

ENVIRONMENTAL CALIBRATION

The AD7142 provides on-chip capacitance sensor calibration to
automatically adjust for environmental conditions that have an
effect on the capacitance sensor ambient levels. Capacitance
sensor output levels are sensitive to temperature, humidity, and
in some cases, dirt. The AD7142 achieves optimal and reliable
sensor performance by continuously monitoring the CDC
ambient levels and correcting for any changes by adjusting the
initial STAGE_OFFSET_HIGH and STAGE_OFFSET_LOW
register values. The CDC ambient level is defined as the
capacitance sensor output level during periods when the user is
not approaching or in contact with the sensor.

The compensation logic runs automatically on every conversion
after configuration when the AD7142 is not being touched. This
allows the AD7142 to account for rapidly changing environ-
mental conditions.

The ambient compensation control registers give the host access
to general setup and controls for the compensation algorithm.
The RAM stores the compensation data for each conversion
stage, as well as setup information specific to each stage.

Figure 23 shows an example of an ideal capacitance sensor
behavior where the CDC ambient level remains constant
regardless of the environmental conditions. In this example, the
initial settings programmed in the STAGE_OFFSET_HIGH and
STAGE_OFFSET_LOW registers are sufficient to detect a
sensor contact resulting with the AD7142 asserting the INT
output when the offset levels are exceeded.

STAGE_OFFSET_HIGH
(INITIAL REGISTER VALUE)

CDC OUT

CODES

STAGE_OFFSET_LOW
(INITIAL REGISTER VALUE)

CDC AMBIENT VALUE

SENSOR 1 INT

ASSERTED

SENSOR 2 INT

ASSERTED

CHANGING ENVIRONMENTALCONDITIONS

05702-

022

Figure 23. Ideal Sensor Behavior with a Constant Ambient Level

Capacitance Sensor Behavior Without Calibration

Figure 24 shows the typical behavior of a capacitance sensor
with no applied calibration. This figure shows ambient levels
drifting over time as environmental conditions change. The
ambient level drift has resulted in the detection of a missed user
contact on Sensor 2. This is a result of the initial low offset level
remaining constant while the ambient levels drifted upward
beyond the detection range. The Capacitance Sensor Behavior
with Calibration section describes how the AD7142 adaptive

calibration algorithm prevents errors such as this from
occurring.

CDC O

UTPUT CO

DES

CDC AMBIENT
VALUE DRIFTING

SENSOR 1 INT

ASSERTED

SENSOR 2 INT

NOT ASSERTED

CHANGING ENVIRONMENTALCONDITIONS

STAGE_OFFSET_HIGH
(INITIAL REGISTER VALUE)

STAGE_OFFSET_LOW
(INITIAL REGISTER VALUE)

05702-

023

Figure 24. Typical Sensor Behavior without Calibration Applied

Capacitance Sensor Behavior with Calibration

The AD7142 on-chip adaptive calibration algorithm prevents
sensor detection errors such the one shown in Figure 24. This is
achieved by monitoring the CDC ambient levels and internally
adjusting the initial offset level register values according to the
amount of ambient drift measured on each sensor. This closed
loop routine ensures the reliability and repeatability operation
of every sensor connected to the AD7142 under dynamic
environmental conditions. Figure 25 shows a simplified
example of how the AD7142 applies the adaptive calibration
process resulting in no interrupt errors under changing CDC
ambient levels due to environmental conditions.

PUT

CODE

CDC AMBIENT
VALUE DRIFTING

SENSOR 1 INT

ASSERTED

SENSOR 2 INT

ASSERTED

NOTES

1. INITIAL STAGE_OFFSET_HIGH REGISTER VALUE

2. POST CALIBRATED REGISTER STAGE_OFFSET_HIGH VALUE

3. POST CALIBRATED REGISTER STAGE_OFFSET_HIGH VALUE

4. INITIAL STAGE_OFFSET_LOW REGISTER VALUE

5. POST CALIBRATED REGISTER STAGE_OFFSET_LOW VALUE

6. POST CALIBRATED REGISTER STAGE_OFFSET_LOW VALUE

CHANGING ENVIRONMENTALCONDITIONS

STAGE_OFFSET_HIGH
(POST CALIBRATED
REGISTER VALUE)

STAGE_OFFSET_LOW
(POST CALIBRATED
REGISTER VALUE)

05702-024

Figure 25. Typical Sensor Behavior with

Calibration Applied on the Data Path

AD7142/AD7142-1

Preliminary Technical Data

Rev. PrD | Page 20 of 64

ADAPTIVE THRESHOLD AND SENSITIVITY

The AD7142 provides an on-chip self-learning adaptive
threshold and sensitivity algorithm. This algorithm continu-
ously monitors the output levels of each sensor and automatically
rescales the threshold levels proportionally to the sensor area
covered by the user. As a result, the AD7142 maintains optimal
threshold and sensitivity levels for all types of users regardless
of their finger sizes.

The threshold level is always referenced from the ambient level
and is defined as the CDC converter output level that must be
exceeded for a valid sensor contact. The sensitivity level is
defined as how sensitive the sensor is before a valid contact is
registered.

Figure 26 provides an example of how the adaptive threshold
and sensitivity algorithm works. In a case where the adaptive
threshold and sensitivity algorithm are disabled, the positive
and negative sensor threshold levels are set by the

STAGE_OFFSET_HIGH and STAGE_OFFSET_LOW initial
values. Reference A in Figure 26 shows that this results in an under
sensitive threshold level for a small finger user, demonstrating the
disadvantages of a fixed threshold level. By enabling the adaptive
threshold and sensitivity algorithm, the positive and negative
threshold levels are determined by the POS_THRESHOLD_SENSI
TIVITY and NEG_THRESHOLD_SENSITIVITY register values
and the most recent average maximum sensor output value.
These registers can be used to select 16 different positive and
negative sensitivity levels ranging between 25% and 95.32% of
the most recent average maximum output level referenced from
the ambient value. Reference B shows that the positive adaptive
threshold level is set at almost mid sensitivity with a 62.51%
threshold level by setting POS_THRESHOLD_SENSITIVITY =
1000. Figure 26 also provides a similar example for the negative
threshold level with NEG_THRESHOLD_SENSITIVITY = 0001.

AMBIENT LEVEL

CDC O

UTP

UT CO

AVERAGE MAX VALUE

STAGE_OFFSET_HIGH
(INITIAL VALUE)

25%

95.32%

62.51% = POS ADAPTIVE THRESHOLD LEVEL

25%

62.51% = POS ADAPTIVE THRESHOLD LEVEL

95.32%

NEG ADAPTIVE THRESHOLD LEVEL = 39.08%

25%

95.32%

25%

95.32%

SENSOR CONTACTED

BY SMALL FINGER

AVERAGE MAX VALUE

STAGE_OFFSET_LOW
(INITIAL VALUE)

NEG ADAPTIVE THRESHOLD LEVEL = 39.08%

SENSOR CONTACTED

BY LARGE FINGER

05702-025

Figure 26. Threshold Sensitivity Example with POS_THRESHOLD_SENSITIVITY = 1000 and NEG_THRESHOLD_SENSITIVITY = 0011

Preliminary Technical Data

AD7142/AD7142-1

Rev. PrD | Page 21 of 64

INTERRUPT OUTPUT

The AD7142 has an interrupt output that triggers an interrupt
service routine on the host processor. The INT signal is on
Pin 25, and is an open-drain output. There are three types of
interrupt events on the AD7142: a CDC conversion complete
interrupt, a sensor threshold interrupt, and a GPIO interrupt.
Each interrupt has enable and status registers. The conversion
complete and sensor threshold interrupts can be enabled on a
per conversion stage basis. The status registers indicate what
type of interrupt triggered the INT pin. Status registers are
cleared, and the INT signal is reset high, during a read
operation. The signal returns high as soon as the read address
has been set up.

CDC CONVERSION COMPLETE INTERRUPT

The AD7142 interrupt signal asserts low to indicate the
completion of a conversion stage, and new conversion result
data is available in the registers.

The interrupt can be independently enabled for each conversion
stage. Each conversion stage complete interrupt can be enabled
via the CDC Conversion Completion register (Address 0x007).
This register has a bit that corresponds to each conversion stage.
Setting this bit to 1 enables the interrupt for that stage. Clearing
this bit to 0 disables the conversion complete interrupt for that
stage.

In normal operation, the AD7142 is set up to interrupt enable
the last stage only in a conversion sequence. For example, if
there are five conversion stages, the conversion complete
interrupt for STAGE4 is enabled. INT only asserts when all five
conversion stages are complete, and the host can read new data
from all five result registers. The interrupt is cleared by reading
the status register.

Register 0x00A is the conversion completion status register.
Each bit in this register corresponds to a conversion stage. If a
bit is set, it means that the conversion complete interrupt for the
corresponding stage was triggered. This register is cleared on a
read, provided the underlying condition that triggered the
interrupt has gone away. (For a detailed register description, see
Table 24.)

SENSOR THRESHOLD INTERRUPT

The AD7142 interrupt signal asserts low to indicate that a
conversion result exceeds either the high or low threshold limits
for that sensor. When a conversion result from a sensor exceeds
the threshold limits, it indicates the sensor has been touched.

The sensor threshold interrupt can be enabled independently
for each conversion stage via the interrupt configuration regis-
ters. Register 0x05 is the low threshold interrupt enable register.
Each bit in the register corresponds to the threshold low interrupt
for conversion STAGE0 to STAGE11. Register 0x006 is the high
threshold enable register. Each bit in this register, corresponds
to the high threshold interrupt enable for conversion STAGE0 to
STAGE11. Setting a bit to 1 enables the interrupt for that stage.
Clearing a bit to 0 disables the interrupt for that stage.

When a conversion result exceeds a low threshold, the status bit
corresponding to that conversion stage is set in the CDC low
limit status register at Address 0x008. (For a detailed register
description, see Table 22.) If a conversion stage result exceeds a
high limit, the status bit corresponding to that stage is set in the
CDC high limit status register at Address 0x009. (For a detailed
register description, see Table 23.) All bits in the status registers
are cleared on read back, if all conversion results are within the
threshold limits.

STAGE 0

CONV_FP

STAGE 1

STAGE 2

STAGE 4

STAGE 5

STAGE 6

STAGE 8

STAGE 9

STAGE 1 0

STAGE 7

STAGE 11

STAGE 3

INT

CONVERSIONS

SERIAL

READS

PROGRAMMINGE NOTES
1. STAGE0_SENSOR_HIGH_INT = STAGE0_SENSOR_LOW_INT = 0, STAGE0_CONVERSION_INT = 1
2. READ-BACK FROM STAGE0_CONVERSION REGISTER TO RESET INT OUTPUT
3. STAGE5_SENSOR_HIGH_INT = STAGE5_SENSOR_LOW_INT = 0, STAGE5_CONVERSION_INT = 1
4. READ-BACK FROM STAGE5_CONVERSION REGISTER TO RESET INT OUTPUT
5. STAGE9_SENSOR_HIGH_INT = STAGE9_SENSOR_LOW_INT = 0, STAGE9_CONVERSION_INT = 1
6. READ-BACK FROM STAGE9_CONVERSION REGISTER TO RESET INT OUTPUT

STAGEx_SENSOR_HIGH_INT = STAGEx_SENSOR_LOW_INT = STAGEx_CONVERSION_INT = 0 FOR ALL STAGES HIGHLIGHTED IN GRAY

05702-

026

Figure 27. Example of Configuring the Registers for End of Conversion Interrupt Set Up

AD7142/AD7142-1

Preliminary Technical Data

Rev. PrD | Page 22 of 64

STAGE 0

CONV_FP

STAGE 1

STAGE 2

STAGE 4

STAGE 5

STAGE 6

STAGE 8

STAGE 9

STAGE 10

STAGE 7

STAGE 11

STAGE 3

INT

CONVERSIONS

SERIAL

READS

NOTES
THIS EXAMPLE ASSUMES THAT SENSOR CONTACT FOR STAGE0 EXCEEDED THE HIGH THRESHOLD LIMIT
THIS EXAMPLE ASSUMES THAT SENSOR CONTACT FOR STAGE9 EXCEEDED THE LOW THRESHOLD LIMIT

PROGRAMMING NOTES
1. STAGE0_SENSOR_HIGH_INT = 1, STAGE0_SENSOR_LOW_INT = STAGE0_CONVERSION_INT = 0
2. READ-BACK FROM STAGE0_HIGH_LIMIT REGISTER TO RESET INT OUTPUT
3. STAGE9_SENSOR_HIGH_INT = 0, STAGE5_SENSOR_LOW_INT = 1, STAGE5_CONVERSION_INT = 0
4. READ-BACK FROM STAGE0_LOW_LIMIT REGISTER TO RESET INT OUTPUT

STAGEx_SENSOR_HIGH_INT = STAGEx_SENSOR_LOW_INT = STAGEx_CONVERSION_INT = 0 FOR ALL STAGES HIGHLIGHTED IN GRAY

05702-

027

Figure 28. Example of Configuring the Registers for Sensor Interrupt Set Up

Table 11. GPIO Interrupt Behavior

GPIO_INPUT_CONFIG

GPIO Pin

GPIO_STATUS

INT

INT Behavior

00 = negative level triggered

Not triggered

00 = negative level triggered

Asserted while signal on GPIO pin is low

01 = positive edge triggered

Pulses low at low to high GPIO transition

01 = positive edge triggered

Not triggered

10 = negative edge triggered

Pulses low at high to low GPIO transition

10 = negative edge triggered

Not triggered

11 = positive level triggered

Asserted while signal on GPIO pin is high

11 = positive level triggered

Not triggered

GPIO INT OUTPUT CONTROL

The INT output signal can be controlled by the GPIO pin when
the GPIO is configured as an input. The GPIO is configured as
an input by setting the GPIO_SETUP bits in the interrupt
configuration register to 01. See GPIO section for more
information on how to configure the GPIO.

Enable the GPIO interrupt by setting the GPIO_INT_EN bit in
Register 0x007 to 1, or disable by clearing this bit to 0. The
GPIO status bit in the CDC conversion completion register
reflects the status of the GPIO interrupt. This bit is set to 1
when the GPIO has triggered INT. The bit is cleared on read

back from the register, provided the condition that caused the
interrupt has gone away.

The GPIO interrupt can be set to trigger on a rising edge, falling
edge, high level, or low level at the GPIO input pin. Table 11
shows how the settings of the GPIO_INPUT_CONFIG bits in
the interrupt configuration register affect the behavior of INT.

Figure 29 to Figure 32 show how the interrupt output is cleared
on a read from the CDC conversion completion register.

Preliminary Technical Data

AD7142/AD7142-1

Rev. PrD | Page 23 of 64

GPIO

INPUT

INT

OUTPUT

SERIAL

READ

GPIO

INPUT

INT

OUTPUT

NOTES
1. READ GPIO_STATUS REGISTER TO RESET INT OUTPUT

GPIO INPUT HIGH WHEN REGISTER IS READBACK

GPIO INPUT LOW WHEN REGISTER IS READBACK

05702-028

Figure 29. INT Output Controlled by the GPIO Input Example,

GPIO_SETUP = 01, GPIO_INPUT_CONFIG = 00

GPIO

INPUT

INT

OUTPUT

SERIAL

READ BACK

GPIO

INPUT

INT

OUTPUT

GPIO INPUT HIGH WHEN REGISTER IS READBACK

GPIO INPUT LOW WHEN REGISTER IS READBACK

NOTES
1. READ GPIO_STATUS REGISTER TO RESET INT OUTPUT

05702-029

Figure 30. INT Output Controlled by the GPIO Input Example,

GPIO_SETUP = 01, GPIO_INPUT_CONFIG = 01

GPIO

INPUT

INT

OUTPUT

SERIAL

READ BACK

GPIO

INPUT

INT

OUTPUT

GPIO INPUT LOW WHEN REGISTER IS READBACK

GPIO INPUT HIGH WHEN REGISTER IS READBACK

NOTES
1. READ GPIO_STATUS REGISTER TO RESET INT OUTPUT

05702-030

Figure 31. INT Output Controlled by the GPIO Input Example,

GPIO_SETUP = 01, GPIO_INPUT_CONFIG = 10

GPIO

INPUT

INT

OUTPUT

SERIAL

READ BACK

GPIO

INPUT

INT

OUTPUT

GPIO INPUT LOW WHEN REGISTER IS READBACK

GPIO INPUT HIGH WHEN REGISTER IS READBACK

NOTES
1. READ GPIO_STATUS REGISTER TO RESET INT OUTPUT

05702-031

Figure 32. INT Output Controlled by the GPIO Input Example,

GPIO_SETUP = 01, GPIO_INPUT_CONFIG = 11

AD7142/AD7142-1

Preliminary Technical Data

Rev. PrD | Page 24 of 64

OUTPUTS

EXCITATION SOURCE

The excitation source on board the AD7142 is as square wave
source with a frequency of 240 kHz. This excitation source
forms the capacitance field between the transmitter and receiver
in the external capacitance sensor PCB. The source is output
from the AD7142 on two pins, the SRC pin and the SRC pin
(outputs an inverted version of the source square wave). The
SRC signal offsets large external sensor capacitances. In current
applications, SRC is not used.

The source output can be disabled from both output pins
separately by writing to the control register (Address 0x000).
Setting Bit 12 in this register to 1 disables the source output on
the SRC pin. Setting Bit 13 in this register to 1 disables the
inverted source output on the SRC pin.

SHIELD

OUTPUT

To prevent leakage from the external capacitance sensors, the
sensor traces are shielded. The AD7142 has a voltage output
that can be used as the potential for any shield traces, C

SHIELD

The C

SHIELD

voltage is equal to V

/2.

The C

SHIELD

potential is derived from the output of the AD7142

internal amplifier, and is of equal potential to the CIN input
lines. Because the shield is at the same potential as the sensor
traces, no leakage to ground occurs.

To eliminate any ringing on the C

SHIELD

output, connect a 10 nF

capacitor between the C

SHIELD

pin and ground.

SHIELD

is connected to layer three on a four-layer sensor PCB to

provide shielding for the sensors. On a two-layer PCB construc-
tion, C

SHIELD

is used in place of a ground plane around the

sensors, on both layers of the PCB.

Figure 33 shows how the sensor traces are shielded by running
traces connected to the shield potential around the sensor traces.

I
EL

10nF

AD7142

Figure 33. Shielding the Sensor Traces

GPIO

The AD7142 has one GPIO pin, Pin 26. It can be configured as an
input or an output. The GPIO_SETUP bits in the interrupt
configuration register determine how the GPIO pin is configured.

Table 12. GPIO_SETUP Bits

GPIO_SETUP GPIO

Configuration

00 GPIO

disabled

01 Input
10 Output

low

11 Output

high

When the GPIO is configured as an output, the voltage level on
the pin is set to either a low level or a high level, as defined by
the GPIO_SETUP bits, shown in Table 12.

When the GPIO is configured as an input, the
GPIO_INPUT_CONFIGURATON bits in the interrupt
configuration register determine the response of the AD7142 to
a signal on the GPIO pin. The GPIO can be configured as either
active high or active low, as well as either edge triggered or level
triggered, as listed in Table 13.

Table 13. GPIO_INPUT_CONFIGURATION Bits

GPIO_INPUT_CONFIGURATION GPIO

Configuration

Triggered on negative level
(active low)

Triggered on positive edge
(active high)

Triggered on negative edge
(active low)

Triggered on positive level
(active high)

When GPIO is configured as an input, it triggers the interrupt
output on the AD7142. Table 11 lists the interrupt output
behavior for each of the GPIO configuration setups.

Preliminary Technical Data

AD7142/AD7142-1

Rev. PrD | Page 25 of 64

SERIAL INTERFACE

The AD7142 is available with an SPI serial interface. The
AD7142-1 is available with an I

C interface. Both parts are

exactly the same, with the exception of the serial interface.

SPI INTERFACE

The AD7142 has a 4-wire serial peripheral interface (SPI). The
SPI has a data input pin (SDI) for inputting data to the device, a
data output pin (SDO) for reading data back from the device,
and a data clock pin (SCLK) for clocking data into and out of
the device. A chip select pin (CS) enables or disables the serial
interface. CS is required for correct operation of the SPI
interface. Data is clocked out of the AD7142 on the negative
edge of SCLK, and data is clocked into the device on the
positive edge of SCLK.

SPI Command Word

All data transactions on the SPI bus begin with the master
taking CS low and sending out the command word. This
indicates to the AD7142 whether the transaction is a read or a
write, and gives the address of the register from which to begin
the data transfer.

Table 14. SPI Command Word

15 10

1 1 1 0 0 R/W

Bits[15:11] of the command word must be set to 11100 to
successfully begin a bus transaction.

Bit 10 is the read/write bit; 1 indicates a read, and 0 indicates a
write.

Bits[9:0] contain the target register address. When reading or
writing to more than one register, this address indicates the
address of the first register to be written to or read from.

Writing Data

Data is written to the AD7142 in 16-bit words. The first word
written to the device is the command word, with the read/write
bit set to 0. The master then supplies the 16-bit input data-word
on the SDI line. The AD7142 clocks the data into the register
addressed in the command word. If there is more than one
word of data to be clocked in, the AD7142 automatically incre-
ments the address pointer, and clock the next data-word into
the next register.

The AD7142 continues to clock in data on the SDI line until
either the master finishes the write transition by pulling CS
high, or until the address pointer reaches its maximum value.
The AD7142 address pointer does not wrap around. When it
reaches its maximum value, any data provided by the master on
the SDI line is ignored by the AD7142.

NOTES
1. SDI BITS ARE LATCHED ON SCLK RISING EDGES. SCLK MAY IDLE HIGH OR LOW BETWEEN WRITE OPERATIONS.
2. ALL 32 BITS MUST BE WRITTEN: 16 BITS FOR CONTROL WORD AND 16 BITS FOR DATA.
3. 16-BIT COMMAND WORD SETTINGS FOR SERIAL WRITE OPERATION:
CW[15:11] = 11100 (ENABLE WORD)
CW[10] = 0 (R/W)
CW[9:0] = [AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0] (10-BIT MSB JUSTIFIED REGISTER ADDRESS)

SDI

16-BIT COMMAND WORD

16-BIT DATA

SCLK

D15

D14

D13

ENABLE WORD

R/W

REGISTER ADDRESS

05702-

033

Figure 34. Single Register Write SPI Timing

AD7142/AD7142-1

Preliminary Technical Data

Rev. PrD | Page 26 of 64

SDI

D15

D14

SCLK

NOTES
1. MULTIPLE SEQUENTIAL REGISTERS MAY BE LOADED CONTINUOUSLY.
2. THE FIRST (LOWEST ADDRESS) REGISTER ADDRESS IS WRITTEN, FOLLOWED BY MULTIPLE 16-BIT DATA-WORDS.
3. THE ADDRESS WILL AUTOMATICALLY INCREMENT WITH EACH 16-BIT DATA-WORD (ALL 16 BITS MUST BE WRITTEN).
4. CS IS HELD LOW UNTIL THE LAST DESIRED REGISTER HAS BEEN LOADED.
5. 16-BIT COMMAND WORD SETTINGS FOR SEQUENTIAL WRITE OPERATION:
CW[15:11] = 11100 (ENABLE WORD)
CW[10] = 0 (R/W)
CW[9:0] = [AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0] (ST

ARTING MSB JUSTIFIED REG IST ER ADDRESS

)

D15

DATA FOR STARTING

REGISTER ADDRESS

DATA FOR NEXT

REGISTER ADDRESS

D15

D14

16-BIT COMMAND WORD

ENABLE WORD

R/W

STARTING REGISTER ADDRESS

05702-

034

Figure 35. Sequential Register Write SPI Timing

NOTES
1. SDI BITS ARE LATCHED ON SCLK RISING EDGES. SCLK MAY IDLE HIGH OR LOW BETWEEN WRITE OPERATIONS.
2. THE 16-BIT CONTROL WORD MUST BE WRITTEN ON SDI: 5-BITS FOR ENABLE WORD, 1 BIT FOR R/W AND 10-BITS FOR REGISTER ADDRESS.
3. THE REGISTER DATA WILL BE READ BACK ON THE SDO PIN.
4. X DENOTES DON'T CARE.
5. XXX DENOTES HIGH IMPEDANCE TRISTATE OUTPUT.
6. CS IS HELD LOW UNTIL ALL REGISTER BITS HAVE BEEN READ BACK.
7. 16-BIT COMMAND WORD SETTINGS FOR SINGLE READ-BACK OPERATION:
CW[15:11] = 11100 (ENABLE WORD)
CW[10] = 1 (R/W)
CW[9:0] = AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 (10-BIT MSB JUSTIFIED REGISTER ADDRESS)

SDI

16-BIT READ BACK DATA

SCLK

XXX

SDO

XXX

D15

D14

D13

XXX

16-BIT COMMAND WORD

ENABLE WORD

R/W

REGISTER ADDRESS

05702-

035

Figure 36. Single Register Readback SPI Timing

Reading Data

A read transaction begins when the master writes the command
word to the AD7142 with the read/write bit set to 1. The master
then supplies 16 clock pulses per data-word to be read, and the
AD7142 clocks out data from the addressed register on the SDO
line. The first data-word is clocked out on the first falling edge
of CS following the command word, as shown in Figure 36.

The AD7142 continues to clock out data on the SDO line
provided the master continues to supply the clock signal on
SCLK. The read transaction finishes when the master takes
CS high. If the AD7142 address pointer reaches its maximum
value, then the AD7142 repeatedly clocks out data from the
addressed register. The address pointer does not wrap around.

Preliminary Technical Data

AD7142/AD7142-1

Rev. PrD | Page 27 of 64

SDI

SCLK

READ BACK DATA FOR

STARTING REGISTER ADDRESS

READ BACK DATA FOR

NEXT REGISTER ADDRESS

XXX XXX XXX

XXX D15 D14

D15

D14

XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX

SDO

16-BIT COMMAND WORD

ENABLE WORD

R/W

REGISTER ADDRESS

NOTES
1. MULTIPLE REGISTERS MAY BE READ BACK CONTINUOUSLY.
2. THE 16-BIT CONTROL WORD MUST BE WRITTEN ON SDI: 5-BITS FOR ENABLE WORD, 1 BIT FOR R/W AND 10-BITS FOR REGISTER ADDRESS.
3. THE ADDRESS WILL AUTOMATICALLY INCREMENT WITH EACH 16-BIT DATA-WORD BEING READ BACK ON THE SDO PIN.
4. CS IS HELD LOW UNTIL ALL REGISTER BITS HAVE BEEN READ BACK.
5. X DENOTES DON'T CARE.
6. XXX DENOTES HIGH IMPEDANCE TRISTATE OUTPUT.
7. 16-BIT COMMAND WORD SETTINGS FOR SEQUENTIAL READ-BACK OPERATION:
CW[15:11] = 11100 (ENABLE WORD)
CW[10] = 1 (R/W)
CW[9:0] = AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 (STARTING MSB JUSTIFIED REGISTER ADDRESS)

05702-

036

Figure 37. Sequential Register Readback SPI Timing

C INTERFACE

The AD7142-1 supports the JEDEC industry standard 2-wire
I

C serial interface protocol. The two wires associated with the

C timing are the SCLK and the SDA inputs. The SDA is an

I/O pin that allows both register write and register readback
operations. The AD7142-1 is always a slave device on the I

serial interface bus.

It has a 7-bit device address, Address 0101 1XX. The lower two
bits are set by tying the Add0 and Add1 pins high or low. The
AD7142-1 responds when the master device sends its device
address over the bus. The AD7142-1 cannot initiate data
transfers on the bus.

Table 15.AD7142-1 I

C Device Address

ADD1 ADD0 I

C Address

0 0 0101

100

0 1 0101

101

1 0 0101

110

1 1 0101

111

Data Transfer

Data is transferred over the I

C serial interface in 8-bit bytes.

The master initiates a data transfer by establishing a start con-
dition, defined as a high-to-low transition on the serial data
line, SDA, while the serial clock line, SCLK, remains high.
This indicates that an address/data stream follows.

All slave peripherals connected to the serial bus respond to
the start condition and shift in the next eight bits,
consisting of a 7-bit address (MSB first) plus an R/W bit
that determines the direction of the data transfer. The
peripheral whose address corresponds to the transmitted
address responds by pulling the data line low during the
ninth clock pulse. This is known as the acknowledge bit.
All other devices on the bus now remain idle while the
selected device waits for data to be read from, or written to
it. If the R/W bit is a zero, the master writes to the slave
device. If the R/W bit is a one, the master reads from the
slave device.

Data is sent over the serial bus in a sequence of nine clock
pulses, eight bits of data followed by an acknowledge bit
from the slave device. Transitions on the data line must
occur during the low period of the clock signal and remain
stable during the high period, since a low-to-high transition
when the clock is high can be interpreted as a stop signal.
The number of data bytes transmitted over the serial bus in a
single read or write operation is limited only by what the
master and slave devices can handle.

When all data bytes are read or written, a stop condition is
established. A stop condition is defined by a low-to-high
transition on SDA while SCLK remains high. If the AD7142
encounters a stop condition, it returns to its idle condition,
and the address pointer resets to Address 0x00.

AD7142/AD7142-1

Preliminary Technical Data

Rev. PrD | Page 28 of 64

NOTES
1. A START CONDITION AT THE BEGINNING IS DEFINED AS A HIGH TO LOW TRANSITION ON SDA WHILE SCLK REMAINS HIGH.
2. A STOP CONDITION AT THE END IS DEFINED AS A LOW TO HIGH TRANSITION ON SDA WHILE SCLK REMAINS HIGH.
3. 7-BIT DEVICE ADDRESS [DEV A6:DEV A0] = [0 1 0 1 1 X X], WHERE X ARE DON'T CARES.
4. 16-BIT REGISTER ADDRESS[A15:A0] = [X X X X X X A9 A8 A7 A6 A5 A4 A3 A2 A1 A0], WHERE X ARE DON'T CARES.
5. REGISTER ADDRESS [A15:A8] AND REGISTER ADDRESS [A7:A0] ARE AWAYS SEPERATED BY A LOW ACK BIT.
6. REGISTER DATA [D15:D8] AND REGISTER DATA [D7:D0] ARE ALWAYS SEPERATED BY A LOW ACK BIT.

SDA

DEV

R/W

SCLK

DEV

ACK

A15

A14

START

AD7142 DEVICE ADDRESS

REGISTER ADDRESS[A15:A8]

REGISTER ADDRESS[A7:A0]

ACK

D15

D14

REGISTER DATA[D15:D8]

REGISTER DATA[D7:D0]

ACK

STOP

DEV

START

AD7142 DEVICE ADDRESS

05702-037

Figure 38. Example of I

C Timing for Single Register Write Operation

Writing Data over the I

C Bus

The process for writing to the AD7142-1 over the I

C bus is

shown in Figure 38 and Figure 40. The device address is sent
over the bus followed by the R/W bit set to 0. This is followed
by two bytes of data that contain the 10-bit address of the
internal data register to be written. The upper and lower register
address bytes are shown in Table 16. Note that Bit 7 to Bit 2 in
the upper address byte are don't cares. The address is contained
in the 10 LSBs of the register address bytes.

Table 16. AD7142-1 Internal Register I

C Addressing:

Register Address Upper Byte

7 6 5 4 3 2 1

X X X X X X Register

Address
Bit 9

Table 17. AD7142-1 Internal Register I

C Addressing:

Register Address Lower Byte

7 6 5 4 3 2 1 0

Reg
Add

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

The third data byte contains the eight MSBs of the data to be
written to the internal register. The fourth byte of data contains
the eight LSBs of data to be written to the internal register.

The AD7142-1 address pointer register automatically increments
after each write. This allows the master to sequentially write to all
registers on the AD7142-1 in the same write transaction. However,
the address pointer does not wrap around after the last address.

Any data written to the AD7142-1 after the address pointer has
reached its maximum value is discarded.

All registers on the AD7142-1 are 16-bit. Two consecutive 8-bit
data bytes are combined and written to the 16-bit registers. To
avoid errors, all writes to the device must contain an even
number of data bytes.

To finish the transaction, the master generates a stop condition
on SDO, or generates a repeat start condition if the master is to
maintain control of the bus.

Reading Data over the I

C Bus

To read from the AD7142-1, the address pointer must first be
set to the address of the required internal register. The master
performs a write transaction, and writes to the AD7142-1 to set
the address pointer. The master then outputs a repeat start
condition to keep control of the bus, or if this is not possible,
ends the write transaction with a stop condition. A read
transaction is initiated, with the R/W bit set to 1.

The AD7142-1 supplies the upper eight bits of data from the
addressed register in the first readback byte, followed by the
lower eight bits in the next byte. This is shown in Figure 39 and
Figure 40.

Because the address pointer automatically increases after each
read, the AD7142-1 continues to output readback data until the
master puts a no acknowledge and stop condition on the bus. If
the address pointer reaches its maximum value, and the master
continues to read from the part, the AD7142-1 repeatedly sends
data from the last register addressed.

Preliminary Technical Data

AD7142/AD7142-1

Rev. PrD | Page 29 of 64

NOTES

1. A START CONDITION AT THE BEGINNING IS DEFINED AS A HIGH TO LOW TRANSITION ON SDA WHILE SCLK REMAINS HIGH.
2. A STOP CONDITION AT THE END IS DEFINED AS A LOW TO HIGH TRANSITION ON SDA WHILE SCLK REMAINS HIGH.
3. THE MASTER GENERATES THE NACK AT THE END OF THE READBACK TO SIGNAL THAT IT DOES NOT WNAT ADDITIONAL DATA.
4. 7-BIT DEVICE ADDRESS [DEV A6:DEV A0] = [0 1 0 1 1 X X], WHERE THE TWO LSB X's ARE DON'T CARES.
5. 16-BIT REGISTER ADDRESS[A15:A0] = [X X X X X X A9 A8 A7 A6 A5 A4 A3 A2 A1 A0], WHERE THE UPPER LSB X 's ARE DON'T CARES.
6. REGISTER ADDRESS [A15:A8] AND REGISTER ADDRESS [A7:A0] ARE AWAYS SEPERATED BY A LOW ACK BIT.
7. REGISTER DATA [D15:D8] AND REGISTER DATA [D7:D0] ARE ALWAYS SEPERATED BY A LOW ACK BIT.
8. THE R/W BIT IS SET TO A "1" TO INDICATE A READBACK OPERATION.

SDA

DEV

R/W

SCLK

DEV

ACK

A15

A14

START

AD7142 DEVICE ADDRESS

REGISTER ADDRESS[A15:A8]

REGISTER ADDRESS[A7:A0]

ACK

REGISTER DATA[D7:D0]

ACK

NACK

DEV

AD7142 DEVICE ADDRESS

ACK

AD7142 DEVICE ADDRESS

DEV

05702-

038

R/W

REGISTER DATA[D7:D0]

ACK

NACK

AD7142 DEVICE ADDRESS

DEV

R/W

USING

REPEATED START

SEPERATE READ AND

WRITE TRANSACTIONS

Figure 39. Example of I

C Timing for Single Register Readback Operation

ACK

WRITE

OUTPUT FROM MASTER

OUTPUT FROM AD7142

ACK

6-BIT DEVICE

ADDRESS

S = START BIT
P = STOP BIT
SR = REPEATED START BIT

ACK = ACKNOWLEDGE BIT
NACK = ACKNOWLEDGE BIT

REGISTER ADDR

[15:8]

REGISTER ADDR

[7:0]

WRITE DATA

HIGH BYTE [15:8]

WRITE DATA

LOW BYTE [7:0]

WRITE DATA

HIGH BYTE [15:8]

WRITE DATA

LOW BYTE [7:0]

ACK

NACK

READ DATA

HIGH BYTE [15:8]

READ DATA

LOW BYTE [7:0]

ACK

READ (USING REPEATED START)

ACK

6-BIT DEVICE

ADDRESS

REGISTER ADDR

HIGH BYTE

REGISTER ADDR

LOW BYTE

6-BIT DEVICE

ADDRESS

READ DATA

HIGH BYTE [15:8]

ACK

READ DATA

LOW BYTE [7:0]

05702-039

ACK

NACK

READ DATA

HIGH BYTE [15:8]

READ DATA

LOW BYTE [7:0]

ACK

READ (WRITE TRANSACITON SETS UP REGISTER ADDRESS)

ACK

6-BIT DEVICE

ADDRESS

REGISTER ADDR

HIGH BYTE

REGISTER ADDR

LOW BYTE

6-BIT DEVICE

ADDRESS

READ DATA

HIGH BYTE [15:8]

ACK

READ DATA

LOW BYTE [7:0]

Figure 40. Example of Sequential I

C Write and Readback Operation

DRIVE

INPUT

The supply voltage to all pins associated with both the I

C and

SPI serial interfaces (SDO, SDI, SCLK, SDA, and CS) is separate
from the main V

supply and is connected to the V

DRIVE

pin.

This allows the AD7142 to be connected directly to processors
whose supply voltage is less than the minimum operating
voltage of the AD7142 without the need for external level-
shifters. The V

DRIVE

pin can be connected to voltage supplies as

low as 1.6 V and as high as V

AD7142/AD7142-1

Preliminary Technical Data

Rev. PrD | Page 30 of 64

PCB DESIGN GUIDELINES

CAPACITIVE SENSOR BOARD MECHANICAL SPECIFICATIONS

Table 18.

Parameter

Symbol

Min

Typ

Max

Unit

Distance from Edge of Any Sensor to Edge of Metal Object

1.0

Distance Between Sensor Edges

= D

0 mm

Distance Between Bottom of Sensor Board and Controller Board or Metal
Casing

(4-Layer, 2-Layer And Flex Circuit)

1.0

The distance is dependent on the application and the positioning of the switches relative to each other and with respect to the user's finger positioning and handling.

Adjacent sensors, with 0 minimum space between them, are implemented differentially.

The 1.0 mm specification is meant to prevent any direct sensor board contact with any conductive material. This specification does not guarantee no EMI coupling

from the controller board to the sensors. Address potential EMI coupling issues by placing a grounded metal shield between the capacitive sensor board and the main
controller board as shown in Figure 43.

05702-045

SLIDER

BUTTONS

CAPACITIVE SENSOR

PRINTED CIRCUIT

8-WAY

SWITCH

METAL OBJECT

Figure 41. Capacitive Sensor Board Mechanicals Top View

CAPACITIVE SENSOR BOARD

CONTROLLER PRINTED CIRCUIT BOARD OR METAL CASING

GROUNDED METAL SHIELD

05702-046

Figure 42. Capacitive Sensor Board Mechanicals Side View

CAPACITIVE SENSOR BOARD

CONTROLLER PRINTED CIRCUIT BOARD OR METAL CASING

05702-047

Figure 43. Capacitive Sensor Board with Grounded Shield

CHIP SCALE PACKAGES

The lands on the chip scale package (CP-32-3) are rectangular.
The printed circuit board pad for these should be 0.1 mm
longer than the package land length, and 0.05 mm wider than
the package land width. Center the land on the pad to maximize
the solder joint size.

The bottom of the chip scale package has a central thermal pad.
The thermal pad on the printed circuit board should be at least
as large as this exposed pad. To avoid shorting, provide a
clearance of at least 0.25 mm between the thermal pad and the
inner edges of the land pattern on the printed circuit board.

Thermal vias can be used on the printed circuit board thermal
pad to improve thermal performance of the package. If vias are
used, they should be incorporated in the thermal pad at a
1.2 mm pitch grid. The via diameter should be between 0.3 mm
and 0.33 mm, and the via barrel should be plated with 1 oz.
copper to plug the via.

Connect the printed circuit board thermal pad to GND.

Preliminary Technical Data

AD7142/AD7142-1

Rev. PrD | Page 31 of 64

POWER-UP SEQUENCE

When the AD7142 is powered up, the following sequence is
recommended:

Turn on the power supplies to the AD7142.

Load all of the required Bank 2 configuration registers.

Load Bank 1 registers at Address 0x000 through
Address 0x004 (except Register Address 0x001 Bits[11:0])
and Register Address 0x045 to configure the AD7142.

Load Bank 1 registers at Address 0x005 through
Address 0x007. This enables the interrupt operation.

Set calibration enable bits for each conversion stage,
Register Address 0x001 Bits[11:0]. Wait for three interrupt
cycles. After the third interrupt, valid data is available in
the AD7142 registers.

Read back either the CDC conversion limit or CDC
conversion completion registers to reset the INT output as
explained in the Interrupt Output section.

Repeat Step 5 every time INT is asserted.

POWER

SUPPLIES

SERIAL

WRITES

INT

(OUTPUT)

FIRST CONVERSION

DVCC = AVCC = VDRIVE = 3V

CONV

SECOND CONVERSION

05702-040

Figure 44. Recommended Start-Up Sequence

AD7142/AD7142-1

Preliminary Technical Data

Rev. PrD | Page 32 of 64

TYPICAL APPLICATION CIRCUITS

DRIVE

10k

8-WAY

SWITCH

HOST

WITH

SPI

INTERFACE

SCK

MOSI

MISO

INT

HOST

SEN

YER

BUTTONS

I
D

CIN3

CIN4

CIN5

CIN6

CIN7

CIN8

CIN9

CIN10

CIN2

CIN11

I
E

SRC

INT

SDI

SCLK

DRIVE

DGND1

SDO

DGND2

1.8V

2.7V3.6V

0.1

F10

(OPTIONAL)

AD7142

0
5702

-
0
41

SEN

SOR

10nF

Figure 45. Typical Application Circuit with SPI Interface

DRIVE

10k

HOST

WITH

INTERFACE

SCK

SDO

INT

R P

B L

R 1

CIN3

CIN4

CIN5

CIN6

CIN7

CIN8

CIN9

CIN10

CIN2

CIN11

I
E

SRC

ADD1

INT

ADD0

SCLK

DRIVE

DGND1

SDA

DGND2

EST

GPI

2.7V3.6V

0.1

F10

(OPTIONAL)

AD7142-1

DRIVE

10k

8-WAY

SWITCH

R P

L
AY

SLIDER

T
T

TTO

0
5702-

10nF

Figure 46. Typical Application Circuit with I

C Interface

Preliminary Technical Data

AD7142/AD7142-1

Rev. PrD | Page 33 of 64

The AD7142 address space is divided into three different
register banks, referred to as Register Bank 1, Register Bank 2,
and Register Bank 3. Figure 47 illustrates the division of these
three banks.

Register Bank 1 contains setup and conversion control registers,
interrupt configuration registers, and CDC conversion limit and
completion registers. Register Bank 1 also contains the 16-bit
ADC raw data for all 12 conversion stages and the AD7142
device ID register.

Register Bank 2 contains the conversion stage configuration
registers used for uniquely configuring the CIN inputs for each

conversion stage. Initialize the Bank 2 configuration registers
immediately after power-up to obtain valid CDC conversion
result data.

Register Bank 3 contains the results of each conversion stage.
These registers automatically update at the end of each conversion
sequence. Although these registers are primarily used by the
AD7142 internal data processing, they are accessible by the host
processor for additional external data processing, if desired.

Default values are undefined for Register Bank 2 and Register
Bank 3 until after power up and configuration of Register Bank 2.

REGISTER BANK 1

ADDR 0x000

ADDR 0x018

ADDR 0x001

ADDR 0x005

ADDR 0x008

ADDR 0x00A

ADDR 0x00B

ADDR 0x017

ADDR 0x7F

ADDR 0x7F0

SET UP CONTROL

(1 REGISTER)

CALIBRATION AND SET UP

(4 REGISTERS)

INTERRUPT CONFIGURATION

(3 REGISTERS)

CDC CONVERSION LIMIT

(2 REGISTERS)

CDC CONVERSION COMPLETION

(1 REGISTER)

CDC 16-BIT CONVERSION DATA

(12 REGISTERS)

DEVICE ID REGISTER

INVALID DO NOT ACCESS

2
4
REG

I
ST

REGISTER BANK 2

ADDR 0x080

ADDR 0x0B8

ADDR 0x088

ADDR 0x090

ADDR 0x098

ADDR 0x0A0

ADDR 0x0A8

ADDR 0x0B0

ADDR 0x0C8

ADDR 0x0C0

STAGE 0 CONFIGURATION

(8 REGISTERS)

STAGE 1 CONFIGURATION

(8 REGISTERS)

STAGE 2 CONFIGURATION

(8 REGISTERS)

STAGE 3 CONFIGURATION

(8 REGISTERS)

STAGE 4 CONFIGURATION

(8 REGISTERS)

STAGE 5 CONFIGURATION

(8 REGISTERS)

STAGE 6 CONFIGURATION

(8 REGISTERS)

STAGE 7 CONFIGURATION

(8 REGISTERS)

STAGE 8 CONFIGURATION

(8 REGISTERS)

STAGE 9 CONFIGURATION

(8 REGISTERS)

STAGE 10 CONFIGURATION

(8 REGISTERS)

STAGE 11 CONFIGURATION

(8 REGISTERS)

ADDR 0x0D8

ADDR 0x0D0

9
6
R

I
ST

REGISTER BANK 3

ADDR 0x0E0

ADDR 0x0B8

ADDR 0x088

ADDR 0x090

ADDR 0x098

ADDR 0x0A0

ADDR 0x0A8

ADDR 0x0B0

ADDR 0x0C8

ADDR 0x0C0

STAGE 0 RESULTS

(36 REGISTERS)

ADDR 0x28F

ADDR 0x0D0

2 R

I
S

STAGE 1 RESULTS

(36 REGISTERS)

STAGE 10 RESULTS

(36 REGISTERS)

STAGE 9 RESULTS

(36 REGISTERS)

STAGE 8 RESULTS

(36 REGISTERS)

STAGE 7 RESULTS

(36 REGISTERS)

STAGE 6 RESULTS

(36 REGISTERS)

STAGE 5 RESULTS

(36 REGISTERS)

STAGE 4 RESULTS

(36 REGISTERS)

STAGE 3 RESULTS

(36 REGISTERS)

STAGE 2 RESULTS

(36 REGISTERS)

STAGE 11 RESULTS

(36 REGISTERS)

PROXIMITY STATUS REGISTER

ADDR 0x042

ADDR 0x045

043

INVALID DO NOT ACCESS

INV

INVALID DO NOT ACCESS

LOW POWER MODE

SETTLING TIME REGISTER

Figure 47. Layout of Bank 1, Bank 2, and Bank 3 Registers

AD7142/AD7142-1

Preliminary Technical Data

Rev. PrD | Page 34 of 64

DETAILED REGISTER DESCRIPTIONS

BANK 1 REGISTERS

All addresses and default values are expressed in hexadecimal.
Table 19. Control Register Map

Address

Data Bit
Content

Default
Value

Type

Name

Description

000

[1:0]

R/W

POWER_MODE

Operating Modes

00 = full power mode

(Normal operation, CDC conversions approximately
every 36 ms)

01 = full shutdown mode

(No CDC conversions)

10 = low power mode

(Automatic wake up operation)

11 = Full Shutdown Mode

(No CDC conversions)

[3:2]

LP_CONV_DELAY

Low Power Mode Conversion Delay

00 = 100 ms

01 = 200 ms

10 = 300 ms

11 = 400 ms

[7:4]

SEQUENCE_STAGE_NUM

Number of Stages in Sequence (N + 1)

0000 = 1 conversion stage in sequence

0001 = 2 conversion stages in sequence

......

Maximum value = 1011 = 12 conversion stages per
sequence

[9:8]

DECIMATION

ADC Decimation Factor

00 = decimate by 256

01 = decimate by 128

10 = decimate by 64

11 = decimate by 64

[10]

SW_RESET

Software Reset Control (Self-Clearing)

1 = resets all registers to default values

[11]

INT_POL

Interrupt Polarity Control

0 = active low

1 = active high

[12]

EXCITATION_SOURCE

Excitation Source Control for Pin 15

0 = enable output

1 = disable output

[13]

SRC

Excitation Source Control for Pin 16

0 = enable output

1 = disable output

[15:14]

CDC_BIAS

CDC Bias Current Control

00 = normal operation

01 = normal operation + 20%

10 = normal operation + 35%

11 = normal operation + 50%

Preliminary Technical Data

AD7142/AD7142-1

Rev. PrD | Page 35 of 64

Table 20. CDC Conversion Control Register Map

Address

Data Bit
Content

Default
Value

Type

Name

Description

001

[0]

R/W

STAGE0_CAL_EN

STAGE0 Calibration Enable

0 = disable

1 = enable

[1]

STAGE1_CAL_EN

STAGE1 Calibration Enable

0 = disable

1 = enable

[2]

STAGE2_CAL_EN

STAGE2 Calibration Enable

0 = disable

1 = enable

[3]

STAGE3_CAL_EN

STAGE3 Calibration Enable

0 = disable

1 = enable

[4]

STAGE4_CAL_EN

STAGE4 Calibration Enable

0 = disable

1 = enable

[5]

STAGE5_CAL_EN

STAGE5 Calibration Enable

0 = disable

1 = enable

[6]

STAGE6_CAL_EN

STAGE6 Calibration Enable

0 = disable

1 = enable

[7]

STAGE7_CAL_EN

STAGE7 Calibration Enable

0 = disable

1 = enable

[8]

STAGE8_CAL_EN

STAGE8 Calibration Enable

0 = disable

1 = enable

[9]

STAGE9_CAL_EN

STAGE9 Calibration Enable

0 = disable

1 = enable

[10]

STAGE10_CAL_EN

STAGE10 Calibration Enable

0 = disable

1 = enable

[11]

STAGE11_CAL_EN

STAGE11 Calibration Enable

0 = disable

1 = enable

[13:12]

AVG_FP_SKIP

Full Power Mode Skip Control

00 = skip 3 samples

01 = skip 7 samples

10 = skip 15 samples

11 = skip 31 samples

[15:14]

AVG_LP_SKIP

Low Power Mode Skip Control

00 = use all samples

01 = skip 1 sample

10 = skip 2 samples

11 = skip 3 samples

AD7142/AD7142-1

Preliminary Technical Data

Rev. PrD | Page 36 of 64

Address

Data Bit
Content

Default
Value

Type

Name

Description

002

[3:0]

R/W

FF_SKIP_CNT

Fast Filter Skip Control (N+1)

0000 = 1 conversion skipped in each stage

0001 = 2 conversions skipped in each stage

......

1011 = max value = 12 conversions skipped in each
stage

[7:4]

FP_PROXIMITY_CNT

Full Power Mode Proximity Period

[11:8]

LP_PROXIMITY_CNT

Low Power Mode Proximity Period

[13:12]

PWR_DOWN_TIMEOUT

Power Down Time Out Control

00 = 1.25 × (LP_PROXIMITY_CNT)

01 = 1.50 × (LP_PROXIMITY_CNT)

10 = 1.75 × (LP_PROXIMITY_CNT)

11 = 2.00 × (LP_PROXIMITY_CNT)

[14]

FORCED_CAL

Forced Calibration Control

0 = normal operation

1 = forces all conversion stages to recalibrate

[15]

CONV_RESET

Conversion Reset Control (Self-Clearing)

0 = normal operation

1 = resets the conversion sequence back to STAGE0.

003

[7:0]

R/W

PROXIMITY_RECAL_LVL

Proximity Recalibration Level

[13:8]

PROXIMITY_DETECTION_RATE

Proximity Detection Rate

[15:14]

SLOW_FILTER_UPDATE_LVL

Slow Filter Update Level

004

[9:0]

3FF

R/W

FP_PROXIMITY_RECAL

Full Power Mode Proximity Recalibration Time Control

[15:10]

LP_PROXIMITY_RECAL

Low Power Mode Proximity Recalibration Time Control

Table 21. Interrupt Configuration Register Map

Address

Data Bit
Content

Default
Value

Type

Name

Description

005

[0]

R/W

STAGE0_LOW_INT_EN

STAGE0 Low Interrupt Enable

0 = interrupt source disabled

1 = INT

asserted if STAGE0 low reference is exceeded

[1]

STAGE1_LOW_INT_EN

STAGE1 Low Interrupt Enable

0 = interrupt source disabled

1 = INT asserted if STAGE0 low reference is exceeded

[2]

STAGE2_LOW_INT_EN

STAGE2 Low Interrupt Enable

0 = interrupt source disabled

1 = INT asserted if STAGE0 low reference is exceeded

[3]

STAGE3_LOW_INT_EN

STAGE3 Low Interrupt Enable

0 = interrupt source disabled

1 = INT asserted if STAGE0 low reference is exceeded

[4]

STAGE4_LOW_INT_EN

STAGE4 Low Interrupt Enable

0 = interrupt source disabled

1 = INT asserted if STAGE0 low reference is exceeded

[5]

STAGE5_LOW_INT_EN

STAGE5 Low Interrupt Enable

0 = interrupt source disabled

1 = INT asserted if STAGE0 low reference is exceeded

[6]

STAGE6_LOW_INT_EN

STAGE6 Low Interrupt Enable

0 = interrupt source disabled

1 = INT asserted if STAGE0 low reference is exceeded

Preliminary Technical Data

AD7142/AD7142-1

Rev. PrD | Page 37 of 64

Address

Data Bit
Content

Default
Value

Type

Name

Description

[7]

STAGE7_LOW_INT_EN

STAGE7 Low Interrupt Enable

0 = interrupt source disabled

1 = INT asserted if STAGE0 low reference is exceeded

[8]

STAGE8_LOW_INT_EN

STAGE8 Low Interrupt Enable

0 = interrupt source disabled

1 = INT asserted if STAGE0 low reference is exceeded

[9]

STAGE9_LOW_INT_EN

STAGE9 Low Interrupt Enable

0 = interrupt source disabled

1 = INT asserted if STAGE0 low reference is exceeded

[10]

STAGE10_LOW_INT_EN

STAGE10 Low Interrupt Enable

0 = interrupt source disabled

1 = INT asserted if STAGE0 low reference is exceeded

[11]

STAGE11_LOW_INT_EN

STAGE11 Low Interrupt Enable

0 = interrupt source disabled

1 = INT asserted if STAGE0 low reference is exceeded

[13:12]

GPIO_SETUP

GPIO Setup

00 = disable GPIO pin

01 = configure GPIO as an input

10 = configure GPIO as an active low output

11 = configure GPIO as an active high output

[15:14]

GPIO_INPUT_CONFIG

GPIO Input Configuration

00 = triggered on negative level

01 = triggered on positive edge

10 = triggered on negative edge

11 = triggered on positive level

006

[0]

R/W

STAGE0_HIGH_INT_EN

STAGE0 High Interrupt Enable

0 = interrupt source disabled

1 = INT asserted if STAGE0 high reference is exceeded

[1]

STAGE1_HIGH_INT_EN

STAGE1 High Interrupt Enable

0 = interrupt source disabled

1 = INT asserted if STAGE0 high reference is exceeded

[2]

STAGE2_HIGH_INT_EN

STAGE2 High Interrupt Enable

0 = interrupt source disabled

1 = INT asserted if STAGE0 high reference is exceeded

[3]

STAGE3_HIGH_INT_EN

STAGE3 High Interrupt Enable

0 = interrupt source disabled

1 = INT asserted if STAGE0 high reference is exceeded

[4]

STAGE4_HIGH_INT_EN

STAGE4 High Interrupt Enable

0 = interrupt source disabled

1 = INT asserted if STAGE0 high reference is exceeded

[5]

STAGE5_HIGH_INT_EN

STAGE5 High Interrupt Enable

0 = interrupt source disabled

1 = INT asserted if STAGE0 high reference is exceeded

[6]

STAGE6_HIGH_INT_EN

STAGE6 High Interrupt Enable

0 = interrupt source disabled

1 = INT asserted if STAGE0 high reference is exceeded

[7]

STAGE7_HIGH_INT_EN

STAGE7 High Interrupt Enable

0 = interrupt source disabled

1 = INT asserted if STAGE0 high reference is exceeded

AD7142/AD7142-1

Preliminary Technical Data

Rev. PrD | Page 38 of 64

Address

Data Bit
Content

Default
Value

Type

Name

Description

[8]

STAGE8_HIGH_INT_EN

STAGE8 High Interrupt Enable

0 = interrupt source disabled

1 = INT asserted if STAGE0 high reference is exceeded

[9]

STAGE9_HIGH_INT_EN

STAGE9 Sensor Interrupt Low Limit Control

0 = interrupt source disabled

1 = INT asserted if STAGE10_LOW is exceeded

[10]

STAGE10_HIGH_INT_EN

STAGE10 High Interrupt Enable

0 = interrupt source disabled

1 = INT asserted if STAGE0 high reference is exceeded

[11]

STAGE11_HIGH_INT_EN

STAGE11 High Interrupt Enable

0 = interrupt source disabled

1 = INT asserted if STAGE0 high reference is exceeded

[15:12]

Unused

Set Unused Register Bits = 0

007

[0]

R/W

STAGE0_COMPLETE_EN

STAGE0 Conversion Interrupt Control

0 = interrupt source disabled

1 = INT asserted at completion of STAGE0 conversion

[1]

STAGE1_COMPLETE_EN

STAGE1 Conversion Interrupt Control

0 = interrupt source disabled

1 = INT asserted at completion of STAGE1 conversion

[2]

STAGE2_COMPLETE_EN

STAGE2 Conversion Interrupt Control

0 = interrupt source disabled

1 = INT asserted at completion of STAGE2 conversion

[3]

STAGE3_COMPLETE_EN

STAGE3 Conversion Interrupt Control

0 = interrupt source disabled

1 = INT asserted at completion of STAGE3 conversion

[4]

STAGE4_COMPLETE_EN

STAGE4 Conversion Interrupt Control

0 = interrupt source disabled

1 = INT asserted at completion of STAGE4 conversion

[5]

STAGE5_COMPLETE_EN

STAGE5 Conversion Interrupt Control

0 = interrupt source disabled

1 = INT asserted at completion of STAGE5 conversion

[6]

STAGE6_COMPLETE_EN

STAGE6 Conversion Interrupt Control

0 = interrupt source disabled

1 = INT asserted at completion of STAGE6 conversion

[7]

STAGE7_COMPLETE_EN

STAGE7 Conversion Interrupt Control

0 = interrupt source disabled

1 = INT asserted at completion of STAGE7 conversion

[8]

STAGE8_COMPLETE_EN

STAGE8 Conversion Complete Interrupt Control

0 = interrupt source disabled

1 = INT asserted at completion of STAGE8 conversion

[9]

STAGE9_COMPLETE_EN

STAGE9 Conversion Interrupt Control

0 = interrupt source disabled

1 = INT asserted at completion of STAGE9 conversion

[10]

STAGE10_COMPLETE_EN

STAGE10 Conversion Interrupt Control

0 = interrupt source disabled

1 = INT asserted at completion of STAGE10 conversion

[11]

STAGE11_COMPLETE_EN

STAGE11 Conversion Interrupt Control

0 = interrupt source disabled

1 = INT asserted at completion of STAGE11 conversion

Preliminary Technical Data

AD7142/AD7142-1

Rev. PrD | Page 39 of 64

Address

Data Bit
Content

Default
Value

Type

Name

Description

[12]

GPIO_INT_EN

Interrupt Control when GPIO Input Pin Changes Level

0 = disabled

1 = enabled

[15:13]

Unused

Set Unused Register Bits = 0

Table 22. CDC Low Limit Status Register Map

Address

Data Bit
Content

Default
Value

Type

Name

Description

008

[0]

STAGE0_LOW_LIMIT

STAGE0 CDC Conversion Low Limit Result

1 = indicates STAGE0_OFFSET_LOW value was
exceeded

[1]

STAGE1_LOW_LIMIT

STAGE1 CDC Conversion Low Limit Result

1 = indicates STAGE1_OFFSET_LOW value was
exceeded

[2]

STAGE2_LOW_LIMIT

STAGE2 CDC Conversion Low Limit Result

1 = indicates STAGE2_OFFSET_LOW value was
exceeded

[3]

STAGE3_LOW_LIMIT

STAGE3 CDC Conversion Low Limit Result

1 = indicates STAGE3_OFFSET_LOW value was
exceeded

[4]

STAGE4_LOW_LIMIT

STAGE4 CDC Conversion Low Limit Result

1 = indicates STAGE4_OFFSET_LOW value was
exceeded

[5]

STAGE5_LOW_LIMIT

STAGE5 CDC Conversion Low Limit Result

1 = indicates STAGE5_OFFSET_LOW value was
exceeded

[6]

STAGE6_LOW_LIMIT

STAGE6 CDC Conversion Low Limit Result

1 = indicates STAGE6_OFFSET_LOW value was
exceeded

[7]

STAGE7_LOW_LIMIT

STAGE7 CDC Conversion Low Limit Result

1 = indicates STAGE7_OFFSET_LOW value was
exceeded

[8]

STAGE8_LOW_LIMIT

STAGE8 CDC Conversion Low Limit Result

1 = indicates STAGE8_OFFSET_LOW value was
exceeded

[9]

STAGE9_LOW_LIMIT

STAGE9 CDC Conversion Low Limit Result

1 = indicates STAGE9_OFFSET_LOW value was
exceeded

[10]

STAGE10_LOW_LIMIT

STAGE10 CDC Conversion Low Limit Result

1 = indicates STAGE10_OFFSET_LOW value was
exceeded

[11]

STAGE11_LOW_LIMIT

STAGE11 CDC Conversion Low Limit Result

1 = indicates STAGE11_OFFSET_LOW value was
exceeded

[15:12]

Unused

Set Unused Register Bits = 0

Registers self-clear to 0 after readback, provided that the limits are not exceeded.

AD7142/AD7142-1

Preliminary Technical Data

Rev. PrD | Page 40 of 64

Table 23.CDC High Limit Status

Address

Data Bit
Content

Default
Value

Type

Name

Description

009

[0]

STAGE0_HIGH_LIMIT

STAGE0 CDC Conversion High Limit Result

1 = indicates STAGE0_OFFSET_HIGH value was exceeded

[1]

STAGE1_HIGH_LIMIT

STAGE1 CDC Conversion High Limit Result

1 = indicates STAGE1_OFFSET_HIGH value was exceeded

[2]

STAGE2_HIGH_LIMIT

Stage2 CDC Conversion High Limit Result

1 = indicates STAGE2_OFFSET_HIGH value was exceeded

[3]

STAGE3_HIGH_LIMIT

STAGE3 CDC Conversion High Limit Result

1 = indicates STAGE3_OFFSET_HIGH value was exceeded

[4]

STAGE4_HIGH_LIMIT

STAGE4 CDC Conversion High Limit Result

1 = indicates STAGE4_OFFSET_HIGH value was exceeded

[5]

STAGE5_HIGH_LIMIT

STAGE5 CDC Conversion High Limit Result

1 = indicates STAGE5_OFFSET_HIGH value was exceeded

[6]

STAGE6_HIGH_LIMIT

STAGE6 CDC Conversion High Limit Result

1 = indicates STAGE6_OFFSET_HIGH value was exceeded

[7]

STAGE7_HIGH_LIMIT

STAGE7 CDC Conversion Low Limit Result

1 = indicates STAGE7_OFFSET_HIGH value was exceeded

[8]

STAGE8_HIGH_LIMIT

STAGE8 CDC Conversion High Limit Result

1 = indicates STAGE8_OFFSET_HIGH value was exceeded

[9]

STAGE9_HIGH_LIMIT

STAGE9 CDC Conversion High Limit Result

1 = indicates STAGE9_OFFSET_HIGH value was exceeded

[10]

STAGE10_HIGH_LIMIT

STAGE10 CDC Conversion High Limit Result

1 =indicates STAGE10_OFFSET_HIGH value was
exceeded

[11]

STAGE11_HIGH_LIMIT

STAGE11 CDC Conversion High Limit Result

1 = indicates STAGE11_OFFSET_HIGH value was
exceeded

[15:12]

Unused

Set Unused Register Bits = 0

Registers self-clear to 0 after readback, provided that the limits are not exceeded.

Preliminary Technical Data

AD7142/AD7142-1

Rev. PrD | Page 41 of 64

Table 24. CDC Conversion Completion Register Map

Address

Data Bit
Content

Default
Value

Type

Name

Description

00A

[0]

STAGE0_COMPLETE_STATUS

STAGE0 Conversion Completion Status