Document Outline

• Specifications
• Features
• Applications
• Product Description
• Ordering Guide
• Absolute Maximum Ratings
• Functional Block Diagram
• Pin Function Description
• SYSTEM DEVELOPMENT
• ADDITIONAL INFORMATION
• ARCHITECTURE OVERVIEW
• PMD-DMD BUS EXCHANGE
• STATUS REGISTERS
• SSTAT
• MSTAT
• IMASK
• ICNTL
• CONDITION CODES
• SYSTEM INTERFACE
• DATA MOVE INSTRUCTIONS
• COMPUTATIONAL INSTRUCTIONS: ALU
• COMPUTATIONAL INSTRUCTIONS: SHIFTER
• COMPUTATIONAL INSTRUCTIONS: MAC
• MULTIFUNTION INSTRUCTIONS
• MISCELLANEOUS INSTRUCTIONS
• RECOMMENDED OPERTING CONDITIONS
• ELECTICAL CHARACTERISTICS
• ESD SENSITIVITY
• SWITCHING CHARACTERISTICS
• GENREAL NOTES
• TIMING NOTES
• MEMORY REQUIREMENTS
• NOTE ON GENERATING WAIT STATES
• TEST CODES
• DERATING FACTOR
• CAPACITANCE IN PGA PACKAGE
• MECHANICAL INFORMATION
• DIAGRAMS
  • Block Diagram
  • Arthmetic/Logic Unit Block Diagram
  • MAC Block Diagram
  • Shifter Block Diagram
  • Dat Address Generator
  • Program Sequencer
  • Basic System Configuration
  • Clock Signals
  • RESET Signals
  • Control Signals
  • Bus Request Asserted
  • Bus Request Negated
  • Untitled
  • use Request/Grant with RESET Low
  • Program Memory Read
  • Program Memoery Write
  • Data Memory Read
  • Data Memory Wait States Extended with DMACK
  • Data Memory Write
  • Data Memory Wait States Extended woth BMACK
  • Normal Load for as Measurements