REV. B

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

CMOS Monolithic 256 18

Color Palette RAM-DAC

ADV476

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700

Fax: 617/326-8703

FUNCTIONAL BLOCK DIAGRAM

FEATURES
Personal System/2* and VGA* Compatible
Plug-in Replacement for INMOS 171/176
66 MHz Pipelined Operation
Three 6-Bit D/A Converters
256 18 Color Palette RAM
RS-343A/RS-170 Compatible Outputs
Blank on All Three Channels
Standard MPU Interface
Asynchronous Access to All Internal Registers

5 V CMOS Monolithic Construction

Low Power Dissipation
Standard 28-Pin, 0.6" DIP and 44-Pin PLCC

APPLICATIONS
High Resolution Color Graphics
CAE/CAD/CAM Applications
Image Processing
Instrumentation
Desktop Publishing

AVAILABLE CLOCK RATES
66 MHz
50 MHz
35 MHz

GENERAL DESCRIPTION

The ADV476 (ADV

) is a pin compatible and software compat-

ible RAM-DAC designed specifically for VGA and Personal
System/2 color graphics.

The ADV476 is a complete analog output RAM-DAC on a
single monolithic chip. The part contains a 256 18 color
lookup table, a pixel mask register as well as a triple 6-bit video
D/A converter. The ADV476 is capable of simultaneously dis-
playing up to 256 colors, from a total color palette of 262,144
addressable colors.

The on-chip asynchronous MPU bus allows access to the color
lookup table without affecting the input video data via the pixel
port. The pixel read mask register provides a convenient way of
altering the displayed colors without updating the color lookup
table. The ADV476 is capable of generating RGB video output
signals which are compatible with RS-343A and RS-170 video
standards, without requiring external buffering.

The ADV476 is fabricated in a +5 V CMOS process. Its mono-
lithic CMOS construction ensures greater functionality with low
power dissipation and small board area. The part is packaged in
a 0.6", 28-pin DIP and a 44-pin PLCC.

PRODUCT HIGHLIGHTS

1. Standard video refresh rates, 35 MHz, 50 MHz and

66 MHz.

2. Fully compatible with VGA and Personal System/2 color

graphics.

3. Guaranteed monotonic. Integral and differential linearity

guaranteed to be a maximum of

1 LSB.

4. Low glitch energy, 75 pV secs.

*Personal System/2 and VGA are trademarks of International Business

Machines Corp.
ADV is a registered trademark of Analog Devices, Inc.

REV. B

ADV476SPECIFICATIONS

= +5 V 10%, I

REF

= 8.88 mA.

All Specifications T

MIN

to T

MAX

unless otherwise noted.)

Parameter

All Versions

Units

Test Conditions/Comments

STATIC PERFORMANCE

Resolution (Each DAC)

Bits

Accuracy (Each DAC)

Integral Nonlinearity

0.5

LSB max

Guaranteed Monotonic

Full Scale Error

% max

Full Scale = 2.15

REF

, I

REF

= 8.39 mA

Blank Level

0.5

LSB max

BLANK

= Logic Low

Offset Error

0.5

LSB max

BLANK

= Logic High

DIGITAL INPUTS

Input High Voltage, V

INH

V min

Input Low Voltage, V

INL

0.8

V max

Input Current, I

A max

= 5.5 V, V

= 0.4 V to V

Input Current (RD Input Only)

100

A max

= 5.5 V, V

= 0.4 V to V

Input Capacitance, C

pF typ

DIGITAL OUTPUTS

Output High Voltage, V

2.4

V min

SOURCE

= 500

A, V

= 4.5 V

Output Low Voltage, V

0.4

V max

SINK

= 5.0 mA, V

= 4.5 V

Floating-State Leakage Current

A max

= 5.5 V, 0.4 V < V

< V

Floating-State Output Capacitance

pF typ

ANALOG OUTPUTS

Max Output Voltage

1.5

V min

IO < 10 mA, IO = 2.15 I

REF

Max Output Current

mA min

1 V

DAC to DAC Matching

2.5

% max

Analog Output Capacitance

pF typ

BLANK

= Logic Low

CURRENT REFERENCE

Input Current (I

REF

) Range

3/10

mA min/mA max

Voltage at I

REF

3/V

V min/V max

REF

= 8.88 mA

POWER SUPPLY

Supply Voltage, V

4.5/5.5

V min/V max

Supply Current, I

220

mA max

MAX

= 66 MHz IO = 2.15

REF

, D0D7 Unloaded

Power Supply Rejection Ratio

%/V

4.5 < V

< 5.5 V, IO = 2.15

REF

, R

= 37.5

= 30 pF, I

REF

= 8.88 mA.

DYNAMIC PERFORMANCE

Clock and Data Feedthrough

3, 4

dB typ

Glitch Impulse

3, 4

pV secs typ

NOTES

Temperature range (T

MIN

to T

MAX

); 0 to +70

Relative to the midpoint of the distribution of the three DACs measured at full scale.

TTL input values are 0 to 3 volts, with input rise/fall times

3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and out-

puts. Analog output load

10 pF, 37.5

. D0D7 output load

50 pF. See timing notes in Figure 2.

Clock and data feedthrough is a function of the amount of overshoot and undershoot on the digital inputs. For this test, the digital inputs have a 1 k

resistor to

ground and are driven by 74HC logic. Glitch impulse includes clock and data feedthrough, 3 dB test bandwidth = 2

clock rate.

Specifications subject to change without notice.

ADV476

REV. B

TIMING CHARACTERISTICS

Parameter

66 MHz Version

50 MHz Version

35 MHz Version

Units

Conditions/Comments

MAX

MHz

Clock Rate

ns min

RS0, RS1 Setup Time

ns min

RS0, RS1 Hold Time

ns min

Asserted to Data Bus Driven

ns max

Asserted to Data Valid

ns max

Negated to Data Bus 3-Stated

ns min

Write Data Setup Time

ns min

Write Data Hold Time

ns min

, WR Pulse Width Low

4 t

ns min

, WR Pulse Width High

ns min

Pixel & Control Setup Time

ns min

Pixel & Control Hold Time

15.3

ns min

Clock Cycle Time

ns min

Clock Pulse Width High Time

ns min

Clock Pulse Width Low Time

ns max

Analog Output Delay

ns min

ns max

Analog Output Rise/Fall Time

15.3

ns typ

Analog Output Settling Time

ns min

Analog Output Skew

clocks

Pipeline Delay

NOTES

TTL input values are 0 to 3 volts, with input rise/fall times

3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and

outputs. Analog output load

10 pF, 37.5

. D0D7 output load

50 pF. See timing notes in Figure 2.

Temperature Range (T

MIN

to T

MAX

); 0 to +70

Settling time does not include clock and data feedthrough. For this test, the digital inputs have a 1 k

resistor to ground and are driven by 74HC logic.

Specifications subject to change without notice.

Figure 1. MPU Read/Write Timing

Figure 2. Video Input/Output Timing

= +5 V 10%. All Specifications T

MIN

to T

MAX

)

ADV476

REV. B

ABSOLUTE MAXIMUM RATINGS

to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7 V

Voltage on any Digital Pin . . . . . GND 0.5 V to V

+ 0.5 V

Ambient Operating Temperature (T

) . . . . . 55

C to +125

Storage Temperature (T

) . . . . . . . . . . . . . . 65

C to +150

Junction Temperature (T

) . . . . . . . . . . . . . . . . . . . . +150

Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . +300

Vapor Phase Soldering (1 minute) . . . . . . . . . . . . . . . +220

Red, Green, Blue to GND

. . . . . . . . . . . . . . . . . . 0 V to V

NOTES

Stresses above those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.

Analog output short circuit to any power supply or common can be of an indefinite
duration.

ORDERING GUIDE

1, 2

Package

Model

Speed

Package Type

Option

ADV476KN35

35 MHz

28-Pin DIP

N-28

ADV476KN50

50 MHz

28-Pin DIP

N-28

ADV476KN66

66 MHz

28-Pin DIP

N-28

ADV476KP35

35 MHz

44-Pin PLCC

P-44A

ADV476KP50

50 MHz

44-Pin PLCC

P-44A

ADV476KP66

66 MHz

44-Pin PLCC

P-44A

NOTES

All devices are specified for 0

C to +70

C operation.

Devices are packaged in 0.6" 28-pin plastic DIPs (N-28), and 44-pin J-leaded

PLCC (P-44A).

N = Plastic DIP; P = Plastic Leaded Chip Carrier.

RECOMMENDED OPERATING CONDITIONS

Parameter

Symbol

Min

Typ

Max

Units

Power Supply

4.5

5.00

5.5

Volts

Ambient Operating Temperature

+70

Output Load

37.5

Reference Current

REF

WARNING!

ESD SENSITIVE DEVICE

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADV476 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

PIN CONFIGURATIONS

PLCC

DIP

The above pins allow the ADV476KP (44-Pin PLCC) to be al-
ternatively driven by a voltage reference. If it is desired to use a
voltage reference configuration instead of the current reference
configuration described in this data sheet, the above listed pins
must be connected as described in Figure 6 of the ADV478/
ADV471 data sheet of this reference manual.

ADV476

REV. B

PIN FUNCTION DESCRIPTION

Pin
Mnemonic

Function

BLANK

Composite blank control input (TTL compatible). A logic zero on this control input drives the analog outputs to
the blanking level, as shown in Table V. The BLANK signal is latched on the rising edge of PCLK. While
BLANK

is a logical zero, the pixel inputs are ignored.

PCLK

Clock input (TTL compatible). The rising edge of PCLK latches the P0P7 data inputs and the BLANK control
input. It is typically the pixel clock rate of the video system. PCLK should be driven by a dedicated TTL buffer.

P0P7

Pixel select inputs (TTL compatible). These inputs specify, on a pixel basis, which one of the 256 entries in the
color palette RAM is to be used to provide color information. P0P7 pixel select inputs are latched on the rising
edge of PCLK. P0 is the LSB. Unused pixel select inputs should be connected to GND.

RED, GREEN,

Red, green and blue current outputs. These high impedance current sources are capable of directly driving a

BLUE

doubly terminated 75

coaxial cable, as shown in Figure 4a. All three current outputs should have similar out-

put loads whether or not they are all being used.

Analog power supply (5 V

10%).

GND

Analog ground.

REF

Current reference input. The relationship between the current input and the full scale output voltage of the
DACs is given by the following expression:

REF

= VO (Full Scale)/2.15 R

= Load Resistance

Write control input (TTL compatible). WR must be at logical zero when writing data to the device. D0D7 data
is latched on the rising edge of WR. See Figure 1.

Read control input (TTL compatible). RD must both be at logical zero when reading data from the device.
See Figure 1.

RS0, RS1

Command control inputs (TTL compatible). RS0 and RS1 specify the type of read or write operation being car-
ried out, i.e., address register or color palette RAM read or write operations. See Tables I, II, III.

D0D7

Data bus (TTL compatible). Data is transferred to and from the address register and the color palette RAM over
this 8-bit bidirectional data bus. D0 is the least significant bit.

TERMINOLOGY
Blanking Level

The level separating the SYNC portion from the Video portion
of the waveform. Usually referred to as the Front Porch or Back
Porch. At 0 IRE Units, it is the level which will shut off the pic-
ture tube, resulting in the blackest possible picture.

Color Video (RGB)

This usually refers to the technique of combining the three pri-
mary colors of Red, Green and Blue to produce color pictures
within the usual spectrum. In RGB monitors, three DACs are
required, one for each color.

Gray Scale

The discrete levels of video signal between Reference Black and
Reference White levels. An 8-bit DAC contains 256 different
levels while a 6-bit DAC contains 64.

Raster Scan

The most basic method of sweeping a CRT one line at a time to
generate and display images.

Reference Black Level

The maximum negative polarity amplitude of the video signal.

Reference White Level

The maximum positive polarity amplitude of the video signal.

Video Signal

That portion of the composite video signal which varies in gray
scale levels between Reference White and Reference Black. Also
referred to as the picture signal, this is the portion which may be
visually observed.

ADV476

REV. B

MPU Interface

As illustrated in the functional block diagram, the ADV476 sup-
ports a standard MPU bus interface, allowing the MPU direct
access to the color palette RAM.

The RS0 and RS1 control inputs specify whether the MPU is
accessing the address register or the color palette RAM, as
shown in Table I. The 8-bit address register is used to address
the color palette RAM, eliminating the requirement for external
address multiplexers.

Table I. Control Input Truth Table

RS1

RS0

Addressed by MPU

Pixel Address Register (RAM Write Mode)

Pixel Address Register (RAM Read Mode)

Color Palette RAM

Pixel Read Mask Register

To write color data, the MPU writes to the address register with
the 8-bit address of the color palette RAM location which is to
be modified. The MPU performs three successive write cycles
(six bits of red data, six bits of green data and six bits of blue
data). During the blue write cycle, the three bytes of color infor-
mation are concatenated into an 18-bit word and written to the
location specified by the address register. The address register
then automatically increments to the next location which the
MPU may modify by simply writing another sequence of red,
green and blue data.

To read back color data, the MPU loads the address register
with the address of the color palette RAM location to be read.
The MPU performs three successive read cycles (6 bits each of
red, green and blue data). Following the blue read cycle, the

address register increments to the next location which the MPU
may read by simply reading another sequence of red, green and
blue data.

This 6-bit color data is right justified, i.e., the lower six bits of
the data bus with D0 being the LSB and D5 the MSB. D6 and
D7 are ignored during a color write cycle and are set to zero
during a color read cycle.

During color palette RAM access, the address register resets to
00H following a blue read or write operation to RAM location
FFH.

The MPU interface operates asynchronously to the pixel clock.
Data transfers between the color palette RAM and the color
registers (R, G, and B in the block diagram) are synchronized by
internal logic, and occur in the period between MPU accesses.
Color (RGB) data is normally loaded to the color palette RAM
during video screen retrace, i.e., during the video waveform
blanking period, see Figure 5.

To keep track of the red, green and blue read/write cycles, the
address register has two additional bits (ADDRa, ADDRb) that
count modulo three, as shown in Table II. They are reset to
zero when the MPU writes to the address register, and are not
reset to zero when the MPU reads the address register. The
MPU does not have access to these bits. The other eight bits of
the address register, incremented following a blue read or write
cycle, (ADDR07) are accessible to the MPU, and are used to
address color palette RAM locations, as shown in Table III.
ADDR0 is the LSB when the MPU is accessing the RAM. The
MPU may read the address register at any time without modify-
ing its contents or the existing read/write mode.

Figure 1 illustrates the MPU read/write timing and Table III
shows the associated functional instructions.

Table II. Address Register (ADDR) Operation

Value

RS1

RS0

Addressed by MPU

ADDRa,b (Counts Modulo 3)

Red Value

Green Value

Blue Value

ADDR07 (Counts Binary)

00HFFH

Color Palette RAM

Table III. Truth Table for Read/Write Operations

RS0

RS1

ADDRa

ADDRb

Operation Performed

Write Address Register;

D0D7

ADDR07

ADDRa,b

Write Red Value;

Increment ADDRab

Write Green Value;

Increment ADDRab

Write Blue Value;

Modify RAM Location
Increment ADDR07
Increment ADDRab

Read Address Register;

ADDR07

D0D7

Read Red Value;

Increment ADDRab

Read Green Value;

Increment ADDRab

Read Blue Value;

Increment ADDR07
Increment ADDRab

Invalid Operation

ADV476

REV. B

Frame Buffer Interface

The P0-P7 inputs are used to address the color palette RAM, as
shown in Table IV. These inputs are latched on the rising edge
of PCLK and address any of the 256 locations in the color pal-
ette RAM. The addressed location contains 18 bits of color (6
bits of red, 6 bits of green and 6 bits of blue) information. This
data is transferred to the three DACs and is then converted to
an analog output (RED, GREEN, BLUE), these outputs then
control the red, green and blue electron guns in the monitor.

The BLANK input is also latched on the rising edge of PCLK.
This is to maintain synchronization with the color data.

Table IV. Pixel Select/Color Palette Control Truth Table

P0P7

Addressed by Frame Buffer

00H

Color Palette RAM Location 00H

01H

Color Palette RAM Location 01H

FFH

Color Palette RAM Location FFH

Pixel Read Mask Register

The Pixel Read Mask Register in the ADV476 can be used to
implement register level pixel processing, thereby cutting down
on software overhead. This is achieved by gating the input pixel
stream (P0P7) with the contents of the pixel read mask regis-
ter. The operation is a bitwise logical ANDing of the pixel data.
The contents of This register can be accessed and altered at any
time by the MPU (D0D7). Table I shows the relevant control
signals.

This pixel masking operation can be used to alter the displayed
colors without changing the contents of either the video frame

buffer or the color palette RAM. The effect of this operation is
to partition the color palette into a user determined number of
color planes. This process can be used for special effects includ-
ing animation, overlays and flashing objects.

(See also application note entitled "Animation Using the Pixel
Read Mask Register of the ADV47x Series of Video RAM-
DACs," available from Analog Devices (Pub No.
E13161510/89).

Figure 3. Block Diagram Showing Pixel Read
Mask Register

Analog Interface

The ADV476 has three analog outputs, corresponding to the
Red, Green and Blue video signals.

The Red, Green and Blue analog outputs of the ADV476 are
high impedance current sources. Each one of these three RGB
current outputs is capable of directly driving a 37.5

load, such

as a doubly-terminated 75

coaxial cable. Figure 4a shows the

required configuration for each of the three RGB outputs con-
nected into a doubly-terminated 75

load. This arrangement

will develop RS-343A video output voltage levels across a 75

monitor. A simple method of driving RS-170 video levels into a
75

monitor is shown in Figure 4b. The output current levels

of the DACs remain unchanged but the source termination

Figure 4a. Recommended Analog Output Termination
for RS-343A

resistance, Z

on each of the three DACs is increased from 75

to 150

More detailed information regarding load terminations for vari-
ous output configurations, including RS-343A and RS-170, is
available in an application note entitled "Video Formats &
Required Load Terminations," available from Analog Devices.

Figure 5 shows the video waveforms associated with the three
RGB outputs, driving the doubly terminated 75

load of Fig-

ure 4a. The BLANK control input drives the analog outputs to
the Black Level. BLANK is asserted prior to horizontal and ver-
tical screen retrace. Table V details how the BLANK input
modifies the output levels.

Figure 4b. Recommended Analog Output Termination
for RS-170

ADV476

REV. B

Figure 5. RGB Video Output Waveform

Table V. Video Output Truth Table

RED, GREEN,

DAC

Description

BLUE, (mA)

BLANK

Input Data

WHITE LEVEL

19.05

FFH

VIDEO

Video

DATA

BLACK LEVEL

00H

BLANK LEVEL

xxH

NOTE

Typical with full Scale RED, GREEN, BLUE = 19.05 mA. I

REF

= 8.88 mA.

Reference Input

The ADV476 requires an active current reference to enable the
DACs provide stable and accurate video output levels. The rela-
tionship between the output voltage and the required input ref-
erence current is given by:

REF

VO ( FULL SCALE )

2.15

where

= 37.5

(for doubly terminated 75

load)

= 75

(for singly terminated 75

load)

and

VO = 0.714 V (RS-343A video levels)

= 1.0 V

(RS-170 video levels).

In a standard application which requires RS-343A video levels
to be driven into a doubly terminated 75

load (R

= 37.5

the necessary reference input current is:

REF

= 8.88 mA.

To drive the same levels into a singly terminated 75

load

= 75

), the reference current is:

REF

= 4.44 mA.

A suggested current reference design for the doubly terminated
case, with RS-343A video levels and based on the LM334, a
three-terminal adjustable current source, is shown in Figure 6.

Figure 6. Current Reference Design Using an LM334
Current Source

ADV476

REV. B

PC BOARD LAYOUT CONSIDERATIONS

The ADV476 is optimally designed for lowest noise perfor-
mance, both radiated and conducted noise. For optimum sys-
tem noise performance, it is imperative that great care be given
to the PC board layout. The layout should be optimized for low-
est noise on the ADV476 power and ground lines. This can be
achieved by shielding the digital inputs and providing good
decoupling. The lead length between groups of V

and GND

pins should by minimized so as to minimize inductive ringing.

Ground Planes

The ground plane should encompass all ADV476 ground pins,
voltage reference circuitry, power supply bypass circuitry, the
analog output traces and all the digital signal traces leading up
to the ADV476.

Power Planes

The PC board layout should have two distinct power planes,
one for analog circuitry and one for digital circuitry. The analog
power plane (V

) should encompass the ADV476 and all asso-

ciated analog circuitry. This power plane should be connected
to the regular PCB power plane at a single point through a fer-
rite bead, as illustrated in Figure 7. This bead should be located
within three inches of the ADV476.

The PCB power plane should provide power to all digital logic
on the PC board, and the analog power plane should provide
power to all ADV476 power pins, current reference circuitry
and any output amplifiers.

The PCB power and ground planes should not overlay portions
of the analog power plane. Keeping the PCB power and ground
planes from overlaying the analog power plane will contribute to
a reduction in plane-to-plane noise coupling.

Supply Decoupling

Noise on the analog power plane can be further reduced by the
use of multiple decoupling capacitors, see Figure 7.

Optimum performance is achieved by the use of 0.1

F ceramic

capacitors. This should be done by placing the capacitors as
close as possible to the device with the capacitor leads as short
as possible, thus minimizing lead inductance.

It is important to note that while the ADV476 contains circuitry
to reject power supply noise, this rejection decreases with fre-
quency. If a high frequency switching power supply is used, the
designer should pay close attention to reducing power supply
noise. A dc power supply filter (Murata BNX002) will provide
EMI suppression between the switching power supply and the
main PCB. Alternatively, consideration could be given to using
a three terminal voltage regulator.

Digital Signal Interconnect

The digital signal lines to the ADV476 should be isolated as
much as possible from the analog outputs and other analog
circuitry. Digital signal lines should not overlay the analog
power plane.

Due to the high clock rates used, long clock lines to the
ADV476 should be avoided so as to minimize noise pickup.

Any active pull-up termination resistors for the digital inputs
should be connected to the regular PCB power plane and not
the analog power plane.

Analog Signal Interconnect

The ADV476 should be located as close as possible to the out-
put connectors thus minimizing noise pickup and reflections
due to impedance mismatch.

The video output signals should overlay the ground plane, and
not the analog power plane, thereby maximizing the high fre-
quency power supply rejection.

For optimum performance, the analog outputs should each have
a source termination resistance to ground of 75

. This termi-

nation resistance should be as close as possible to the ADV476
to minimize reflections.

Note: For additional information on PC Board-Layout see
Application Note "Design and Layout of a Video Graphics
System for Reduced EMI", available from Analog Devices
(Pub. No. E13091510/89).

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