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REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.

ADV7195

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700

www.analog.com

Fax: 781/326-8703

© Analog Devices, Inc., 2002

Multiformat Progressive Scan/HDTV

Encoder with Three 11-Bit DACs

and 10-Bit Data Input

FUNCTIONAL BLOCK DIAGRAM

CGMS

MACROVISION

SHARPNESS

FILTER CONTROL

AND

ADAPTIVE

FILTER CONTROL

TEST PATTERN

GENERATOR

AND

DELAY

AND

GAMMA

CORRECTION

Y0Y9

Cr0Cr9

Cb0Cb9

CHROMA

4:2:2

4:4:4

(SSAF)

INTER-

POLATION

TIMING

GENERATOR

SYNC

GENERATOR

C MPU

PORT

CLKIN

HORIZONTAL

SYNC

VERTICAL

SYNC

BLANKING

RESET

ADV7195

DAC CONTROL

BLOCK

DAC A (Y)

DAC B

DAC C

REF

RESET

COMP

11-BIT+

SYNC

DAC

11-BIT

DAC

11-BIT

DAC

LUMA

SSAF

CHROMA

4:2:2

4:4:4

(SSAF)

FEATURES
INPUT FORMATS

YCrCb in 2

10-Bit (4:2:2) or 3 10-Bit (4:4:4) Format-

Compliant to SMPTE-293M (525p), ITU-R.BT1358
(625p), SMPTE274M (1080i), SMPTE296M (720p)
and Any Other High-Definition Standard Using
Async Timing Mode

RGB in 3

10 Bit (4:4:4) Format

OUTPUT FORMATS

YPrPb Progressive Scan (EIA-770.1, EIA-770.2)
YPrPb HDTV (EIA-770.3)
RGB Levels Compliant to RS-170 and RS-343A
11-Bit + Sync (DAC A)
11-Bit DACs (DAC B, DAC C)

PROGRAMMABLE FEATURES

Internal Test Pattern Generator with Color Control
Y/C Delay ( )
Gamma Correction
Individual DAC On/Off Control
54 MHz Output (2 Oversampling)
Sharpness Filter with Programmable Gain/Attenuation
Programmable Adaptive Filter Control
Undershoot Limiter
VBI Open Control
I

Filter

CGMS-A (525p)
2-Wire Serial MPU Interface
Single Supply 3.3 V Operation
52-MQFP Package

APPLICATIONS

Progressive Scan/HDTV Display Devices
MPEG at 81 MHz
Progressive Scan/HDTV Projection Systems
Digital Video Systems
High Resolution Color Graphics
Image Processing/Instrumentation
Digital Radio Modulation/Video Signal Reconstruction

GENERAL DESCRIPTION

The ADV7195 is a triple high-speed, digital-to-analog encoder
on a single monolithic chip. It consists of three high-speed video
D/A converters with TTL-compatible inputs.

The ADV7195 has three separate 10-bit-wide input ports that
accept data in 4:4:4 10-bit YCrCb or RGB or 4:2:2 10-bit YCrCb.
This data is accepted in progressive scan format at 27 MHz or
HDTV format at 74.25 MHz or 74.1758 MHz. For any other
high-definition standard but SMPTE293M, ITU-R BT.1358,
SMPTE274M or SMPTE296M the Async Timing Mode can
be used to input data to the ADV7195. For all standards, exter-
nal horizontal, vertical, and blanking signals or EAV/SAV codes
control the insertion of appropriate synchronization signals into
the digital data stream and therefore the output signals.

The ADV7195 outputs analog YPrPb progressive scan format
complying to EIA-770.1, EIA-770.2; YPrPb HDTV complying
to EIA-770.3; RGB complying to RS-170/RS-343A.

The ADV7195 requires a single 3.3 V power supply, an
optional external 1.235 V reference and a 27 MHz clock in
Progressive Scan Mode or a 74.25 MHz (or 74.1758 MHz)
clock in HDTV mode.

In Progressive Scan Mode, a sharpness filter with programmable
gain allows high-frequency enhancement on the luminance signal.
Programmable Adaptive Filter Control, which may be used,
allows removal of ringing on the incoming Y data. The ADV7195
supports CGMS-A data control generation.

The ADV7195 is packaged in a 52-lead MQFP package.

C is a registered trademark of Philips Corporation.

REV. A

ADV7195

FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 1
FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . . 1
3.3 V SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3 V DYNAMICSPECIFICATIONS . . . . . . . . . . . . . . . . . . 4
3.3 V TIMINGSPECIFICATIONS . . . . . . . . . . . . . . . . . . 5
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . 8
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . 9
FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . 10

Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Analog Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Undershoot Limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
I

C Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Internal Test Pattern Generator . . . . . . . . . . . . . . . . . . . . 10
Y/CrCb Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Gamma Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
54 MHz Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

PROGRAMMABLE SHARPNESS FILTER . . . . . . . . . . . 10
PROGRAMMABLE ADAPTIVE FILTER CONTROL . . 11
INPUT/OUTPUT CONFIGURATION . . . . . . . . . . . . . . 11
MPU PORT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . 11
REGISTER ACCESSES . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
REGISTER PROGRAMMING . . . . . . . . . . . . . . . . . . . . . 13

Subaddress Register (SR7SR0) . . . . . . . . . . . . . . . . . . . 13
Register Select (SR6SR0) . . . . . . . . . . . . . . . . . . . . . . . . 13

PROGRESSIVE SCAN MODE . . . . . . . . . . . . . . . . . .

MODE REGISTER 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

MR0 (MR07MR00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

MR0 BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 14

Output Standard Selection (MR00MR01) . . . . . . . . . . . 14
Input Control Signals (MR02MR03) . . . . . . . . . . . . . . . 14
Input Standard (MR04) . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Reserved (MR05) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
DV Polarity (MR06) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Reserved (MR07) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

MODE REGISTER 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

MR1 (MR17MR10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

MR1 BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 16

Pixel Data Enable (MR10) . . . . . . . . . . . . . . . . . . . . . . . . 16
Input Format (MR11) . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Test Pattern Enable (MR12) . . . . . . . . . . . . . . . . . . . . . . 16
Test Pattern Hatch/Frame (MR13) . . . . . . . . . . . . . . . . . 16
VBI Open (MR14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Undershoot Limiter (MR15MR16) . . . . . . . . . . . . . . . . 16
Sharpness Filter (MR17) . . . . . . . . . . . . . . . . . . . . . . . . . 16

MODE REGISTER 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

MR1 (MR27MR20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

MR2 BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 17

Y Delay (MR20MR22) . . . . . . . . . . . . . . . . . . . . . . . . . 17
Color Delay (MR23MR25) . . . . . . . . . . . . . . . . . . . . . . 17
CGMS Enable (MR26) . . . . . . . . . . . . . . . . . . . . . . . . . . 17
CGMS CRC (MR27) . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

MODE REGISTER 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

MR3 (MR37MR30) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

MR3 BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 18

HDTV Enable (MR30) . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Reserved (MR31MR32) . . . . . . . . . . . . . . . . . . . . . . . . . 18
DAC A Control (MR33) . . . . . . . . . . . . . . . . . . . . . . . . . 18
DAC B Control (MR34) . . . . . . . . . . . . . . . . . . . . . . . . . 18
DAC C Control (MR35) . . . . . . . . . . . . . . . . . . . . . . . . . 18
Interpolation (MR36) . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Reserved (MR37) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

MODE REGISTER 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

MR4 (MR47MR40) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

MR4 BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . 18

Timing Reset (MR40) . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

MODE REGISTER 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

MR5 (MR57MR50) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

MR5 BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 18

Reserved (MR50) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
RGB Mode (MR51) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Sync on PrPb (MR52) . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Color Output Swap (MR53) . . . . . . . . . . . . . . . . . . . . . . 19
Gamma Curve (MR54) . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Gamma Correction (MR55) . . . . . . . . . . . . . . . . . . . . . . 19
Adaptive Mode Control (MR56) . . . . . . . . . . . . . . . . . . . 19
Adaptive Filter Control (MR57) . . . . . . . . . . . . . . . . . . . 19

COLOR Y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

CY (CY7CY0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

COLOR CR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

CCR (CCR7CCR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

COLOR CB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

CCB (CCB7CCB0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

MODE REGISTER 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

MR6 (MR67MR60) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

MR6 BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 20

MR67MR60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

CGMS DATA REGISTERS 20 . . . . . . . . . . . . . . . . . . . . 20

CGMS2 (CGMS27CGMS20) . . . . . . . . . . . . . . . . . . . . 20
CGMS1 (CGMS17CGMS10) . . . . . . . . . . . . . . . . . . . . 20
CGMS0 (CGMS07CGMS00) . . . . . . . . . . . . . . . . . . . . 20

FILTER GAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

FG (FG7FG0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

FG BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Filter Gain A (FG3FG0) . . . . . . . . . . . . . . . . . . . . . . . . 21
Filter Gain B (FG4FG7) . . . . . . . . . . . . . . . . . . . . . . . . 21

GAMMA CORRECTION REGISTERS 013

(GAMMA CORRECTION 013) . . . . . . . . . . . . . . . . . . 21

SHARPNESS FILTER CONTROL AND

ADAPTIVE FILTER CONTROL . . . . . . . . . . . . . . . . . 22

SHARPNESS FILTER MODE . . . . . . . . . . . . . . . . . . . . . 22
ADAPTIVE FILTER MODE . . . . . . . . . . . . . . . . . . . . . . . 22
ADAPTIVE FILTER GAIN 1 . . . . . . . . . . . . . . . . . . . . . . 23

AFG1 (AFG1)70 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

ADAPTIVE FILTER GAIN 2 . . . . . . . . . . . . . . . . . . . . . . 23

AFG2 (AFG2)70 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

ADAPTIVE FILTER GAIN 3 . . . . . . . . . . . . . . . . . . . . . . 23

AFG3 (AFG3)70 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

TABLE OF CONTENTS

REV. A

ADV7195

ADAPTIVE FILTER THRESHOLD A . . . . . . . . . . . . . . . 23

AFTA AFTA70 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

ADAPTIVE FILTER THRESHOLD B . . . . . . . . . . . . . . . 23

AFTB AFTB70 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

ADAPTIVE FILTER THRESHOLD C . . . . . . . . . . . . . . . 23

AFTC AFTC70 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

SHARPNESS FILTER AND ADAPTIVE FILTER

APPLICATIONS EXAMPLES . . . . . . . . . . . . . . . . . . . . 24
Sharpness Filter Application . . . . . . . . . . . . . . . . . . . . . . 24
Adaptive Filter Control Application . . . . . . . . . . . . . . . . . 25

HDTV MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MODE REGISTER 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

MR0 (MR07MR00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

MR0 BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 26

Output Standard Selection (MR00-MR01) . . . . . . . . . . . 26
Input Control Signals (MR02MR03) . . . . . . . . . . . . . . . 26
Reserved (MR04) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Input Standard (MR05) . . . . . . . . . . . . . . . . . . . . . . . . . . 26
DV Polarity (MR06) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Reserved (MR07) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

MODE REGISTER 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

MR1 (MR17MR10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

MR1 BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 27

Pixel Data Enable (MR10) . . . . . . . . . . . . . . . . . . . . . . . . 27
Input Format (MR11) . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Test Pattern Enable (MR12) . . . . . . . . . . . . . . . . . . . . . . 27
Test Pattern Hatch/Frame (MR13) . . . . . . . . . . . . . . . . . 27
VBI Open (MR14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Reserved (MR15MR17) . . . . . . . . . . . . . . . . . . . . . . . . . 27

MODE REGISTER 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

MR1 (MR27MR20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

MR2 BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . 28

Y Delay (MR20MR22) . . . . . . . . . . . . . . . . . . . . . . . . . 28

Color Delay (MR23MR25) . . . . . . . . . . . . . . . . . . . . . . 28
Reserved (MR26MR27) . . . . . . . . . . . . . . . . . . . . . . . . . 28

MODE REGISTER 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

MR3 (MR37MR30) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

MR3 BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 28

HDTV Enable (MR30) . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Reserved (MR31MR32) . . . . . . . . . . . . . . . . . . . . . . . . . 28
DAC A Control (MR33) . . . . . . . . . . . . . . . . . . . . . . . . . 28
DAC B Control (MR34) . . . . . . . . . . . . . . . . . . . . . . . . . 28
DAC C Control (MR35) . . . . . . . . . . . . . . . . . . . . . . . . . 28
Reserved (MR36MR37) . . . . . . . . . . . . . . . . . . . . . . . . . 28

MODE REGISTER 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

MR4 (MR47MR40) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

MR4 BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . 29

Timing Reset (MR40) . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Reserved (MR41MR47) . . . . . . . . . . . . . . . . . . . . . . . . . 29

MODE REGISTER 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

MR5 (MR57MR50) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

MR5 BIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 29

Reserved (MR50) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
RGB Mode (MR51) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Sync on PrPb (MR52) . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Color Output Swap (MR53) . . . . . . . . . . . . . . . . . . . . . . 29
Reserved (MR54MR57) . . . . . . . . . . . . . . . . . . . . . . . . . 29

DAC TERMINATION AND LAYOUT

CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

PC BOARD LAYOUT CONSIDERATIONS . . . . . . . . . . 30

Supply Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Digital Signal Interconnect . . . . . . . . . . . . . . . . . . . . . . . . 31
Analog Signal Interconnect . . . . . . . . . . . . . . . . . . . . . . . 31
Video Output Buffer and Optional Output Filter . . . . . . . 31

OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . 36

REV. A

ADV7195SPECIFICATIONS

3.3 V SPECIFICATIONS

Parameter

Min

Typ

Max

Unit

Test Conditions

STATIC PERFORMANCE

Resolution (Each DAC)

Bits

Integral Nonlinearity

1.5

LSB

Differential Nonlinearity

0.9

2.0

LSB

DIGITAL OUTPUTS

Output Low Voltage, V

0.4

SINK

= 3.2 mA

Output High Voltage, V

2.4

SOURCE

= 400

µA

Three-State Leakage Current

µA

= 0.4 V

Three-State Output Capacitance

DIGITAL AND CONTROL INPUTS

Input High Voltage, V

Input Low Voltage, V

0.8

0.65

Input Current, I

µA

= 0.0 V or V

Input Capacitance, C

ANALOG OUTPUTS

Full-Scale Output Current

3.92

4.25

4.56

DAC A

2.54

2.83

3.11

DAC B, DAC C

Output Current Range

3.92

4.25

4.56

DAC A

2.39

2.66

2.93

DAC B, DAC C

DAC-to-DAC Matching

1.4

Output Compliance Range, V

1.4

Output Impedance, R

OUT

100

Output Capacitance, C

OUT

VOLTAGE REFERENCE (External)

Reference Range, V

REF

1.112

1.235

1.359

POWER REQUIREMENTS

× Interpolation

HDTV Mode
(With f

CLK

= 7425 MHz)

3, 4

× Interpolation,

× Interpolation, and

HDTV Mode

PLL

6.0

× Interpolation,

× Interpolation, and

HDTV Mode

Power Supply Rejection Ratio

0.01

%/%

NOTES

Guaranteed by characterization.

or the circuit current is the continuous current required to drive the digital core without I

PLL

is the total current required to supply all DACs, including the V

REF

circuitry.

All DACs On.

Specifications subject to change without notice.

= 3.15 V to 3.45 V, V

REF

= 1.235 V, R

SET

= 2470

, R

LOAD

= 300

. All specifications T

MIN

to T

MAX

[0 C

to 70 C] unless otherwise noted, TJ

MAX

= 110 C.)

3 V DYNAMICSPECIFICATIONS

Parameter

Min

Typ

Max

Unit

Luma Bandwidth

13.5

MHz

Chroma Bandwidth

6.75

MHz

Signal-to-Noise Ratio

dB Luma Ramp Unweighted

Chroma/Luma Delay Inequality

Specifications subject to change without notice.

= 3.15 V to 3.45 V, V

REF

= 1.235 V, R

SET

= 2470

, R

LOAD

= 300

. All specifications

MIN

to T

MAX

[0 C to 70 C] unless otherwise noted.)

REV. A

ADV7195

3.3 V TIMINGSPECIFICATIONS

arameter

Min

Typ

Max

Unit

Conditions

MPU PORT

SCLOCK Frequency

400

kHz

SCLOCK High Pulsewidth, t

0.6

µs

SCLOCK Low Pulsewidth, t

1.3

µs

Hold Time (Start Condition), t

0.6

µs

After this Period the 1st Clock Is Generated

Setup Time (Start Condition), t

0.6

µs

Relevant for Repeated Start Condition

Data Setup Time, t

100

SDATA, SCLOCK Rise Time, t

300

SDATA, SCLOCK Fall Time, t

300

Setup Time (Stop Condition), t

0.6

µs

RESET Low Time

100

ANALOG OUTPUTS

Analog Output Delay, t

Analog Output Skew

0.5

CLOCK CONTROL AND PIXEL PORT

CLK

MHz

Progressive Scan Mode

74.25

MHz

HDTV Mode

MHz

ASYNC Timing Mode and 1

× Interpolation

Clock High Time, t

5.0

21.5

Clock Low Time, t

5.0

22.0

Data Setup Time, t

2.0

3.4

Data Hold Time, t

4.5

3.2

Control Setup Time, t

7.0

3.4

Control Hold Time, t

4.0

3.2

Pipeline Delay

Clock Cycles

For 4:4:4 Pixel Input Format at 1

× Oversampling

Pipeline Delay

Clock Cycles

For 4:4:4 or 4:2:2 Pixel Input Format at
2

× Oversampling

NOTES

Guaranteed by characterization.

Output delay measured from 50% point of rising edge of CLOCK to the 50% point of DAC output full-scale transition.

Data: Cb/Cr(90), Cr(90), Y(90); Control:

HSYNC/SYNC, VSYNC/TSYNC, DV.

Specifications subject to change without notice.

= 3.15 V to 3.45 V, V

REF

= 1.235 V, R

SET

= 2470

, R

LOAD

= 300 . All specifications

MIN

to T

MAX

[0 C to 70 C] unless otherwise noted.)

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: ADV7195

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: ADV7195

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: ADV7195