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REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700

www.analog.com

Fax: 781/326-8703

ADV7314

Multiformat 216 MHz

Video Encoder with Six NSV

14-Bit DACs

FEATURES
High Definition Input Formats

8-/10-,16-/20-, 24-/30-Bit (4:2:2, 4:4:4) Parallel YCrCb
Compliant with:

SMPTE 293M (525p)
BTA T-1004 EDTV2 525p
ITU-R BT.1358 (625p/525p)
ITU-R BT.1362 (625p/525p)
SMPTE 274M (1080i) at 30 Hz and 25 Hz
SMPTE 296M (720p)
RGB in 3 10-Bit 4:4:4 Input Format

HDTV RGB Supported:

RGB and RGBHV
Other High Definition Formats Using Async
Timing Mode

High Definition Output Formats

YPrPb Progressive Scan (EIA-770.1, EIA-770.2)
YPrPb HDTV (EIA 770.3)
RGB, RGBHV
CGMS-A (720p/1080i)
Macrovision Rev 1.1 (525p/625p)
CGMS-A (525p)

Standard Definition Input Formats

CCIR-656 4:2:2 8-/10-/16-/20-Bit Parallel Input

Standard Definition Output Formats

Composite NTSC M/N
Composite PAL M/N/B/D/G/H/I, PAL-60
SMPTE 170M NTSC Compatible Composite Video
ITU-R BT.470 PAL Compatible Composite Video
S-Video (Y/C)
EuroScart RGB
Component YPrPb (Betacam, MII, SMPTE/EBU N10)
Macrovision Rev 7.1.L1

CGMS/WSS
Closed Captioning

GENERAL FEATURES
Simultaneous SD and HD Inputs and Outputs
Oversampling up to 216 MHz
Programmable DAC Gain Control
Sync Outputs in All Modes

SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM

CLKIN_A
CLKIN_B

HSYNC

VSYNC

BLANK

Y9Y0

C9C0

S9S0

TIMING

GENERATOR

PLL

V
E
R
S
A

P
L

N
G

INTERFACE

D
E
M
U
X

STANDARD DEFINITION

CONTROL BLOCK

COLOR CONTROL

BRIGHTNESS

DNR

GAMMA

PROGRAMMABLE FILTERS

SD TEST PATTERN

HIGH DEFINITION

CONTROL BLOCK

HD TEST PATTERN

COLOR CONTROL

ADAPTIVE FILTER CTRL

SHARPNESS FILTER

PROGRAMMABLE

RGB MATRIX

14-BIT

DAC

14-BIT

DAC

14-BIT

DAC

14-BIT

DAC

14-BIT

DAC

14-BIT

DAC

ADV7314

GENERAL DESCRIPTION

The ADV

7314 is a high speed, digital-to-analog encoder on a

single monolithic chip. It includes six high speed NSV video
D/A converters with TTL compatible inputs.

The ADV7314 has separate 8-/10-/16-/20-bit input ports that
accept data in high definition and/or standard definition video
format. For all standards, external horizontal, vertical and
blanking signals, or EAV/SAV timing codes control the inser-
tion of appropriate synchronization signals into the digital data
stream and therefore the output signal.

On-Board Voltage Reference
Six 14-Bit NSV Precision Video DACs
2-Wire Serial I

Interface

Dual Input/Output Supply 2.5 V/3.3 V Operation
Analog and Digital Supply 2.5 V
On-Board PLL
64-Lead LQFP Package
Lead (Pb) Free Product

APPLICATIONS
High End DVD
High End PS DVD Recorders/Players
SD/Prog Scan/HDTV Display Devices
SD/HDTV Set Top Boxes
Professional Video Systems

Purchase of licensed I

C components of Analog Devices or one of its

sublicensed Associated Companies conveys a license for the purchaser under
the Philips I

C Patent Rights to use these components in an I

C system,

provided that the system conforms to the I

C Standard Specification as

defined by Philips.

REV. 0

ADV7314

DETAILED FEATURES
High Definition Programmable Features (720p/1080i)

2 Oversampling (148.5 MHz)
Internal Test Pattern Generator

(Color Hatch, Black Bar, Flat Field/Frame)

Fully Programmable YCrCb to RGB Matrix
Gamma Correction
Programmable Adaptive Filter Control
Programmable Sharpness Filter Control
CGMS-A (720p/1080i)

Programmable Features (525p/625p)

8 Oversampling (216 MHz Output)
Internal Test Pattern Generator

(Color Hatch, Black Bar, Flat Frame)

Individual Y and PrPb Output Delay
Gamma Correction
Programmable Adaptive Filter Control
Fully Programmable YCrCb to RGB Matrix
Undershoot Limiter
Macrovision Rev 1.1 (525p/625p)
CGMS-A (525p)

Standard Definition Programmable Features

16 Oversampling (216 MHz)
Internal Test Pattern Generator (Color Bars, Black Bar)
Controlled Edge Rates for Sync, Active Video
Individual Y and PrPb Output Delay
Gamma Correction

Digital Noise Reduction (DNR)
Multiple Chroma and Luma Filters
Luma-SSAFTM Filter with Programmable

Gain/Attenuation

PrPb SSAF
Separate Pedestal Control on Component and

Composite/S-Video Outputs

VCR FF/RW Sync Mode
Macrovision Rev 7.1.L1

CGMS/WSS
Closed Captioning

Standards Directly Supported

Frame Rate

Clk Input

Resolution

(Hz)

(MHz)

Standard

720 480

29.97

ITU-R BT.656

720 576

ITU-R BT.656

720 483

59.94

SMPTE 293M

720 480

59.94

BTA T-1004

720 576

ITU-R BT.1362

1280 720

74.25

SMPTE 296M

1920 1080

74.25

SMPTE 274M

1920 1080

74.25

SMPTE 274M

Other standards are supported in Async Timing mode.

*SMPTE 274M-1998: System no.6

DETAILED FUNCTIONAL BLOCK DIAGRAM

S_HSYNC

S_VSYNC

S_BLANK

CLKIN_A

P_HSYNC

P_VSYNC

P_BLANK

CLKIN_B

HD PIXEL

INPUT

SD PIXEL

INPUT

DEINTER-

LEAVE

TEST

PATTERN

SHARPNESS

AND

ADAPTIVE

FILTER

CONT

LUMA

AND

CHROMA

FILTERS

MODULA-

TION

ROL

Y COLOR

CR COLOR
CB COLOR

4:2:2

4:4:4

TIMING

GENERATOR

TIMING

GENERATOR

TEST

PATTERN

DNR

GAMMA

COLOR

CONTROL

SYNC

INSERTION

CLOCK

CONTROL

AND PLL

UV SSAF

PS 8

HDTV 2

RGB

MATRIX

SD 16

CGMS

WSS

OVER-

SAMPLING

DAC

DEINTER-

LEAVE

REV. 0

ADV7314

ABLE OF CONTENTS

PROGRAMMABLE DAC GAIN CONTROL . . . . . . . . . . 48

Gamma Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
HD Sharpness Filter Control and Adaptive Filter

Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

HD Sharpness Filter and Adaptive Filter Application

Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

SD DIGITAL NOISE REDUCTION . . . . . . . . . . . . . . . . 53

Coring Gain Border . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Coring Gain Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
DNR Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Border Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Block Size Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
DNR Input Select Control . . . . . . . . . . . . . . . . . . . . . . . . 54
DNR Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Block Offset Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

SD ACTIVE VIDEO EDGE . . . . . . . . . . . . . . . . . . . . . . . . 55

SAV/EAV Step Edge Control . . . . . . . . . . . . . . . . . . . . . . 55

BOARD DESIGN AND LAYOUT CONSIDERATIONS . 56

DAC Termination and Layout Considerations . . . . . . . . 56
Video Output Buffer and Optional Output Filter . . . . . . . 56

PC BOARD LAYOUT CONSIDERATIONS . . . . . . . . . . 58

Supply Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Digital Signal Interconnect . . . . . . . . . . . . . . . . . . . . . . . 58
Analog Signal Interconnect . . . . . . . . . . . . . . . . . . . . . . . 58

APPENDIX 1--COPY GENERATION MANAGEMENT

SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
PS CGMS Data Registers 20 . . . . . . . . . . . . . . . . . . . . . 60
SD CGMS Data Registers 20 . . . . . . . . . . . . . . . . . . . . . 60
Function of CGMS Bits . . . . . . . . . . . . . . . . . . . . . . . . . . 60
CGMS Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

APPENDIX 2--SD WIDE SCREEN SIGNALING . . . . . . 62
APPENDIX 3--SD CLOSED CAPTIONING . . . . . . . . . . 63
APPENDIX 4--TEST PATTERNS . . . . . . . . . . . . . . . . . . 64
APPENDIX 5--SD TIMING MODES . . . . . . . . . . . . . . . 66

Mode 0 (CCIR-656)--Slave Option . . . . . . . . . . . . . . . . 66
Mode 0 (CCIR-656)--Master Option . . . . . . . . . . . . . . . 67
Mode 1--Slave Option . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Mode 1--Master Option . . . . . . . . . . . . . . . . . . . . . . . . . 69
Mode 2--Slave Option . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Mode 2--Master Option . . . . . . . . . . . . . . . . . . . . . . . . . 71
Mode 3--Master/Slave Option . . . . . . . . . . . . . . . . . . . . . 72

APPENDIX 6--HD TIMING . . . . . . . . . . . . . . . . . . . . . . 73
APPENDIX 7--VIDEO OUTPUT LEVELS . . . . . . . . . . . 74

HD YPrPb Output Levels . . . . . . . . . . . . . . . . . . . . . . . . 74
RGB Output Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
YPrPb Output Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

APPENDIX 8--VIDEO STANDARDS . . . . . . . . . . . . . . . 80
OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . 82

FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
GENERAL FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM . . . . . . 1
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 1
DETAILED FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
DETAILED FUNCTIONAL BLOCK DIAGRAM . . . . . . . 2
SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
DYNAMIC SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . 5
TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . 6
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . 14
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . 15
PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . 15
TERMINOLOGY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
MPU PORT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . 17
REGISTER ACCESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Register Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Subaddress Register (SR7SR0) . . . . . . . . . . . . . . . . . . . 18

INPUT CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . 31

Standard Definition Only . . . . . . . . . . . . . . . . . . . . . . . . . 31
Progressive Scan Only or HDTV Only . . . . . . . . . . . . . . . 31
Simultaneous Standard Definition

and Progressive Scan or HDTV . . . . . . . . . . . . . . . . . . 32

Progressive Scan At 27 Mhz (Dual Edge)

or 54 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

OUTPUT CONFIGURATION . . . . . . . . . . . . . . . . . . . . . 34
TIMING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

HD Async Timing Mode . . . . . . . . . . . . . . . . . . . . . . . . . 35
HD Timing Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
SD Real-Time Control, Subcarrier Reset,

and Timing Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
SD VCR FF/RW Sync . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Vertical Blanking Interval . . . . . . . . . . . . . . . . . . . . . . . . . 39
SD Subcarrier Frequency Registers . . . . . . . . . . . . . . . . . 39
Square Pixel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

FILTER SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

HD Sinc Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
SD Internal Filter Response . . . . . . . . . . . . . . . . . . . . . . . 41

Typical Performance Characteristics . . . . . . . . . . . . . . . . . . 42
COLOR CONTROLS AND RGB MATRIX . . . . . . . . . . . 46

HD/PS Y Level, Cr Level, Cb Level . . . . . . . . . . . . . . . . 46
HD RGB Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Programming the RGB Matrix . . . . . . . . . . . . . . . . . . . . . 46
SD Luma and Color Control . . . . . . . . . . . . . . . . . . . . . . 46
SD Hue Adjust Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
SD Brightness Control . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
SD Brightness Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Double Buffering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

REV. 0

ADV7314SPECIFICATIONS

= 2.375 V2.625 V, V

= 2.375 V2.625 V; V

DD_IO

= 2.375 V3.6 V,

REF

= 1.235 V, R

SET

= 3040

, R

LOAD

= 150

. All specifications T

MIN

to T

MAX

(0 C to 70 C), unless otherwise noted.)

Parameter

Min

Typ

Max

Unit

Test Conditions

STATIC PERFORMANCE

Resolution

Bits

Integral Nonlinearity

2.0

LSB

Differential Nonlinearity

, +ve

1.0

LSB

Differential Nonlinearity

, ve

3.0

LSB

DIGITAL OUTPUTS

Output Low Voltage, V

0.4 [0.4]

SINK

= 3.2 mA

Output High Voltage, V

2.4 [2.0]

SOURCE

= 400

Three-State Leakage Current

±1.0

= 0.4 V, 2.4 V

Three-State Output Capacitance

DIGITAL AND CONTROL INPUTS

Input High Voltage, V

Input Low Voltage, V

0.8

Input Leakage Current

= 2.4 V

Input Capacitance, C

ANALOG OUTPUTS

Full-Scale Output Current

4.1

4.33

4.6

Output Current Range

4.1

4.33

4.6

DAC-to-DAC Matching

1.0

Output Compliance Range, V

1.0

1.4

Output Capacitance, C

OUT

VOLTAGE REFERENCE

Internal Reference Range, V

REF

1.15

1.235

1.3

External Reference Range, V

REF

1.15

1.235

1.3

REF

Current

±10

POWER REQUIREMENTS

Normal Power Mode

170

SD Only [16 ]

110

PS Only [8 ]

HDTV Only [2 ]

172

190

SD [16 , 10 Bit] + PS [8 , 20 Bit]

DD_IO

1.0

7, 8

Sleep Mode

200

DD_IO

250

Power Supply Rejection Ratio

0.01

%/%

NOTES

Oversampling disabled. Static DAC performance will be improved with increased oversampling ratios.

DNL measures the deviation of the actual DAC output voltage step from the ideal. For +ve DNL, the actual step value lies above the ideal step value; for ve DNL,

the actual step value lies below the ideal step value.

Value in brackets for V

DD_IO

= 2.375 V2.75 V.

External current required to overdrive internal V

REF

, the circuit current, is the continuous current required to drive the digital core.

Guaranteed maximum by characterization.

is the total current required to supply all DACs including the V

REF

circuitry and the PLL circuitry.

All DACs on.

Specifications subject to change without notice.

REV. 0

ADV7314

DYNAMIC SPECIFICATIONS

Parameter

Min

Typ

Max

Unit

Test Conditions

PROGRESSIVE SCAN MODE

Luma Bandwidth

12.5

MHz

Chroma Bandwidth

5.8

MHz

SNR

65.6

Luma Ramp Unweighted

SNR

Flat Field Full Bandwidth

HDTV MODE

Luma Bandwidth

MHz

Chroma Bandwidth

13.75

MHz

STANDARD DEFINITION MODE

Hue Accuracy

0.44

Color Saturation Accuracy

0.20

Chroma Nonlinear Gain

0.84

±%

Referenced to 40 IRE

Chroma Nonlinear Phase

0.2

Chroma/Luma Intermodulation

±%

Chroma/Luma Gain Inequality

97.5

±%

Chroma/Luma Delay Inequality

Luminance Nonlinearity

0.1

±%

Chroma AM Noise

Chroma PM Noise

75.3

Differential Gain

0.09

NTSC

Differential Phase

0.12

NTSC

SNR

63.5

Luma Ramp

SNR

77.7

Flat Field Full Bandwidth

= 2.375 V2.625 V, V

= 2.375 V2.625 V; V

DD_IO

= 2.375 V3.6 V, V

REF

= 1.235 V, R

SET

3040

, R

LOAD

= 150

. All specifications T

MIN

to T

MAX

(0 C to 70 C), unless otherwise noted.)

Specifications subject to change without notice.

REV. 0

ADV7314

TIMING SPECIFICATIONS

= 2.375 V2.625 V, V

= 2.375 V2.625 V; V

DD_IO

= 2.375 V3.6 V, V

REF

= 1.235 V, R

SET

3040

, R

LOAD

= 150

. All specifications T

MIN

to T

MAX

(0 C to 70 C), unless otherwise noted.)

Parameter

Min

Typ

Max

Unit

Conditions

MPU PORT

SCLOCK Frequency

400

kHz

SCLOCK High Pulsewidth, t

0.6

SCLOCK Low Pulsewidth, t

1.3

Hold Time (Start Condition), t

0.6

The first clock is generated after
this period

Setup Time (Start Condition), t

0.6

Relevant for repeated start
condition

Data Setup Time, t

100

SDATA, SCLOCK Rise Time, t

300

SDATA, SCLOCK Fall Time, t

300

Setup Time (Stop Condition), t

0.6

RESET Low Time

100

ANALOG OUTPUTS

Analog Output Delay

Output Skew

CLOCK CONTROL AND PIXEL PORT

CLK

MHz

Progressive Scan Mode

CLK

MHz

HDTV Mode/ASYNC Mode

Clock High Time t

% of one clk cycle

Clock Low Time t

% of one clk cycle

Data Setup Time t

2.0

Data Hold Time t

2.0

SD Output Access Time t

SD Output Hold Time t

5.0

HD Output Access Time t

HD Output Hold Time t

5.0

PIPELINE DELAY

clk cycles

SD [2 , 16 ]

clk cycles

SD Component Mode [16 ]

clk cycles

PS [1 ]

clk cycles

PS [8 ]

clk cycles

HD [2 , 1 ]

NOTES

Guaranteed by characterization.

Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of DAC output full-scale transition.

Data: C [9:0]; Y [9:0], S[9:0]

Control:

P_HSYNC, P_VSYNC, P_BLANK, S_HSYNC, S_VSYNC, S_BLANK.

SD, PS = 27 MHz, HD = 74.25 MHz.

Specifications subject to change without notice.

REV. 0

ADV7314

CLKIN_A

C9C0

P_HSYNC,

P_VSYNC,

P_BLANK

Cb0

Cr0

Cb2

Cr2

Cb4

Cr4

Y9Y0

CONTROL
OUTPUTS

= CLOCK HIGH TIME

= CLOCK LOW TIME

= DATA SETUP TIME

= DATA HOLD TIME

CONTROL

INPUTS

Figure 1. HD Only 4:2:2 Input Mode [Input Mode 010]; PS Only 4:2:2 Input Mode [Input Mode 001]

CLKIN_A

C9C0

P_HSYNC,

P_VSYNC,

P_BLANK

Cb0

Cb1

Cb2

Cb3

Cb4

Cb5

Y9Y0

CONTROL

= CLOCK HIGH TIME

= CLOCK LOW TIME

= DATA SETUP TIME

= DATA HOLD TIME

S9S0

Cr0

Cr1

Cr2

Cr3

Cr5

OUTPUTS

CONTROL

INPUTS

Cr4

Figure 2. HD Only 4:4:4 Input Mode [Input Mode 010]; PS Only 4:4:4 Input Mode [Input Mode 001]

REV. 0

ADV7314

CLKIN_A

C9C0

P_HSYNC,

P_VSYNC,

CONTROL

INPUTS

Y9Y0

CONTROL

OUTPUTS

= CLOCK HIGH TIME

= CLOCK LOW TIME

= DATA SETUP TIME

= DATA HOLD TIME

S9S0

P_BLANK

Figure 3. HD RGB 4:4:4 Input Mode [Input Mode 010]

CONTROL

OUTPUTS

CLKIN_B*

*CLKIN_B MUST BE USED IN THIS PS MODE.

Y9Y

= CLOCK HIGH TIME

= CLOCK LOW TIME

= DATA SETUP TIME

= DATA HOLD TIME

P_HSYNC,

P_VSYNC,

P_BLANK

CONTROL

INPUTS

Cb0 Y0 Cr0 Y1 Crxxx Yxxx

Figure 4. PS 4:2:2 1 10-Bit Interleaved at 27 MHz

HSYNC/VSYNC Input Mode [Input Mode 100]

REV. 0

ADV7314

Cb0 Y0 Cr0 Y1 Crxxx Yxxx

CLKIN_A

Y9Y0

= CLOCK HIGH TIME

= CLOCK LOW TIME

= DATA SETUP TIME

= DATA HOLD TIME

CONTROL

OUTPUTS

P_HSYNC,

P_VSYNC,

P_BLANK

CONTROL

INPUTS

Figure 5. PS 4:2:2 1 10-Bit Interleaved at 54 MHz

HSYNC/VSYNC Input Mode [Input Mode 111]

CLKIN_B*

*CLKIN_B USED IN THIS PS ONLY MODE.

Y9Y

= CLOCK HIGH TIME

= CLOCK LOW TIME

= DATA SETUP TIME

= DATA HOLD TIME

3FF 00 00 XY Cb0 Y0 Cr0 Y1

CONTROL

OUTPUTS

Figure 6. PS Only 4:2:2 1 10-Bit Interleaved at 27 MHz EAV/SAV Input Mode [Input Mode 100]

CLKIN_A

Y9Y0

= CLOCK HIGH TIME

= CLOCK LOW TIME

= DATA SETUP TIME

= DATA HOLD TIME

3FF 00 00 XY Cb0 Y0 Cr0 Y1

NOTE: Y0, Cb0 SEQUENCE AS PER SUBADDRESS 0x01 BIT 1

CONTROL

OUTPUTS

Figure 7. PS Only 4:2:2 1 10-Bit Interleaved at 54 MHz EAV/SAV Input Mode [Input Mode 111]

REV. 0

ADV7314

Cb0

Cr0

Cb2

Cr2

Cb4

Cr4

Cb0

Cr0

Cb1

HD INPUT

SD INPUT

S9S0

CLKIN_A

CLKIN_B

Y9Y0

C9C0

P_HSYNC,

P_VSYNC,

P_BLANK

CONTROL

INPUTS

S_HSYNC,

S_VSYNC,

S_BLANK

CONTROL

INPUTS

Figure 8. HD 4:2:2 and SD (10-Bit) Simultaneous Input Mode [Input Mode 101]; SD Oversampled
[Input Mode 110] HD Oversampled

Cb0

Cr0

Cb2

Cr2

Cb4

Cr4

Cb0

Cr0

Cb1

PS INPUT

SD INPUT

S9S0

CLKIN_A

CLKIN_B

Y9Y0

C9C0

P_HSYNC,

P_VSYNC,

P_BLANK

CONTROL

INPUTS

S_HSYNC,

S_VSYNC,

S_BLANK

CONTROL

INPUTS

Figure 9. PS (4:2:2) and SD (10-Bit) Simultaneous Input Mode [Input Mode 011]

REV. 0

ADV7314

S9S0

Cb0

Cr0

Cb1

CLKIN_A

SD INPUT

CLKIN_B

Y9Y0

PS INPUT

Crxxx Yxxx

Cb0 Y0 Cr0 Y1

P_HSYNC,

P_VSYNC,

P_BLANK

CONTROL

INPUTS

S_HSYNC,

S_VSYNC,

S_BLANK

CONTROL

INPUTS

Figure 10. PS (10-Bit) and SD (10-Bit) Simultaneous Input Mode [Input Mode 100]

CLKIN_A

S9S0/Y9Y0*

Cb0

Cr0

Cb2

Cr2

Cb4

Cr4

CONTROL

OUTPUTS

*SELECTED BY ADDRESS 0x01 BIT 7

IN MASTER/SLAVE MODE

IN SLAVE MODE

S_HSYNC,

S_VSYNC,

S_BLANK

CONTROL

INPUTS

Figure 11. 10-/8-Bit SD Only Pixel Input Mode [Input Mode 000]

REV. 0

ADV7314

CLKIN_A

C9C0

Cb0

Cr0

Cb2

Cr2

*SELECTED BY ADDRESS 0x01 BIT 7

IN MASTER/SLAVE MODE

IN SLAVE MODE

S9S0/Y9Y0*

CONTROL

OUTPUTS

S_HSYNC,

S_VSYNC,

S_BLANK

CONTROL

INPUTS

Figure 12. 20-/16-Bit SD Only Pixel Input Mode [Input Mode 000]

P_HSYNC

P_VSYNC

P_BLANK

Y9Y0

C9C0

Cb0

Cr0

Cr1

Cb1

A = 16 CLK CYCLES FOR 525p
A = 12 CLK CYCLES FOR 626p
A = 44 CLK CYCLES FOR 1080i @ 30Hz, 25Hz
A = 70 CLK CYCLES FOR 720p
AS RECOMMENDED BY STANDARD

B (MIN) = 122 CLK CYCLES FOR 525p
B (MIN) = 132 CLK CYCLES FOR 625p
B (MIN) = 236 CLK CYCLES FOR 1080i @ 30Hz, 25Hz
B (MIN) = 300 CLK CYCLES FOR 720p

Figure 13. HD 4:2:2 Input Timing Diagram

REV. 0

ADV7314

P_HSYNC

P_VSYNC

P_BLANK

Y9Y0

a = 32 CLK CYCLES FOR 525p
a = 24 CLK CYCLES FOR 625p
AS RECOMMENDED BY STANDARD

b(MIN) = 244 CLK CYCLES FOR 525p
b(MIN) = 264 CLK CYCLES FOR 625p

Figure 14. PS 4:2:2 1 10-Bit Interleaved Input Timing Diagram

S_HSYNC

S_VSYNC

S_BLANK

PAL = 24 CLKCYCLES
NTSC = 32 CLKCYCLES

PAL = 24 CLK CYCLES
NTSC = 32 CLK CYCLES

S9S0/Y9Y0*

*SELECTED BY ADDRESS 0x01 BIT 7

Figure 15. SD Timing Input for Timing Mode 1

SDA

SCLK

Figure 16. MPU Port Timing Diagram

REV. 0

ADV7314

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
ADV7314 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.

ABSOLUTE MAXIMUM RATINGS

to AGND . . . . . . . . . . . . . . . . . . . . . . . . +3.0 V to 0.3 V

to GND . . . . . . . . . . . . . . . . . . . . . . . . . +3.0 V to 0.3 V

DD_IO

to IO_GND . . . . . . . . . . . . 0.3 V to V

DD_IO

to +0.3 V

Ambient Operating Temperature (T

) . . . . . . . . . 0

C to 70C

Storage Temperature (T

) . . . . . . . . . . . . . . . 65

C to +150C

Infrared Reflow Soldering (20 secs) . . . . . . . . . . . . . . . . 260

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.

THERMAL CHARACTERISTICS

= 11

C/W

= 47

C/W

The ADV7314 is a Pb-free environmentally friendly product. It is
manufactured using the most up-to-date materials and processes.
The coating on the leads of each device is 100% pure Sn electro-
plate. The device is suitable for Pb-free applications and is able to
withstand surface-mount soldering at up to 255

C [±5C]. In

addition, it is backward compatible with conventional SnPb solder-
ing processes. This means that the electroplated Sn coating can
be soldered with Sn/Pb solder pastes at conventional reflow tem-
peratures of 220

C to 235C.

ORDERING GUIDE

Model

Package Description

Package Option

ADV7314KST

Plastic Quad Flatpack

ST-64

(LQFP)

*Analog output short circuit to any power supply or common can be of an indefi-

nite duration.

REV. 0

ADV7314

PIN CONFIGURATION

PIN 1
IDENTIFIER

TOP VIEW

(Not to Scale)

DD_IO

DGND

S_BLANK
R

SET1

REF

COMP1

DAC A

DAC B

DAC C

AGND

DAC D

DAC E

DAC F

COMP2

SET2

EXT_LF

RESET

ALSB

SCLK

P_HSYNC

P_VSYNC

P_BLANK

C_SCR_TR

CLKIN_A

GND_IO

CLKN_B

DGND

S_HSYN

S_VSYNC

ADV7314

LQFP

PIN FUNCTION DESCRIPTIONS

Pin No.

Mnemonic

Input/Output

Function

11, 57

DGND

Digital Ground.

AGND

Analog Ground.

CLKIN_A

Pixel Clock Input for HD (74.25 MHz Only, PS Only (27 MHz), SD Only
(27 MHz).

CLKIN_B

Pixel Clock Input. Requires a 27 MHz reference clock for Progressive Scan
mode or a 74.25 MHz (74.1758 MHz) reference clock in HDTV mode. This
clock is only used in dual modes.

36, 45

COMP2, COMP1 O

Compensation Pin for DACs. Connect 0.1

mF capacitor from COMP pin

to V

DAC A

CVBS/Green/Y/Y Analog Output.

DAC B

Chroma/Blue/U/Pb Analog Output.

DAC C

Luma/Red/V/Pr Analog Output.

DAC D

In SD Only Mode: CVBS/Green/Y Analog Output.
In HD Only mode and simultaneous HD/SD mode: Y/Green [HD] Analog
Output.

DAC E

In SD Only Mode: Luma/Blue/U Analog Output.
In HD Only mode and simultaneous HD/SD mode: Pr/Red Analog Output.

DAC F

In SD Only Mode: Chroma/Red/V Analog Output.
In HD Only mode and simultaneous HD/SD mode: Pb/Blue [HD] Analog
Output.

P_HSYNC

Video Horizontal Sync Control Signal for HD in Simultaneous SD/HD Mode
and HD.

P_VSYNC

Video Vertical Sync Control Signal for HD in Simultaneous SD/HD Mode
and HD.

P_BLANK

Video Blanking Control Signal for HD in Simultaneous SD/HD Mode and HD.

S_BLANK

I/O

Video Blanking Control Signal for SD only.

REV. 0

ADV7314

Pin No.

Mnemonic

Input/Output

Function

S_HSYNC

I/O

Video Horizontal Sync Control Signal for SD Only.

S_VSYNC

I/O

Video Vertical Sync Control Signal for SD Only.

29, 1213

Y9Y0

SD or Progressive Scan/HDTV Input Port for Y Data. Input port for inter-
leaved progressive scan data. The LSB is set up on Pin Y0. For 8-bit data
input, LSB is set up on Y2.

1418, 2630

C9C0

Progressive Scan/HDTV Input Port. In 4:4:4 Input mode, this port is used for
the Cb[Blue/U] data. The LSB is set up on Pin C0. For 8-bit data input, LSB
is set up on C2.

5155, 5862

S9S0

SD or Progressive Scan/HDTV Input Port for Cr [Red/V] Data in 4:4:4 Input
Mode. LSB is set up on Pin S0. For 8-bit data input, LSB is set up on S2.

RESET

This input resets the on-chip timing generator and sets the ADV7314 into
default register setting.

RESET is an active low signal.

35, 47

SET2

, R

SET1

A 3040

W resistor must be connected from this pin to AGND and is used

to control the amplitudes of the DAC outputs.

SCLK

C Port Serial Interface Clock Input.

SDA

I/O

C Port Serial Data Input/Output.

ALSB

TTL Address Input. This signal sets up the LSB of the I

C address. When

this pin is tied low, the I

C filter is activated, reducing noise on the I

interface.

DD_IO

Power Supply for Digital Inputs and Outputs.

10, 56

Digital Power Supply.

Analog Power Supply.

REF

I/O

Optional External Voltage Reference Input for DACs or Voltage Reference
Output (1.235 V).

EXT_LF

External Loop Filter for the Internal PLL.

RTC_SCR_TR

Multifunctional Input. Real-time control (RTC) input, timing reset input,
subcarrier reset input.

This input pin must be tied high (V

DD_IO

) for the ADV7314 to interface

over the I

C port.

GND_IO

Digital Input/Output Ground.

TERMINOLOGY

Standard definition video, conforming to ITU-R BT.601/656.

High definition video, such as progressive scan or HDTV.

Progressive scan video, conforming to SMPTE 293M, ITU-R BT.1358, BTA T-1004 EDTV2, BTA 1362

HDTV

High definition television video, conforming to SMPTE 274M or SMPTE 296M.

YCrCb

SD, HD, or PS component digital video.

YPrPb

HD, SD, or PS component analog video.

REV. 0

ADV7314

MPU PORT DESCRIPTION

The ADV7314 supports a 2-wire serial (I

C compatible) micro-

processor bus driving multiple peripherals. Two inputs, serial
data (SDA) and serial clock (SCL), carry information between
any device connected to the bus. Each slave device is recognized
by a unique address. The ADV7314 has four possible slave
addresses for both read and write operations. These are unique
addresses for each device and are illustrated in Figure 17. The
LSB sets either a read or write operation. Logic 1 corresponds
to a read operation, while Logic 0 corresponds to a write opera-
tion. A1 is set by setting the ALSB pin of the ADV7314 to
Logic 0 or Logic 1. When ALSB is set to 1, there is greater
input bandwidth on the I

C lines, which allows high speed data

transfers on this bus. When ALSB is set to 0, there is reduced
input bandwidth on the I

C lines, which means that pulses of

less than 50 ns will not pass into the I

C internal controller.

This mode is recommended for noisy systems.

ADDRESS
CONTROL

SET UP BY

ALSB

READ/WRITE

CONTROL

0 WRITE
1 READ

Figure 17. ADV7314 Slave Address = D4h

To control the various devices on the bus, the following protocol
must be followed. First, the master initiates a data transfer by
establishing a start condition, defined by a high-to-low transition
on SDA, while SCL remains high. This indicates that an address/
data stream will follow. All peripherals respond to the start
condition and shift the next eight bits (7-bit address + R/

W bit).

The bits are transferred from MSB down to LSB. The periph-
eral that recognizes the transmitted address responds by pulling
the data line low during the ninth clock pulse. This is known as
an acknowledge bit. All other devices withdraw from the bus at

this point and maintain an idle condition. The idle condition is
when the device monitors the SDA and SCL lines waiting for
the start condition and the correct transmitted address. The
R/

W bit determines the direction of the data.

A Logic 0 on the LSB of the first byte means that the master
will write information to the peripheral. A Logic 1 on the LSB
of the first byte means that the master will read information
from the peripheral.

The ADV7314 acts as a standard slave device on the bus. The
data on the SDA pin is eight bits wide, supporting the 7-bit
addresses plus the R/

W bit. It interprets the first byte as the

device address and the second byte as the starting subaddress.
There is a subaddress auto-increment facility, which allows data
to be written to or read from registers in ascending subaddress
sequence starting at any valid subaddress. A data transfer is
always terminated by a stop condition. The user can also access
any unique subaddress register on a one-by-one basis without
having to update all the registers.

Stop and start conditions can be detected at any stage during
the data transfer. If these conditions are asserted out of sequence
with normal read and write operations, then these cause an
immediate jump to the idle condition. During a given SCL high
period, the user should issue only one start condition, one stop
condition, or a single stop condition followed by a single start
condition. If an invalid subaddress is issued by the user, the
ADV7314 will not issue an acknowledge and will return to the
idle condition. If in auto-increment mode the user exceeds the
highest subaddress, the following action will be taken:

1. In read mode, the highest subaddress register contents

will continue to be output until the master device issues a
no-acknowledge. This indicates the end of a read. A
no-acknowledge condition is when the SDA line is not
pulled low on the ninth pulse.

2. In write mode, the data for the invalid byte will not be loaded

into any subaddress register, a no-acknowledge will be issued
by the ADV7314, and the part will return to the idle condition.

REV. 0

ADV7314

Before writing to the subcarrier frequency registers, the ADV7314
must have been reset at least once since power-up.

The four subcarrier frequency registers must be updated start-
ing with subcarrier frequency register 0 through subcarrier
frequency register 3. The subcarrier frequency will not update
until the last subcarrier frequency register byte has been received
by the ADV7314.

Figure 18 illustrates an example of the data transfer for a write
sequence and the start and stop conditions.

Figure 19 shows bus write and read sequences.

REGISTER ACCESS

The MPU can write to or read from all of the registers of the
ADV7314 except the subaddress registers, which are write-only
registers. The subaddress register determines which register the

SDATA

SCLOCK

START ADRR R/

W ACK SUBADDRESS ACK

DATA

ACK

STOP

17

Figure 18. Bus Data Transfer

WRITE

SEQUENCE

READ

SEQUENCE

SLAVE ADDR

A(S)

SUB ADDR

A(S)

DATA

A(S)

DATA

A(S)

SLAVE ADDR

A(S)

SUB ADDR

A(S) S

SLAVE ADDR

A(S)

DATA

A(M)

A(M) P

S = START BIT
P = STOP BIT

A(S) = ACKNOWLEDGE BY SLAVE
A(M) = ACKNOWLEDGE BY MASTER

A(S) = NO-ACKNOWLEDGE BY SLAVE

A(M) = NO-ACKNOWLEDGE BY MASTER

LSB = 0

LSB = 1

Figure 19. Write and Read Sequence

next read or write operation accesses. All communications with
the part through the bus start with an access to the subaddress
register. A read/write operation is then performed from/to the
target address, which increments to the next address until a stop
command on the bus is performed.

Register Programming

The following section describes the functionality of each register.
All registers can be read from as well as written to unless other-
wise stated.

Subaddress Register (SR7SR0)

The communications register is an 8-bit write-only register. After
the part has been accessed over the bus and a read/write opera-
tion is selected, the subaddress is set up. The subaddress register
determines to/from which register the operation takes place.

REV. 0

ADV7314

SR7-
SR0

Register

Bit Description

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Register Setting

Sleep Mode off

FCh

Sleep Mode on

PLL on

PLL off

DAC F off

DAC F on

DAC E off

DAC E on

DAC D off

DAC D on

DAC D off

DAC C on

DAC B off

DAC B on

DAC A off

DAC A on

Disabled

Enabled

Cb clocked on rising edge

Y clocked on rising edge

Reserved

38h

Must be set if the phase
delay between the two
input clocks is <9.25 ns or
>27.75 ns.

Only if two input
clocks are used

SD input only

PS input only

HDTV input only

SD and PS [20-bit]

SD and PS [10-bit]

SD and HDTV [SD
oversampled

SD and HDTV [HDTV
oversampled]

PS only [at 54 MHz]

10-bit data on S Bus

10-bit data on Y Bus

SD Only. 10-Bit/
20-Bit Input mode

PLL and Oversampling Control. This control
allows the internal PLL cct to be powered down
and the oversampling to be switched off.

Sleep Mode. With this control enabled, the current
consumption is reduced to A level. All DACs and
the internal PLL cct are disabled. I

C registers can

be read from and written to in sleep mode.

Clock Edge

Y/S Bus Swap

DAC B. Power on/off.

DAC A. Power on/off.

BTA T-1004 or 1362 Compatibility

Clock Align

Input Mode

Mode Select
Register

01h

00h

Power
Mode
Register

DAC E. Power on/off.

Only for PS
interleaved input at
27 MHz

DAC D. Power on/off.

DAC F. Power on/off.

DAC C. Power on/off.

Only for PS dual
edge clk mode

REV. 0

ADV7314

SR7-
SR0

Register

Bit Description

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1 Bit 0

Register Setting

Reset Value

02h

Mode Register 0

Reserved

Zero must be written to
these bits

20h

Test Pattern Black Bar

Disabled

Enabled

RGB Matrix

Disable Programmable
RGB Matrix

Enable Programmable
RGB Matrix

Sync on RGB

No Sync

Sync on all RGB outputs

RGB/YUV Output

RGB component outputs

YUV component outputs

SD Sync

No Sync output

Output SD syncs on
S_HSYNC output, S_VSYNC
output,

S_BLANK output

HD Sync

No Sync output

Output HD syncs on
P_HSYNC output, P_VSYNC
output,

P_BLANK output

03h

RGB Matrix 0

LSB for GY

03h

04h

RGB Matrix 1

LSB for RV

F0h

LSB for BU

LSB for GV

LSB for GU

05h

RGB Matrix 2

Bit 92 for GY

4Eh

06h

RGB Matrix 3

Bit 92 for GU

0Eh

07h

RGB Matrix 4

Bit 92 for GV

24h

08h

RGB Matrix 5

Bit 92 for BU

92h

09h

RGB Matrix 6

Bit 92 for RV

7Ch

0Ah

DAC A,B,C Output
Level

Positive Gain to DAC Output
Voltage

00h

+0.018%

0.036%

...

......

+7.382%

+7.5%

Negative Gain to DAC Output
Voltage

7.5%

7.382%

7.364%

...

.......

0.018%

0Bh

DAC D,E,F Output
Level

Positive Gain to DAC Output
Voltage

00h

+0.018%

0.036%

...

......

+7.382%

+7.5%

Negative Gain to DAC Output
Voltage

7.5%

7.382%

7.364%

...

.......

0.018%

0Ch

Note 3

00h

0Dh

Note 3

00h

0Eh

Reserved

00h

0Fh

Reserved

00h

11h, Bit 2 must
be enabled also

For more detail, refer to Appendix 7.

For more detail on the programmable output levels, refer to the Programmable DAC Gain Control section.

Must be written to after power-up/reset.

REV. 0

ADV7314

SR7-
SR0

Register

Bit Description

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Register Setting

Reset Values

10h

HD Output Standard

EIA770.2 output

00h

EIA770.1 output

Output levels for full input
range

Reserved

HD Input Control Signals

HSYNC, VSYNC, BLANK

EAV/SAV codes

Async timing mode

Reserved

HD 625p

525p

625p

HD 720p

1080i

720p

BLANK Polarity

BLANK active high

BLANK active low

HD Macrovision for 525p/625p

Macrovision off

Macrovision on

11h

HD Pixel Data Valid

Pixel data valid off

00h

Pixel data valid on

Reserved

HD Test Pattern Enable

HD test pattern off

HD test pattern on

HD Test Pattern Hatch/Field

Hatch

Field/Frame

HD VBI Open

Disabled

Enabled

HD Undershoot Limiter

Disabled

11 IRE

6 IRE

1.5 IRE

HD Sharpness Filter

Disabled

Enabled

HD Mode
Register 2

HD Mode
Register 1

REV. 0

ADV7314

NOTES

When set to 0, the line and field counters automatically wrap around at the end of the field/frame of the standard selected. When set to 1 , the field/line

counters are free running and wrap around when external sync signals indicate so.

Adaptive Filter mode is not available in PS only @ 54 MHz input mode.

SR7-
SR0

Register

Bit Description

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Register Setting

Reset Value

12h

0 clk cycle

00h

1 clk cycle

2 clk cycle

3 clk cycle

4 clk cycle

0 clk cycle

1 clk cycle

2 clk cycle

3 clk cycle

4 clk cycle

HD CGMS

Disabled

Enabled

HD CGMS CRC

Disabled

Enabled

13h

HD Cr/Cb Sequence

Cb after falling edge of

HSYNC

4Ch

Cr after falling edge of

HSYNC

Reserved

0 must be written to this bit

8-bit input

10-bit input

Disabled

Enabled

Reserved

0 must be written to this bit

HD Chroma SSAF

Disabled

Enabled

HD Chroma Input

4:4:4

4:2:2

Disabled

Enabled

14h

HD Mode
Register 5

HD Timing Reset

A low-high-low transition resets the
internal HD timing counters

00h

1080i Frame Rate

30 Hz/2200 total samples/line

25 Hz/2640 total samples/line

Reserved

0 should be written to these bits

Field Input

VSYNC Input

Lines/Frame

Update Field/line counter

Field/line counter free running

15h

Reserved

0 must be written to this bit

00h

HD RGB Input

Disabled

Enabled

HD Sync on PrPb

Disabled

Enabled

HD Color DAC Swap

DAC E = Pb; DAC F = Pr

DAC E = Pr; DAC F = Pb

HD Gamma Curve A/B

Gamma Curve A

Gamma Curve B

HD Gamma Curve
Enable

Disabled

Enabled

HD Adaptive Filter
Mode

Mode A

Mode B

HD Adaptive Filter
Enable

Disabled

Enabled

HD Double Buffering

HD Mode
Register 4

HD Mode
Register 6

HD Mode
Register 3

VSYNC/Field

Input

Sinc Filter on DAC D,
E, F

HD Input Format

HD with Respect to
Falling Edge of

HSYNC

HD Y Delay with
Respect to Falling Edge
of

HSYNC

REV. 0

ADV7314

SR7-
SR0

Register

Bit Description

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1

Bit 0

Reset Value

1 6 h

HD Y Level

Y color value

A0h

1 7 h

HD Cr Level

Cr color value

8 0 h

1 8 h

HD Cb Level

Cb color value 8 0 h

1 9 h

Reserved

0 0 h

1Ah

Reserved

0 0 h

1 B h

Reserved

0 0 h

1Ch

Reserved

0 0 h

1Dh

Reserved

0 0 h

1 E h

Reserved

0 0 h

1 F h

Reserved

0 0 h

Disabled

Enabled

Mode A

Mode B

Disabled

Enabled

2 0 h

Gain A = 0

0 0 h

Gain A = +1

......

Gain A = +7

Gain A = 8

......

Gain A = 1

Gain B = 0

Gain B = +1

.......

Gain B = +7

Gain B = 8

........

Gain B = 1

21h

HD CGMS

HD CGMS Data Bits

C19

C18

C17

C16

CGMS 1916

0 0 h

2 2 h

HD CGMS

HD CGMS Data Bits

C15

C14

C13

C12

C11

C10

CGMS 158

0 0 h

2 3 h

HD CGMS

HD CGMS Data Bits

CGMS 70

0 0 h

2 4 h

HD Gamma A

HD Gamma Curve A Data Points

0 0 h

2 5 h

HD Gamma A

HD Gamma Curve A Data Points

0 0 h

2 6 h

HD Gamma A

HD Gamma Curve A Data Points

0 0 h

2 7 h

HD Gamma A

HD Gamma Curve A Data Points

0 0 h

2 8 h

HD Gamma A

HD Gamma Curve A Data Points

0 0 h

2 9 h

HD Gamma A

HD Gamma Curve A Data Points

0 0 h

2Ah

HD Gamma A

HD Gamma Curve A Data Points

0 0 h

2 B h

HD Gamma A

HD Gamma Curve A Data Points

0 0 h

2Ch

HD Gamma A

HD Gamma Curve A Data Points

0 0 h

2Dh

HD Gamma A

HD Gamma Curve A Data Points

0 0 h

2 E h

HD Gamma B

HD Gamma Curve B Data Points

B 0

0 0 h

2 F h

HD Gamma B

HD Gamma Curve B Data Points

B 1

0 0 h

3 0 h

HD Gamma B

HD Gamma Curve B Data Points

B 2

0 0 h

3 1 h

HD Gamma B

HD Gamma Curve B Data Points

B 3

0 0 h

3 2 h

HD Gamma B

HD Gamma Curve B Data Points

B 4

0 0 h

3 3 h

HD Gamma B

HD Gamma Curve B Data Points

B 5

0 0 h

3 4 h

HD Gamma B

HD Gamma Curve B Data Points

B 6

0 0 h

3 5 h

HD Gamma B

HD Gamma Curve B Data Points

B 7

0 0 h

3 6 h

HD Gamma B

HD Gamma Curve B Data Points

B 8

0 0 h

37h

HD Gamma B

HD Gamma Curve B Data Points

B 9

0 0 h

HD Sharpness Filter Gain Value A

HD Sharpness Filter Gain Value B

1 5 h

HD Mode
Register 6

HD Gamma Curve Enable

HD Adaptive Filter Mode

HD Adaptive Filter Enable

HD Sharpness
Filter Gain

NOTES

Used for internal test pattern only.

Programmable gamma correction is not available in PS only mode @ 54 MHz operation.

REV. 0

ADV7314

SR7SR0

Register

Bit Description

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Register Setting

Value

38h

HD Adaptive Filter

Gain A = 0

00h

Gain 1

Gain A = +1

......

Gain A = +7

Gain A = 8

......

Gain A = 1

Gain B = 0

Gain B = +1

.......

Gain B = +7

Gain B = 8

........

Gain B = 1

39h

Gain A = 0

00h

Gain A = +1

......

Gain A = +7

Gain A = 8

......

Gain A = 1

Gain B = 0

Gain B = +1

.......

Gain B = +7

Gain B = 8

........

Gain B = 1

3Ah

Gain A = 0

00h

Gain A = +1

......

Gain A = +7

Gain A = 8

......

Gain A = 1

Gain B = 0

Gain B = +1

.......

Gain B = +7

Gain B = 8

........

Gain B = 1

HD Adaptive Filter
Threshold A

Threshold A

00h

HD Adaptive Filter
Threshold B

Threshold B

00h

HD Adaptive Filter
Threshold C

Threshold C

00h

HD Adaptive Filter
Gain 1 Value A

HD Adaptive Filter
Gain 1 Value B

HD Adaptive Filter
Threshold C Value

HD Adaptive Filter
Gain 3 Value B

HD Adaptive Filter
Threshold B Value

HD Adaptive Filter
Threshold A Value

3Bh

3Ch

3Dh

HD Adaptive Filter
Gain 3

HD Adaptive Filter
Gain 2 Value A

HD Adaptive Filter
Gain 2 Value B

HD Adaptive Filter
Gain 2

HD Adaptive Filter
Gain 3 Value A

REV. 0

ADV7314

SR7
SR0

Register

Bit Description

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset
Value

3Eh

Reserved

00h

3Fh

Reserved

00h

40h

SD Mode Register 0 SD Standard

NTSC

00h

PAL B, D, G, H, I

PAL M

PAL N

SD Luma Filter

LPF NTSC

LPF PAL

Notch NTSC

Notch PAL

SSAF Luma

Luma CIF

Luma QCIF

Reserved

SD Chroma Filter

1.3 MHz

0.65 MHz

1.0 MHz

2.0 MHz

Reserved

Chroma CIF

Chroma QCIF

3.0 MHz

41h

Reserved

00h

42h

SD Mode Register 1 SD UV SSAF

Disabled

08h

Enabled

SD DAC Output 1

0
1

SD DAC Output 2

SD Pedestal

Disabled

Enabled

SD Square Pixel

Disabled

Enabled

SD VCR FF/RW Sync

Disabled

Enabled

SD Pixel Data Valid

Disabled

Enabled

Disabled

Enabled

43h

SD Mode Register 2 SD Pedestal YPrPb Output

No pedestal on YUV

00h

7.5 IRE pedestal on YUV

SD Output Levels Y

Y = 700/300 mV

Y = 714/286 mV

SD Output Levels PrPb

700 mV p-p[PAL]; 1000 mV
p-p[NTSC]

700 mV p-p

1000 mV p-p

648 mV p-p

SD VBI Open

Disabled

Enabled

SD CC Field Control

CC disabled

CC on odd field only

CC on even field only

CC on both fields

Reserved

Refer to Output
Configuration section

SD SAV/EAV Step Edge
Control

REV. 0

ADV7314

SR7
SR0

Register

Bit Description

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting

Reset
Value

4 4 h

SD Mode Register SD VSYNC3H

Disabled

0 0 h

VSYNC = 2.5 lines [PAL]

VSYNC = 3 lines [NTSC]

SD RTC/TR/SCR

Genlock disabled

Subcarrier reset

Timing reset

RTC enabled

SD Active Video Length

720 pixels

710 [NTSC]/702 [PAL]

SD Chroma

Chroma enabled

Chroma disabled

SD Burst

Enabled

Disabled

SD Color Bars

Disabled

Enabled

SD DAC Swap

0
1

4 5 h

Reserved

0 0 h

4 6 h

Reserved

0 0 h

4 7 h

SD Mode Register SD PrPb Scale

Disabled

0 0 h

Enabled

SD Y Scale

Disabled

Enabled

SD Hue Adjust

Disabled

Enabled

SD Brightness

Disabled

Enabled

SD Luma SSAF Gain

Disabled

Enabled

Reserved

0 must be written to

Reserved

0 must be written to

Reserved

0 must be written to

4 8 h

SD Mode Register Reserved

0 0 h

Reserved

0 must be written to

SD Double Buffering

Disabled

Enabled

SD Input Format

8-bit input

16-bit input

10-bit input

20-bit input

SD Digital Noise

Disabled

Enabled

SD Gamma Control

Disabled

Enabled

SD Gamma Curve

Gamma Curve A

Gamma Curve B

4 9 h

SD Mode Register SD Undershoot Limiter

Disabled

0 0 h

11 IRE

6 IRE

1.5 IRE

Reserved

0 must be written to

SD Black Burst Output

Disabled

Enabled

SD Chroma Delay

Disabled

4 clk cycles

8 clk cycles

Reserved

0 must be written to

Reserved

0 must be written to

DAC B = Luma, DAC C = Chroma
DAC B = Chroma, DAC C = Luma

*See Figure 31, RTC Timing and Connections.

REV. 0

ADV7314

SR7-
SR0

Register

Bit Description

Bit 7

Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1

Bit 0 Register Setting

Reset
Value

4Ah

SD Timing Register 0

SD Slave/Master Mode

Slave mode

0 8 h

Master mode

SD Timing Mode

Mode 0

Mode 1

Mode 2

Mode 3

BLANK Input

Enabled

Disabled

SD Luma Delay

No delay

2 clk cycles

4 clk cycles

6 clk cycles

SD Min. Luma Value

40 IRE

7.5 IRE

SD Timing Reset

A low-high-low transistion will
reset the internal SD timing
c o u n t e r s

4 B h

SD Timing Register 1

HSYNC Width

Ta = 1 clk cycle

0 0 h

Ta = 4 clk cycles

Ta = 16 clk cycles

Ta = 128 clk cycles

HSYNC to VSYNC delay

Tb = 0 clk cycle

Tb = 4 clk cycles

Tb = 8 clk cycles

Tb = 18 clk cycles

Tc = Tb

Tc = Tb + 32 s

1 clk cycle

4 clk cycles

16 clk cycles

128 clk cycles

0 clk cycles

1 clk cycle

2 clk cycles

3 clk cycles

4Ch

SD F

Subcarrier Frequency Bit 70

1 6 h

4Dh

SD F

Subcarrier Frequency Bit 158

7Ch

4 E h

SD F

Subcarrier Frequency Bit 2316

F 0 h

4 F h

SD F

Subcarrier Frequency Bit 3124

2 1 h

5 0 h

SD F

Phase

Subcarrier Phase Bit 92

0 0 h

5 1 h

SD Closed Captioning

Extended Data on Even
Fields

Extended Data Bit 70

0 0 h

5 2 h

SD Closed Captioning

Extended Data on Even
Fields

Extended Data Bit 158

0 0 h

5 3 h

SD Closed Captioning

Data on Odd Fields

Data Bit 70

0 0 h

5 4 h

SD Closed Captioning

Data on Odd Fields

Data Bit 158

0 0 h

5 5 h

SD Pedestal Register 0

Pedestal on Odd Fields

0 0 h

5 6 h

SD Pedestal Register 1

Pedestal on Odd Fields

0 0 h

5 7 h

SD Pedestal Register 2

Pedestal on Even Fields 17

0 0 h

5 8 h

SD Pedestal Register 3

Pedestal on Even Fields 25

0 0 h

Setting any of these bits to 1 will
disable pedestal on the line
number indicated by the bit
settings.

HSYNC to VSYNC Rising

Edge Delay [Mode 1
only]

VSYNC Width

[Mode 2 only]

HSYNC to Pixel Data
Adjust

LINE 313

LINE 314

LINE 1

HSYNC

VSYNC

Figure 20. Timing Register 1 in PAL Mode

REV. 0

ADV7314

SR7
SR0

Register

Bit Description

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting

Reset Value

5 9 h

SD CGMS/WSS 0

SD CGMS Data

CGMS Data Bits C19C16

0 0 h

SD CGMS CRC

Disabled

Enabled

SD CGMS on Odd

Disabled

Enabled

SD CGMS on Even

Disabled

Enabled

SD WSS

Disabled

Enabled

5Ah

SD CGMS/WSS 1

SD CGMS/WSS Data

CGMS Data Bits C13C8 or
WSS Data Bits C13C8

0 0 h

CGMS Data Bits C15C14

0 0 h

5 B h

SD CGMS/WSS 2

SD CGMS/WSS Data

CGMS/WSS Data Bits C7C0 0 0 h

5Ch

SD LSB Register

SD LSB for Y Scale

SD Y Scale Bit 10

SD LSB for U Scale

SD U Scale Bit 10

SD LSB for V Scale

SD V Scale Bit 10

SD LSB for F

Phase

Subcarrier Phase Bits 10

5Dh

SD Y Scale

SD Y Scale Value

SD Y Scale Bit 72

0 0 h

5Eh SD

Scale

SD V Scale Value

SD V Scale Bit 72

0 0 h

5 F h

SD U Scale

SD U Scale Value

SD U Scale Bit 72

0 0 h

6 0 h

SD Hue Register

SD Hue Adjust Value

SD Hue Adjust Bit 70

0 0 h

6 1 h

SD Brightness Value

SD Brightness Bit 60

0 0 h

SD Blank WSS Data

Disabled

Line 23

Enabled

6 2 h

SD Luma SSAF

4 dB

0 0 h

0 dB

+4 dB

6 3 h

SD DNR 0

Coring Gain Border

No gain

0 0 h

+1/16 [1/8]

+2/16 [2/8]

+3/16 [3/8]

+4/16 [4/8]

+5/16 [5/8]

+6/16 [6/8]

+7/16 [7/8]

+8/16 [1]

Coring Gain Data

No gain

+1/16 [1/8]

+2/16 [2/8]

+3/16 [3/8]

+4/16 [4/8]

+5/16 [5/8]

+6/16 [6/8]

+7/16 [7/8]

+8/16 [1]

6 4 h

SD DNR 1

DNR Threshold

0 0 h

...

Border Area

2 pixels

4 pixels

Block Size Control

8 pixels

16 pixels

In DNR
Mode the
values in
brackets
apply

SD Brightness/
WSS

SD Luma SSAF
G a i n / A t t e n u a t i o n

REV. 0

ADV7314

SR7-
SR0 Register

Bit Description

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting

Reset Value

6 5 h

SD DNR 2

DNR Input Select

Filter A

0 0 h

Filter B

Filter C

Filter D

DNR Mode

DNR mode

DNR Sharpness mode

DNR Block Offset

0 pixel offset

1 pixel offset

...

14 pixel offset

15 pixel offset

6 6 h

SD Gamma A

SD Gamma Curve A Data Points

0 0 h

6 7 h

SD Gamma A

SD Gamma Curve A Data Points

0 0 h

6 8 h

SD Gamma A

SD Gamma Curve A Data Points

0 0 h

6 9 h

SD Gamma A

SD Gamma Curve A Data Points

0 0 h

6Ah SD Gamma A

SD Gamma Curve A Data Points

0 0 h

6 B h SD Gamma A

SD Gamma Curve A Data Points

0 0 h

6Ch SD Gamma A

SD Gamma Curve A Data Points

0 0 h

6Dh SD Gamma A

SD Gamma Curve A Data Points

0 0 h

6 E h SD Gamma A

SD Gamma Curve A Data Points

0 0 h

6 F h SD Gamma A

SD Gamma Curve A Data Points

0 0 h

7 0 h

SD Gamma B

SD Gamma Curve B Data Points

B 0

0 0 h

7 1 h

SD Gamma B

SD Gamma Curve B Data Points

B 1

0 0 h

7 2 h

SD Gamma B

SD Gamma Curve B Data Points

B 2

0 0 h

7 3 h

SD Gamma B

SD Gamma Curve B Data Points

B 3

0 0 h

7 4 h

SD Gamma B

SD Gamma Curve B Data Points

B 4

0 0 h

7 5 h

SD Gamma B

SD Gamma Curve B Data Points

B 5

0 0 h

7 6 h

SD Gamma B

SD Gamma Curve B Data Points

B 6

0 0 h

7 7 h

SD Gamma B

SD Gamma Curve B Data Points

B 7

0 0 h

7 8 h

SD Gamma B

SD Gamma Curve B Data Points

B 8

0 0 h

7 9 h

SD Gamma B

SD Gamma Curve B Data Points

B 9

0 0 h

7Ah SD Brightness Detect SD Brightness Value

Read only

7 B h Field Count Register Field Count

Read only

Reserved

0 must be written to this

Reserved

0 must be written to this

Reserved

0 must be written to this

Revision Code

Read Only

7Ch 10-Bit Input

Must write this for 10 bit
Data Input (SD, PS, HD)

0 0 h

REV. 0

ADV7314

SR7-
SR0

Register

Bit Description

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Register Setting

Reset Value

7Dh

Reserved

7 E h

Reserved

7 F h

Reserved

8 0 h

M a c r o v i s i o n

MV Control Bits

0 0 h

8 1 h

M a c r o v i s i o n

MV Control Bits

0 0 h

8 2 h

M a c r o v i s i o n

MV Control Bits

0 0 h

8 3 h

M a c r o v i s i o n

MV Control Bits

0 0 h

8 4 h

M a c r o v i s i o n

MV Control Bits

0 0 h

8 5 h

M a c r o v i s i o n

MV Control Bits

0 0 h

8 6 h

M a c r o v i s i o n

MV Control Bits

0 0 h

8 7 h

M a c r o v i s i o n

MV Control Bits

0 0 h

8 8 h

M a c r o v i s i o n

MV Control Bits

0 0 h

8 9 h

M a c r o v i s i o n

MV Control Bits

0 0 h

8Ah

M a c r o v i s i o n

MV Control Bits

0 0 h

8 B h

M a c r o v i s i o n

MV Control Bits

0 0 h

8Ch

M a c r o v i s i o n

MV Control Bits

0 0 h

8Dh

M a c r o v i s i o n

MV Control Bits

0 0 h

8 E h

M a c r o v i s i o n

MV Control Bits

0 0 h

8 F h

M a c r o v i s i o n

MV Control Bits

0 0 h

9 0 h

M a c r o v i s i o n

MV Control Bits

0 0 h

9 1 h

M a c r o v i s i o n

MV Control Bit

0 0 h

0 must be written to

b i t s

REV. 0

ADV7314

INPUT CONFIGURATION

When 10-bit input data is applied, the following bits must be
set to 1:

Address 0x7C, Bit 1 (Global 10-Bit Enable)

Address 0x13, Bit 2 (HD 10-Bit Enable)

Address 0x48, Bit 4 (SD 10-Bit Enable)

Note that the ADV7314 defaults to simultaneous standard
definition and progressive scan on power-up. Address[01h]:
Input Mode = 011.

Standard Definition Only
Address [01h] Input Mode = 000

The 8-bit/10-bit multiplexed input data is input on Pins S9S0
(or Y9Y0, depending on Register Address 0x01, Bit7), with S0
being the LSB in 10-bit input mode. Input standards supported
are ITU-R BT.601/656.

In 16-bit input mode, the Y pixel data is input on Pins S9S2,
and CrCb data is input on Pins C9C2. The 27 MHz clock
input must be input on the CLKIN_A pin.

Input sync signals are optional and are input on the

S_VSYNC,

S_ HSYNC, and S_BLANK pins.

MPEG2

DECODER

S_VSYNC
S_HSYNC
S_BLANK

CLKIN_A

S[9:0] or Y[9:0]*

27MHz

YCrCb

ADV7314

*Selected by Address 0x01 Bit 7

Figure 21 . SD Only Input Mode

Progressive Scan Only or HDTV Only
Address [01h] Input Mode 001 or 010, Respectively

YCrCb Progressive Scan, HDTV, or any other HD YCrCb data
can be input in 4:2:2 or 4:4:4. In 4:2:2 input mode, the Y data
is input on Pins Y9Y0 and the CrCb data on Pins C9C0. In
4:4:4 input mode, Y data is input on Pins Y9Y0, Cb data on
Pins C9C0, and Cr data on Pins S9S0.

If the YCrCb data does not conform to SMPTE 293M (525p),
ITU-R BT.1358M (625p), SMPTE 274M (1080i), SMPTE
296M (720p), or BTA T-1004/1362, the async timing mode must
be used.

RGB data can be input in 4:4:4 format in PS Input mode only
or in HDTV Input mode only when HD RGB input is enabled.
G data is input on Pins Y9Y0, R data on S9S0, and B data
on C9C0.

The clock signal must be input on the CLKIN_A pin.

MPEG2

DECODER

P_VSYNC
P_HSYNC
P_BLANK

CLKIN_A

C[9:0]

S[9:0]

Y[9:0]

INTERLACED

PROGRESSIVE

YCrCb

27MHz

ADV7314

Figure 22. Progressive Scan Input Mode

REV. 0

ADV7314

Simultaneous Standard Definition and
Progressive Scan or HDTV
Address [01h]: Input Mode 011(SD 40-Bit, PS 20-Bit) or
101 (SH and HD, SD Oversampled), 110 (SD and HD, HD
Oversampled)

YCrCb PS, HDTV, or any other HD data must be input in
4:2:2 format. In 4:2:2 input mode, the HD Y data is input on
Pins Y9Y0 and the HD CrCb data on C9C0.

If PS 4:2:2 data is interleaved onto a single 10-bit bus, Y9Y0 are
used for the input port. The input data is to be input at 27 MHz
with the data clocked on the rising and falling edge of the input
clock. The input mode register at Address 01h is set accordingly.

If the YCrCb data does not conform to SMPTE 293M (525p),
ITU-R BT.1358M (625p), SMPTE 274M (1080i), SMPTE
296M (720p), or BTA T-1004, the Async Timing mode must
be used.

The 8-bit or 10-bit standard definition data must be compliant
to ITU-R BT.601/656 in 4:2:2 format.

Standard definition data is input on Pins S9S0, with S0 being the
LSB. Using 8-bit input format, the data is input on Pins S9S2.

The clock input for SD must be input on CLKIN_A, and the
clock input for HD must be input on CLKIN_B.

Synchronization signals are optional. SD syncs are input on pins
S_VSYNC, S_ HSYNC, and S_BLANK.

HD syncs are input on Pins

P_VSYNC, P_ HSYNC, P_BLANK.

S_VSYNC
S_HSYNC
S_BLANK

CLKIN_A

P_VSYNC
P_HSYNC
P_BLANK

CLKIN_B

MPEG2

DECODER

27MHz

YCrCb

INTERLACED TO
PROGRESSIVE

CrCb

27MHz

S[9:0]

C[9:0]

Y[9:0]

ADV7314

Figure 23. Simultaneous PS and SD Input

S_VSYNC
S_HSYNC
S_BLANK

CLKIN_A

P_VSYNC
P_HSYNC
P_BLANK

CLKIN_B

SDTV

DECODER

27MHz

YCrC b

HDTV

DECODER

CrCb

74.25MHz

1080 i

720 p

S[9:0]

C[9:0]

Y[9:0]

ADV7314

Figure 24. Simultaneous HD and SD Input

If in simultaneous SD/HD input mode, the two clock phases
differ by less than 9.25 ns or more than 27.75 ns, the CLOCK

ALIGN bit [Address 01h, Bit 3] must be set accordingly. If the
application uses the same clock source for both SD and PS, the
CLOCK ALIGN bit must be set since the phase difference
between both inputs is less than 9.25 ns.

DELAY

9.25ns OR

DELAY

27.75ns

CLKIN_A

CLKIN_B

Figure 25. Clock Phase with Two Input Clocks

Progressive Scan at 27 MHz (Dual Edge) or 54 MHz
Address [01h]: Input Mode 100 OR 111, Respectively

YCrCb progressive scan data can be input at 27 MHz or 54
MHz. The input data is interleaved onto a single 8-/10-bit bus
and is input on Pins Y9Y0. When a 27 MHz clock is supplied,
the data is clocked in on the rising and falling edge of the input
clock and CLOCK EDGE [Address 01h, Bit 1] must be set
accordingly.

The following figures show the possible conditions. (a) Cb data
on the rising edge and (b) Y data on the rising edge.

3FF

Cr0

CLKIN_B

Y9Y0

Cb0

Figure 26a. Clock Edge Address 01h, Bit 1
Should Be Set to 0

3FF

Cb0

Cr0

CLKIN_B

Y9Y0

Figure 26b. Clock Edge Address 01h, Bit 1
Should Be Set to 1

With a 54 MHz clock, the data is latched on the every rising edge.

PIXEL INPUT

DATA

3FF

Cb0

Cr0

CLKIN

Figure 26c. Input Sequence in PS Bit Interleaved
Mode, EAV/SAV Followed by Cb0 Data

MPEG2

DECODER

P_VSYNC
P_HSYNC
P_BLANK

CLKIN_A

Y[9:0]

INTERLACED

PROGRESSIVE

YCrCb

27MHz OR

54MHz

YCrCb

ADV7314

Figure 27. 1 10-Bit PS at 27 MHz or 54 MHz

REV. 0

ADV7314

Table I provides an overview of all possible input configurations.

Table I. Input Configurations

Input Format

Total Bits

Input Video

Input Pins

Subaddress

Register Setting

ITU-R BT.656

01h

00h

48h

00h

01h

00h

48h

10h

S9-S2 [MSB = S9]

01h

00h

CrCb

Y9-Y2 [MSB = Y9]

48h

08h

S9-S0 [MSB = S9]

01h

00h

CrCb

Y9-Y0 [MSB = Y9]

48h

18h

YCrCb

Y9-Y2 [MSB = Y9]

01h

80h

48h

00h

YCrCb

Y9-Y0 [MSB = Y9]

01h

80h

48h

10h

PS Only

01h

10h

13h

40h

01h

10h

13h

44h

01h

70h

13h

40h

70h

10h

13h

44h

Y9-Y2 [MSB = Y9]

01h

10h

CrCb

C9-C2 [MSB = C9]

13h

40h

Y9-Y0 [MSB = Y9]

01h

10h

CrCb

C9-C0 [MSB = C9]

13h

44h

4:4:4

Y9-Y2 [MSB = Y9]

01h

10h

C9-C2 [MSB = C9]

13h

00h

S9-S2 [MSB = S9]

4:4:4

Y9-Y0 [MSB = Y9]

01h

10h

C9-C0 [MSB = C9]

13h

04h

S9-S0 [MSB = S9]

HDTV Only

4:2:2

Y9-Y2 [MSB = Y9]

01h

20h

CrCb

C9-Y2 [MSB = C9]

13h

40h

4:2:2

Y9-Y0 [MSB = Y9]

01h

20h

CrCb

C9-C0 [MSB = C9]

13h

44h

4:4:4

Y9-Y2 [MSB = Y9]

01h

20h

C9-Y2 [MSB = C9]

13h

00h

S9-S2 [MSB = S9]

4:4:4

Y9-Y0 [MSB = Y9]

01h

20h

C9-C0 [MSB = C9]

13h

04h

S9-S0 [MSB = S9]

4:4:4

Y9-Y2 [MSB = Y9]

01h

10h or 20h

C9-C2 [MSB = C9]

13h

00h

S9-S2 [MSB = S9]

15h

02h

4:4:4

Y9-Y0 [MSB = Y9]

01h

10h or 20h

C9-C0 [MSB = C9]

13h

04h

S9-S0 [MSB = S9]

15h

02h

4:2:2

YCrCb

S9-S2 [MSB = S9]

01h

40h

13h

40h

48h

00h

4:2:2

YCrCb

S9-S0 [MSB = S9]

01h

40h

13h

44h

48h

10h

4:2:2

YCrCb

S9-S2 [MSB = S9]

01h

30h or 50h or 60h

4:2:2

Y9-Y2 [MSB = Y9]

13h

60h

CrCb

C9-C2 [MSB = C9]

48h

00h

4:2:2

YCrCb

S9-S0 [MSB = S9]

01h

30h or 50h or 60h

4:2:2

Y9-Y0 [MSB = Y9]

13h

60h

CrCb

C9-C0 [MSB = C9]

48h

10h

YCrCb

S9-S2 [MSB = S9]

YCrCb

S9-S0 [MSB = S9]

8 [54 MHz clock]

YCrCb

Y9-Y2 [MSB = Y9]

YCrCb

Y9-Y0 [MSB = Y9]

YCrCb

Y9-Y2 [MSB = Y9]

4:2:2

YCrCb

Y9-Y0 [MSB = Y9]

HD RGB

4:2:2

10 [54 MHz clock]

YCrCb

Y9-Y2 [MSB = Y9]

ITU-R BT.656 and PS

4:2:2

YCrCb

Y9-Y0 [MSB = Y9]

ITU-R BT.656 and PS

ITU-R BT.656 and PS or HDTV

4:2:2

8 [27 MHz clock]

4:2:2

10 [27 MHz clock]

4:2:2

REV. 0

ADV7314

OUTPUT CONFIGURATION

These tables show which output signals are assigned to the DACs when the control bits are set accordingly.

Table II. Output Configuration in SD Only Mode

RGB/YUV
Output 02h,
Bit 5

SD DAC
Output 1
42h, Bit 2

SD DAC
Output 2
42h, Bit 1

DAC A

DAC B

DAC C

DAC D

DAC E

DAC F

CVBS

Luma

Chroma

CVBS

Luma Chroma

Luma

Chroma

CVBS

Luma Chroma

CVBS

Luma

Chroma

CVBS

Luma Chroma

Luma

Chroma

CVBS

Luma Chroma

Table above with all Luma/Chroma instances swapped

Table as above

Luma/Chroma Swap 44h, Bit 7

Table III. Output Configuration in HD/PS Only Mode

HD Input
Format

HD RGB
Input 15h,
Bit 1

RGB/YPrP
b Output
02h, Bit 5

HD Color
Swap 15h,
Bit 3

DAC A

DAC B DAC C DAC D

DAC E

DAC F

YCrCb 4:2:2

N/A

YCrCb 4:2:2

N/A

YCrCb 4:2:2

N/A

YCrCb 4:2:2

N/A

YCrCb 4:4:4

N/A

YCrCb 4:4:4

N/A

YCrCb 4:4:4

N/A

YCrCb 4:4:4

N/A

RGB 4:4:4

N/A

RGB 4:4:4

N/A

RGB 4:4:4

N/A

RGB 4:4:4

N/A

Table IV. Output Configuration in Simultaneous SD and HD/PS Mode

Input Formats

RGB/YPrP
b Output
02h, Bit 5

HD Color
Swap 15h,
Bit 3

DAC A

DAC B

DAC C

DAC D

DAC E

DAC F

ITU-R BT.656 and
HD YCrCb in 4:2:2

CVBS

Luma

Chroma

ITU-R BT.656 and
HD YCrCb in 4:2:2

CVBS

Luma

Chroma

ITU-R BT.656 and
HD YCrCb in 4:2:2

CVBS

Luma

Chroma

ITU-R BT.656 and
HD YCrCb in 4:2:2

CVBS

Luma

Chroma

REV. 0

ADV7314

TIMING MODES

HD Async Timing Mode
[Subaddress 10h, Bit 3,2]

For any input data that does not conform to the standards
selectable in input mode, Subaddress 01h, asynchronous tim-
ing mode can be used to interface to the ADV7314. Timing
control signals for

HSYNC, VSYNC, and BLANK have to be

programmed by the user. Macrovision and programmable

oversampling rates are not available in async timing mode. When
using async mode, the PLL must be turned off [Subaddress
00h, Bit 1 = 1].

Figures 28a and 28b show an example of how to program the
ADV7314 to accept a different high definition standard other
than SMPTE 293M, SMPTE 274M, SMPTE 296M, or
ITU-R BT.1358. The truth table in Table V must be followed
when programming the control signals in async timing mode.

CLK

ACTIVE VIDEO

PROGRAMMABLE
INPUT TIMING

ANALOG
OUTPUT

243

1920

HORIZONTAL SYNC

P_HSYNC

P_VSYNC

P_BLANK

SET ADDRESS 10h,

BIT 6 TO 1

Figure 28a. Async Timing Mode--Programming Input Control Signals for SMPTE 295M Compatibility

ACTIVE VIDEO

HORIZONTAL SYNC

CLK

P_HSYNC

P_VSYNC

P_BLANK

SET ADDRESS 10h,

BIT 6 TO 1

ANALOG OUTPUT

Figure 28b. Async Timing Mode--Programming Input Control Signals for Bilevel Sync Signal

REV. 0

ADV7314

Table V. Async Timing Mode Truth Table

Reference in

P_HSYNC

P_VSYNC

P_BLANK*

Figures 28a and 28b

1 -> 0

0 or 1

50% point of falling edge of tri-level horizontal sync signal

0 -> 1

0 or 1

25% point of rising edge of tri-level horizontal sync signal

0 -> 1

0 or 1

50% point of falling edge of tri-level horizontal sync signal

0 or 1

0 -> 1

50% start of active video

0 or 1

1 -> 0

50% end of active video

*When async timing mode is enabled, P_BLANK [Pin 25] becomes an active high input. P_BLANK is set to active low at Address 10h, Bit 6.

For standards that do not require a tri-sync level,

P_BLANK must be tied low at all times.

HD Timing Reset
[Subaddress 14h, Bit 0]

A timing reset is achieved in setting the HD timing reset control
bit at Address 14h from 0 to 1. In this state, the horizontal and
vertical counters will remain reset. On setting this bit back to 0,
the internal counters will commence counting again.

The minimum time the pin has to be held high is one clock
cycle, otherwise this reset signal might not be recognized. This
timing reset applies to the HD timing counters only.

REV. 0

ADV7314

SD Real-Time Control, Subcarrier Reset, and Timing Reset
[Subaddress 44h, Bit 2,1]

Together with the RTC_SCR_TR pin and SD Mode Register 3,
the ADV7314 can be used in timing reset mode, subcarrier phase
reset mode, or RTC mode.

Timing Reset Mode

A timing reset is achieved in a low-to-high transition on the
RTC_SCR_TR pin (Pin 31). In this state, the horizontal and
vertical counters will remain reset. On releasing this pin (set to
low), the internal counters will commence counting again, the
field count will start on Field 1, and the subcarrier phase will
be reset.

The minimum time the pin has to be held high is one clock
cycle; otherwise this reset signal might not be recognized.
This timing reset applies to the SD timing counters only.

Subcarrier Phase Reset

A low-to-high transition on the RTC_SCR_TR pin (Pin 31) will
reset the subcarrier phase to zero on the field following the
subcarrier phase reset when the SD RTC/TR/SCR control bits
at Address 44h are set to 01.

This reset signal will have to be held high for a minimum of one
clock cycle.

Since the field counter is not reset, it is recommended that the
reset signal should be applied in Field 7 [PAL] or Field 3
[NTSC]. The reset of the phase will then occur on the next
field, i.e., Field 1, being lined up correctly with the internal
counters. The field count register at Address 7Bh can be used to
identify the number of the active field.

RTC Mode

In RTC mode, the ADV7314 can be used to lock to an external
video source. The real-time control mode allows the ADV7314
to automatically alter the subcarrier frequency to compensate
for line length variations. When the part is connected to a device
that outputs a digital datastream in the RTC format (such as an
ADV7183A video decoder, see Figure 31), the part will auto-
matically change to the compensated subcarrier frequency on a
line by line basis. This digital datastream is 67 bits wide and the
subcarrier is contained in Bits 0 to 21. Each bit is two clock
cycles long. 00h should be written into all four subcarrier
frequency registers when using this mode.

DISPLAY

NO TIMING RESET APPLIED

TIMING RESET APPLIED

START OF FIELD 4 OR 8

PHASE = FIELD 4 OR 8

PHASE = FIELD 1

TIMING RESET PULSE

307

310

307

313

320

DISPLAY

START OF FIELD 1

Figure 29. Timing Reset Timing Diagram

NO F

RESET APPLIED

PHASE = FIELD 4 OR 8

307

310

313

320

DISPLAY

START OF FIELD 4 OR 8

RESET APPLIED

RESET PULSE

PHASE = FIELD 1

307

310

313

320

DISPLAY

START OF FIELD 4 OR 8

Figure 30. Subcarrier Reset Timing Diagram

REV. 0

ADV7314

Reset Sequence

A reset is activated with a high-to-low transition on the

RESET pin

[Pin 33] according to the timing specifications. The ADV7314
will revert to the default output configuration. Figure 32 illus-
trates the

RESET sequence timing.

SD VCR FF/RW Sync
[Subaddress 42h, Bit 5]

In DVD record applications where the encoder is used with a
decoder, the VCR FF/RW Sync control bit can be used for non-
standard input video, i.e., in fast forward or rewind modes.

In fast forward mode, the sync information at the start of a new
field in the incoming video usually occurs before the correct
number of lines/field are reached. In rewind mode, this sync

signal usually occurs after the total number of lines/field are
reached. Conventionally this means that the output video will
have corrupted field signals, one generated by the incoming
video and one when the internal lines/field counters reach the
end of a field.

When the VCR FF/RW sync control is enabled [Subaddress 42h,
Bit 5] the lines/field counters are updated according to the
incoming

VSYNC signal and the analog output matches the

incoming

VSYNC signal.

This control is available in all slave timing modes except Slave
Mode 0.

LCC1

GLL

P19P10

ADV7183A

VIDEO

DECODER

COMPOSITE

VIDEO

e.g., VCR

OR CABLE

CLKIN_A

RTC_SCR_TR

DAC A

DAC B

DAC C

DAC D

DAC E

DAC F

Y9-Y0/S9S0*

RTC

LOW

H/L TRANSITION

COUNT START

128

TIME SLOT 01

14 BITS

SUBCARRIER

PHASE

PLL INCREMENT

VALID

SAMPLE

INVALID

SAMPLE

8/LINE

LOCKED

CLOCK

6768

4 BITS

RESERVED

SEQUENCE

BIT

RESET

BIT

RESERVED

5 BITS

RESERVED

ADV7314

NOTES

PLL INCREMENT IS 22 BITS LONG. VALUE LOADED INTO ADV7314 F

DDS REGISTER IS F

PLL INCREMENTS BITS 21:0

PLUS BITS 0:9 OF SUBCARRIER FREQUENCY REGISTERS. ALL ZEROS SHOULD BE WRITTEN TO THE SUBCARRIER FREQUENCY REGISTERS
OF THE ADV7314.

SEQUENCE BIT
PAL: 0 = LINE NORMAL, 1 = LINE INVERTED; NTSC: 0 = NO CHANGE

SEQUENCE BIT
RESET ADV7314 DDS

*SELECTED BY REGISTER
ADDRESS 01h BIT 7

Figure 31. RTC Timing and Connections

XXXXXX

OFF

DIGITAL TIMING SIGNALS SUPPRESSED

VALID VIDEO

TIMING ACTIVE

RESET

DIGITAL TIMING

DACs

A, B, C

PIXEL DATA

VALID

Figure 32.

RESET Timing Sequence

REV. 0

ADV7314

Vertical Blanking Interval

The ADV7314 accepts input data that contains VBI data [e.g.,
CGMS, WSS, VITS] in SD and HD modes.

For SMPTE 293M [525p] standards, VBI data can be inserted
on Lines 13 to 42 of each frame, or Lines 6 to 43 for ITU-R
BT.1358 [625p] standard. For SD NTSC, this data can be
present on Lines 10 to 20, and in PAL on Lines 7 to 22.

If VBI is disabled [Address 11h, Bit 4 for HD; Address 43h,
Bit 4 for SD], VBI data is not present at the output and the
entire VBI is blanked. These control bits are valid in all master
and slave modes.

In Slave Mode 0, if VBI is enabled, the blanking bit in the EAV/
SAV code is overwritten; it is possible to use VBI in this timing
mode as well.

In Slave mode 1 or 2, the

BLANK control bit must be set to

enabled [Address 4Ah, Bit 3] to allow VBI data to pass through
the ADV7314; otherwise the ADV7314 automatically blanks the
VBI to standard.

If CGMS is enabled and VBI is disabled, the CGMS data will
nevertheless be available at the output.

SD Subcarrier Frequency Registers
[Subaddress 4Ch4Fh]

Four 8-bit registers are used to set up the subcarrier frequency.
The value of these registers is calculated in using the following
equation:

Subcarrier Frequency

gister

Subcarrier Frequency Value

MHz clk cycles in one video line

# 27

For example, in NTSC mode,

Subcarrier FrequencyValue

= ÊËÁ

¯
~ ¥

227 5

1716

569408542

SD F

Refer to the MPU Port Description section for more details on
how to access the subcarrier frequency registers.

Square Pixel Timing [Register 42h, Bit 4]

In square pixel mode, the following timing diagrams apply.

F
F

0
0

X
Y

8
0

1
0

8
0

1
0

F
F

0
0

F
F

A
B

8
0

1
0

8
0

1
0

F
F

0
0

X
Y

C
b

Y C

C
b

EAV CODE

SAV CODE

ANCILLARY DATA

(HANC)

4 CLOCK

272 CLOCK

1280 CLOCK

4 CLOCK

344 CLOCK

1536 CLOCK

END OF ACTIVE

VIDEO LINE

START OF ACTIVE

VIDEO LINE

ANALOG

VIDEO

INPUT PIXELS

NTSC/PAL M SYSTEM

(525 LINES/60Hz)

PAL SYSTEM

(625 LINES/50Hz)

Figure 33. EAV/SAV Embedded Timing

FIELD

PIXEL

DATA

PAL = 44 CLOCK CYCLES

NTSC = 44 CLOCK CYCLES

PAL = 136 CLOCK CYCLES

NTSC = 208 CLOCK CYCLES

HSYNC

BLANK

Figure 34. Active Pixel Timing

REV. 0

ADV7314

FILTER SECTION

Table VI shows an overview of the programmable filters avail-
able on the ADV7314.

Table VI. Selectable Filters of the ADV7314

Filter

Subaddress

SD Luma LPF NTSC

40h

SD Luma LPF PAL

40h

SD Luma Notch NTSC

40h

SD Luma Notch PAL

40h

SD Luma SSAF

40h

SD Luma CIF

40h

SD Luma QCIF

40h

SD Chroma 0.65 MHz

40h

SD Chroma 1.0 MHz

40h

SD Chroma 1.3 MHz

40h

SD Chroma 2.0 MHz

40h

SD Chroma 3.0 MHz

40h

SD Chroma CIF

40h

SD Chroma QCIF

40h

SD UV SSAF

42h

HD Chroma Input

13h

HD Sinc Filter

13h

HD Chroma SSAF

13h

HD Sinc Filter

FREQUENCY (MHz)

0.5

GAIN (dB)

0.4

0.1

0.2

0.3

0.4

0.3

0.2

0.1

Figure 35. HD Sinc Filter Enabled

FREQUENCY (MHz)

0.5

GAIN (dB)

0.4

0.1

0.2

0.3

0.4

0.3

0.2

0.1

Figure 36. HD Sinc Filter Disabled

REV. 0

ADV7314

SD Internal Filter Response
[Subaddress 40h; Subaddress 42, Bit 0]

The Y filter supports several different frequency responses includ-
ing two low-pass responses, two notch responses, an extended
(SSAF) response, with or without gain boost/attenuation, a CIF
response and a QCIF response. The UV filter supports several
different frequency responses, including six low-pass responses,
a CIF response and a QCIF response, as can be seen in the
Typical Performance Characteristics graphs.

If SD SSAF gain is enabled, there are 12 possible responses in
the range from 4 dB to +4 dB [Subaddress 47h, Bit 4]. The
desired response can be chosen by the user by programming the
correct value via the I

C [Subaddress 62h]. The variation of

frequency responses can be seen in the Typical Performance
Characteristics graphs.

Table VII. Internal Filter Specifications

Pass-Band Ripple 3 dB Bandwidth

Filter

(dB)

(MHz)

Luma LPF NTSC

0.16

4.24

Luma LPF PAL

0.1

4.81

Luma Notch NTSC

0.09

2.3/4.9/6.6

Luma Notch PAL

0.1

3.1/5.6/6.4

Luma SSAF

0.04

6.45

Luma CIF

0.127

3.02

Luma QCIF

Monotonic

1.5

Chroma 0.65 MHz

Monotonic

0.65

Chroma 1.0 MHz

Monotonic

Chroma 1.3 MHz

0.09

1.395

Chroma 2.0 MHz

0.048

2.2

Chroma 3.0 MHz

Monotonic

3.2

Chroma CIF

Monotonic

0.65

Chroma QCIF

Monotonic

0.5

Pass-band ripple refers to the maximum fluctuations from the 0 dB response in

the pass band, measured in dB. The pass band is defined to have 0 Hz to fc
(Hz) frequency limits for a low-pass filter, 0 Hz to f1 (Hz) and f2 (Hz) to
infinity for a notch filter, where fc, f1, f2 are the 3 dB points.

3 dB bandwidth refers to the 3 dB cutoff frequency.

In addition to the chroma filters listed in Table VII, the ADV7314
contains an SSAF filter specifically designed for and applicable
to the color difference component outputs, U and V.

This filter has a cutoff frequency of about 2.7 MHz and 40 dB
at 3.8 MHz, as can be seen in Figure 37. This filter can be
controlled with Address 42h, Bit 0.

If this filter is disabled, the selectable chroma filters shown in
Table VII can be used for the CVBS or Luma/Chroma signal.

FREQUENCY (MHz)

GAIN (dB)

10

30

50

60

20

40

EXTENDED UV FILTER MODE

Figure 37. UV SSAF Filter

REV. 0

ADV7314Typical Performance Characteristics

FREQUENCY (MHz)

PROG SCAN Pr/Pb RESPONSE. LINEAR INTERP FROM 4:2:2 TO 4:4:4

GAIN (dB)

70

60

50

40

30

20

10

80

200

100

120

140

160

180

TPC 1. PS UV 8 Oversampling Filter--Linear

FREQUENCY (MHz)

Y RESPONSE IN PS OVERSAMPLING MODE

GAIN (dB)

70

60

50

40

30

20

10

80

200

100

120

140

160

180

TPC 2. PS Y 8 Oversampling Filter

FREQUENCY (MHz)

Pr/Pb RESPONSE IN HDTV OVERSAMPLING MODE

GAIN (dB)

70

60

50

40

30

20

10

80

140

100

120

TPC 3. HDTV UV 2 Oversampling Filter

FREQUENCY (MHz)

PROG SCAN Pr/Pb RESPONSE. SSAF INTERP FROM 4:2:2 TO 4:4:4

GAIN (dB)

70

60

50

40

30

20

10

80

200

100

120

140

160

180

TPC 4. PS UV 8 Oversampling Filter--SSAF

FREQUENCY (MHz)

Y PASSBAND IN PS OVERSAMPLING MODE

GAIN (dB)

2.5

2.0

1.5

1.0

0.5

1.0

3.0

TPC 5. PS Y 8 Oversampling Filter--Pass Band

FREQUENCY (MHz)

Y RESPONSE IN HDTV OVERSAMPLING MODE

GAIN (dB)

70

60

50

40

30

20

10

80

140

100

120

TPC 6. HDTV Y 2 Oversampling Filter

REV. 0

ADV7314

FREQUENCY (MHz)

MAGNITUDE (dB)

10

30

50

60

70

20

40

TPC 7. Luma NTSC Low-Pass Filter

FREQUENCY (MHz)

MAGNITUDE (dB)

10

30

50

60

70

20

40

TPC 8. Luma NTSC Notch Filter

FREQUENCY (MHz)

Y RESPONSE IN SD OVERSAMPLING MODE

GAIN (dB)

50

80

100

120

140

160

180

200

10

40

60

70

20

30

TPC 9. Y--16 Oversampling Filter

FREQUENCY (MHz)

MAGNITUDE (dB)

10

30

50

60

70

20

40

TPC 10. Luma PAL Low-Pass Filter

FREQUENCY (MHz)

MAGNITUDE (dB)

10

30

50

60

70

20

40

TPC 11. Luma PAL Notch Filter

FREQUENCY (MHz)

MAGNITUDE (dB)

10

30

50

60

70

20

40

TPC 12. Luma SSAF

Filter up to 12 MHz

REV. 0

ADV7314

FREQUENCY (MHz)

MAGNITUDE (dB)

12

10

TPC 13. Luma SSAF Filter--Programmable Responses

FREQUENCY (MHz)

MAGNITUDE (dB)

TPC 14. Luma SSAF Filter--Programmable Attenuation

FREQUENCY (MHz)

MAGNITUDE (dB)

10

30

50

60

70

20

40

TPC 15. Luma QCIF LP Filter

FREQUENCY (MHz)

MAGNITUDE (dB)

TPC 16. Luma SSAF Filter--Programmable Gain

FREQUENCY (MHz)

MAGNITUDE (dB)

10

30

50

60

70

20

40

TPC 17. Luma CIF LP Filter

FREQUENCY (MHz)

MAGNITUDE (dB)

10

30

50

60

70

20

40

TPC 18. Chroma 3.0 MHz LP Filter

REV. 0

ADV7314

FREQUENCY (MHz)

MAGNITUDE (dB)

10

30

50

60

70

20

40

TPC 19. Chroma 2.0 MHz LP Filter

FREQUENCY (MHz)

MAGNITUDE (dB)

10

30

50

60

70

20

40

TPC 20. Chroma 1.0 MHz LP Filter

FREQUENCY (MHz)

MAGNITUDE (dB)

10

30

50

60

70

20

40

TPC 21. Chroma CIF LP Filter

FREQUENCY (MHz)

MAGNITUDE (dB)

10

30

50

60

70

20

40

TPC 22. Chroma 1.3 MHz LP Filter

FREQUENCY (MHz)

MAGNITUDE (dB)

10

30

50

60

70

20

40

TPC 23. Chroma 0.65 MHz LP Filter

FREQUENCY (MHz)

MAGNITUDE (dB)

10

30

50

60

70

20

40

TPC 24. Chroma QCIF LP Filter

REV. 0

ADV7314

COLOR CONTROLS AND RGB MATRIX

HD/PS Y Level, Cr Level, Cb Level
[Subaddress 16h18h]

Three 8-bit registers at Address 16h, 17h, 18h are used to program
the output color of the internal HD test pattern generator, whether
it is the lines of the cross hatch pattern or the uniform field test
pattern. They are not functional as color controls on external
pixel data input. For this purpose, the RGB matrix is used.

The standard used for the values for Y and the color difference
signals to obtain white, black, and the saturated primary and
complementary colors conforms to the ITU-R BT.6014 standard.

Table VIII shows sample color values to be programmed into
the color registers when Output Standard Selection is set to
EIA 770.2.

Table VIII. Sample Color Values for
EIA770.2 Output Standard Selection

Sample

Color Y

Color CR

Color CB

Color

Value

White

235 (EB)

128 (80)

Black

16 (10)

128(80)

128 (80)

Red

81 (51)

240 (F0)

90 (5A)

Green

145 (91)

34 (22)

54 (36)

Blue

41 (29)

110 (6E)

240 (F0)

Yellow

210 (D2)

146 (92)

16 (10)

Cyan

170 (AA)

16 (10)

166 (A6)

Magenta

106 (6A)

222 (DE)

202 (CA)

HD RGB Matrix
[Subaddress 03h09h]

When the programmable RGB matrix is disabled [Address 02h,
Bit 3], the internal RGB matrix takes care of all YCrCb to YUV
or RGB scaling according to the input standard programmed
into the device.

When the programmable RGB matrix is enabled, the color
components are converted according to the 1080i standard
[SMPTE 274M]:

Y' = 0.2126R' + 0.7152 G' + 0.0722 B'

CR' = [0.5/(1 0.0722)] (B'Y')
CR' = [0.5/(1 0.2126)] (R'Y')

This is reflected in the preprogrammed values for GY = 138Bh,
GU = 93h, GV = 3B, BU = 248h, RV = 1F0.

If another input standard is used, the scale values for GY, GU,
GV, BU, and RV have to be adjusted according to this input
standard. The user must consider that the color component
conversion might use different scale values. For example,
SMPTE 293M uses the following conversion:

Y' = 0.299 R' + 0.587 G' + 0.114 B'

CB' = [0.5 / (1 0.114)] (B'Y')
CR' = [0.5 / (1 0.299)] (R'Y')

The programmable RGB matrix can be used to control the HD
output levels in cases where the video output does not conform
to standard due to altering the DAC output stages such as ter-
mination resistors. The programmable RGB matrix is used for
external HD data and is not functional when the HD test pattern
is enabled.

Programming the RGB Matrix

The RGB matrix should be enabled [Address 02h, Bit 3], the
output should be set to RGB [Address 02h, Bit 5], sync on
PrPb should be disabled [Address 15h, Bit 2], sync on RGB is
optional [Address 02h, Bit 4].

GY at Addresses 03h and 05h control the output levels on the
green signal, BU at 04h and 08h control the blue signal output
levels, and RV at 04h and 09h control the red output levels. To
control YPrPb output levels, YUV output should be enabled
[Address 02h, Bit 5]. In this case GY [Address 05h; Address 03,
Bit 01] is used for the Y output, RV [Address 09; Address 04,
Bit 01] is used for the Pr output and BU [Address 08h; Address
04h, Bit 23] is used for the Pb output.

If RGB output is selected the RGB matrix scaler uses the fol-
lowing equations:

G = GY Y + GU Pb + GV Pr

B = GY Y + BU Pb
R = GY Y + RV Pr

If YUV output is selected the following equations are used:

Y = GY Y

U = BU Pb

V = RV Pr

On power-up, the RGB matrix is programmed with default values:

Table IX. RGB Matrix Default Values

Address

Default

03h

04h

F0h

05h

4Eh

06h

0Eh

07h

24h

08h

92h

09h

7Ch

When the programmable RGB matrix is not enabled, the
ADV7314 automatically scales YCrCb inputs to all standards
supported by this part.

SD Luma and Color Control
[Subaddresses 5Ch, 5Dh, 5Eh, 5Fh]

SD Y scale, SD Cr scale, and SD Cb scale are 10-bit control
registers to scale the Y, U, and V output levels.

Each of these registers represents the value required to scale the
U or V level from 0.0 to 2.0 and Y level from 0.0 to 1.5 of its
initial level. The value of these 10 bits is calculated using the
following equation:

Y, U, or V Scalar Value = Scale Factor 512

For example:

Scale Factor = 1.18

Y, U, or V Scale Value = 1.18 512 = 665.6
Y, U, or V Scale Value = 665 (rounded to the nearest integer)
Y, U, or V Scale Value = 1010 0110 01b
Address 5Ch, SD LSB Register = 15h
Address 5Dh, SD Y Scale Register = A6h
Address 5Eh, SD V Scale Register = A6h
Address 5Fh, SD U Scale Register = A6h

REV. 0

ADV7314

SD Hue Adjust Value
[Subaddress 60h]

The hue adjust value is used to adjust the hue on the composite
and chroma outputs.

These eight bits represent the value required to vary the hue of
the video data, i.e., the variance in phase of the subcarrier during
active video with respect to the phase of the subcarrier during
the color burst. The ADV7314 provides a range of

±22.5 incre-

ments of 0.17578125

. For normal operation (zero adjustment),

this register is set to 80h. FFh and 00h represent the upper and
lower limit (respectively) of adjustment attainable.

(Hue Adjust) [

] = 0.17578125 (HCRd 128), for positive

hue adjust value.

0 17578125

128

151

Ê
Ë
Á

^
¯
~ +

*Rounded to the nearest integer.

To adjust the hue by 4

, write 69h to the hue adjust value

Ê
Ë
Á

^
¯
~ +

0 17578125

128

105

*Rounded to the nearest integer.

SD Brightness Control
[Subaddress 61h]

The brightness is controlled by adding a programmable setup
level onto the scaled Y data. This brightness level may be added
onto the scaled Y data. For NTSC with pedestal, the setup can
vary from 0 IRE to 22.5 IRE. For NTSC without pedestal and
PAL, the setup can vary from 7.5 IRE to +15 IRE.

The brightness control register is an 8-bit register. Seven bits of
this 8-bit register are used to control the brightness level. This
brightness level can be a positive or negative value. For example:

Standard: NTSC with pedestal.
To add +20 IRE brightness level, write 28h to Address 61h, SD
brightness.

[

]

[

]

[

]

[

]

SD BrightnessValue H

IRE Value

2 015631

40 31262

Standard: PAL.
To add 7 IRE brightness level, write 72h to Address 61h, SD
brightness.

IRE Value

o twos complement

[

]

[

]

[

]

[

]

[

]

2 015631

14 109417

0001110

1110010

int

Table X. Brightness Control Values

Setup

Level In

Setup

NTSC with

NTSC No

Level In

Pedestal

PAL

Brightness

22.5 IRE

15 IRE

1Eh

15 IRE

7.5 IRE

0Fh

7.5 IRE

0 IRE

00h

0 IRE

7.5 IRE

71h

*Values in the range from 3Fh to 44h might result in an invalid output signal.

SD Brightness Detect
[Subaddress 7Ah]

The ADV7314 allows monitoring of the brightness level of the
incoming video data. Brightness detect is a read-only register.

Double Buffering
[Subaddress 13h, Bit 7; Subaddress 48h, Bit 2]

Double buffered registers are updated once per field on the
falling edge of the

VSYNC signal. Double buffering improves

the overall performance since modifications to register settings
will not be made during active video, but take effect on the start
of the active video.

Double buffering can be activated on the following HD registers:
HD Gamma A and Gamma B curves and HD CGMS registers.
Double buffering can be activated on the following SD regis-
ters: SD Gamma A and Gamma B curves, SD Y scale, SD U
scale, SD V scale, SD brightness, SD closed captioning, and
SD Macrovision Bits 50.

NTSC WITHOUT PEDESTAL

NO SETUP

VALUE ADDED

POSITIVE SETUP

VALUE ADDED

100 IRE

0 IRE

NEGATIVE SETUP

VALUE ADDED

7.5 IRE

+7.5 IRE

Figure 38. Examples for Brightness Control Values

REV. 0

ADV7314

PROGRAMMABLE DAC GAIN CONTROL

DACs A, B, and C are controlled by Register 0A.
DACs D, E, and F are controlled by Register 0B.
The I

C control registers will adjust the output signal gain up or

down from its absolute level.

CASE B

700mV

300mV

NEGATIVE GAIN PROGRAMMED IN
DAC OUTPUT LEVEL REGISTERS,
SUBADDRESS 0Ah, 0Bh

CASE A

GAIN PROGRAMMED IN DAC O/P LEVEL
REGISTERS, SUBADDRESS 0Ah, 0Bh

700mV

300mV

Figure 39. Programmable DAC Gain--Positive
and Negative Gain

In case A, the video output signal is gained. The absolute level
of the sync tip and blanking level both increase with respect to
the reference video output signal. The overall gain of the
signal is increased from the reference signal.

In case B, the video output signal is reduced. The absolute
level of the sync tip and blanking level both decrease with respect
to the reference video output signal. The overall gain of the signal
is reduced from the reference signal.

The range of this feature is specified for

±7.5% of the nominal

output from the DACs. For example, if the output current of
the DAC is 4.33 mA, the DAC tune feature can change this
output current from 4.008 mA (7.5%) to 4.658 mA (+7.5%).

The reset value of the vid_out_ctrl registers is 00h > nominal
DAC output current. Table XI is an example of how the output
current of the DACs varies for a nominal 4.33 mA output current.

Table XI.

DAC

Register

Current

0Ah or 0Bh

(mA)

% Gain

0100 0000 (40h)

4.658

7.5000

0011 1111 (3Fh)

4.653

7.3820

0011 1110 (3Eh)

4.648

7.3640

...

0000 0010 (02h)

4.43

0.0360

0000 0001 (01h)

4.38

0.0180

0000 0000 (00h)

4.33

0.0000

C Reset Value,

Nominal)

1111 1111 (FFh)

4.25

0.0180

1111 1110 (FEh)

4.23

0.0360

...

1100 0010 (C2h)

4.018

7.3640

1100 0001 (C1h)

4.013

7.3820

1100 0000 (C0h)

4.008

7.5000

REV. 0

ADV7314

Gamma Correction

[Subaddress 24h37h for HD, Subaddress 66h79h for SD]

Gamma correction is available for SD and HD video. For each
standard there are 20 8-bit registers. They are used to program
the gamma correction curves A and B. HD gamma curve A is
programmed at Addresses 24h2Dh, HD gamma curve B at
2Eh37h. SD gamma curve A is programmed at addresses
66h6Fh, and SD gamma curve B at Addresses 70h79h.

Generally, gamma correction is applied to compensate for the
nonlinear relationship between signal input and brightness level
output (as perceived on the CRT). It can also be applied wher-
ever nonlinear processing is used.

Gamma correction uses the function

Signal

OUT

(

)

where = gamma power factor.

Gamma correction is performed on the luma data only. The
user has the choice to use two different curves, curve A or curve
B. At any time, only one of these curves can be used.

The response of the curve is programmed at 10 predefined
locations. In changing the values at these locations, the gamma
curve can be modified. Between these points linear interpolation
is used to generate intermediate values. Considering the curve
to have a total length of 256 points, the 10 locations are at 24,
32, 48, 64, 80, 96, 128, 160, 192, and 224. Location 0, 16,
240, and 255 are fixed and cannot be changed.

LOCATION

100

150

200

250

300

100

150

200

250

0.5

SIGNAL INPUT

GAMMA CORRECTED AMPLITUDE

SIGNAL OUTPUT

GAMMA CORRECTION BLOCK OUTPUT TO A RAMP INPUT

Figure 40. Signal Input (Ramp) and
Signal Output for Gamma 0.5

For the length of 16 to 240, the gamma correction curve has to
be calculated as follows:

y = x

where:

y = gamma corrected output.
x = linear input signal.

= gamma power factor.

To program the gamma correction registers, the seven values for
y have to be calculated using the following formula:

(

)

È
Î

(

)

( )

240 16

where:

(n16)

= value for x along x-axis at points.

n = 24, 32, 48, 64, 80, 96, 128, 160, 192, or 224.

= value for y along the y-axis, which has to be written into

the gamma correction register.

For example:
y

= [(8 / 224)

0.5

224] + 16 = 58

= [(16 / 224)

0.5

224] + 16 = 76

= [(32 / 224)

0.5

224] + 16 = 101

= [(48 / 224)

0.5

224] + 16 =120

= [(64 / 224)

0.5

224] + 16 =136

= [(80 / 224)

0.5

224] + 16 = 150

128

= [(112 / 224)

0.5

224] + 16 = 174

160

= [(144 / 224)

0.5

224] + 16 = 195

192

= [(176 / 224)

0.5

224] + 16 = 214

224

= [(208 / 224)

0.5

224] + 16 = 232

*rounded to the nearest integer

The gamma curves in Figure 41 are examples only; any user
defined curve is acceptable in the range of 16 to 240.

LOCATION

100

150

200

250

300

100

150

200

250

GAMMA CORRECTED AMPLITUDE

GAMMA CORRECTION BLOCK TO A RAMP INPUT FOR

VARIOUS GAMMA VALUES

0.3

0.5

1.5

1.8

SIGNAL INPUT

Figure 41. Signal Input (Ramp) and
Selectable Gamma Output Curves

REV. 0

ADV7314

HD Sharpness Filter Control and Adaptive Filter Control
[Subaddress 20h, 38h3Dh]

There are three Filter modes available on the ADV7314:
sharpness filter mode and two adaptive filter modes.

HD Sharpness Filter Mode

To enhance or attenuate the Y signal in the frequency ranges
shown in Figure 42, the following register settings must be used:
HD sharpness filter must be enabled and HD adaptive filter
enable must be disabled.

To select one of the 256 individual responses, the according gain
values for each filter, which range from 8 to +7, must be pro-
grammed into the HD sharpness filter gain register at Address 20h.

HD Adaptive Filter Mode

The HD adaptive filter threshold A, B, C registers, the HD
adaptive filter gain 1, 2, 3 registers, and the HD sharpness filter
gain register are used in adaptive filter mode. To activate the
adaptive filter control, HD sharpness filter must be enabled and
HD adaptive filter gain must be enabled.

FREQUENCY (MHz)

MAGNITUDE

0.5

0.6

0.7

0.8

0.9

1.0

1.1

1.2

1.3

1.4

1.5

FILTER A RESPONSE (Gain Ka)

FREQUENCY (MHz)

MAGNITUDE

0.5

0.6

0.7

0.8

0.9

1.0

1.1

1.2

1.3

1.4

1.5

FILTER B RESPONSE (Gain Kb)

FREQUENCY (MHz)

MAGNITUDE RESPONSE (Linear Scale)

1.0

1.1

1.2

1.3

1.4

1.5

1.6

INPUT SIGNAL:

STEP

FREQUENCY RESPONSE IN SHARPNESS
FILTER MODE WITH Ka = 3 AND Kb = 7

SHARPNESS AND ADAPTIVE FILTER CONTROL BLOCK

Figure 42. Sharpness and Adaptive Filter Control Block Frequency Response in
Sharpness Filter Mode with Ka = +3 and Kb = +7

The derivative of the incoming signal is compared to the three
programmable threshold values: HD adaptive filter threshold
A, B, C. The recommended threshold range is from 16 to 235
although any value in the range of 0 to 255 can be used.

The edges can then be attenuated with the settings in HD adaptive
filter gain 1, 2, 3 registers and HD sharpness filter gain register.
According to the settings of the HD adaptive filter mode con-
trol, there are two adaptive filter modes available:

1. Mode A is used when adaptive filter mode is set to 0. In this

case, Filter B (LPF) will be used in the adaptive filter block.
Also, only the programmed values for Gain B in the HD
sharpness filter gain, HD adaptive filter gain 1, 2, 3 are applied
when needed. The Gain A values are fixed and cannot be
changed.

2. Mode B is used when adaptive filter gain is set to 1. In this

mode, a cascade of Filter A and Filter B is used. Both set-
tings for Gain A and Gain B in the HD sharpness filter gain,
HD adaptive filter gain 1, 2, 3 become active when needed.

REV. 0

ADV7314

CH1

500mV

M 4.00 s

CH1

ALL FIELDS

REF A

500mV 4.00 s

9.99978ms

CH1

500mV

M 4.00 s

CH1

ALL FIELDS

REF A

500mV 4.00 s

9.99978ms

Figure 43. HD Sharpness Filter Control with Different Gain Settings for HS Sharpness Filter Gain Value

HD Sharpness Filter and Adaptive Filter Application Examples
HD Sharpness Filter Application

The HD sharpness filter can be used to enhance or attenuate
the Y video output signal. The following register settings were
used to achieve the results shown in the figures below. Input
data was generated by an external signal source.

Table XII.

Register

Reference in

Address

Setting

Figure 43

00h

FCh

01h

10h

02h

20h

10h

00h

11h

81h

20h

00h

20h

08h

20h

04h

20h

40h

20h

80h

20h

22h

The effect of the sharpness filter can also be seen when using
the internally generated cross hatch pattern.

Table XIII.

Address

Register Setting

00h

FCh

01h

10h

02h

20h

10h

00h

11h

85h

20h

99h

In toggling the sharpness filter enable bit [Address 11h, Bit 7],
it can be seen that the line contours of the cross hatch pattern
change their sharpness.

REV. 0

ADV7314

Adaptive Filter Control Application

Figures 44 and 45 show a typical signal to be processed by the
adaptive filter control block.

: 692mV

@: 446mV

: 332ns

@: 12.8ms

Figure 44. Input Signal to Adaptive Filter Control

: 692mV

@: 446mV

: 332ns

@: 12.8ms

Figure 45. Output Signal after Adaptive Filter Control

The following register settings were used to obtain the results
shown in Figure 45, i.e., to remove the ringing on the Y signal.
Input data was generated by an external signal source.

Table XIV.

Address

Register Setting

00h

FCh

01h

38h

02h

20h

10h

00h

11h

81h

15h

80h

20h

00h

38h

ACh

39h

9Ah

3Ah

88h

3Bh

28h

3Ch

3Fh

3Dh

64h

*All other registers at normal settings.

When changing the adaptive filter mode to Mode B, [Address
15h, Bit 6], the following output can be obtained:

: 674mV

@: 446mV

: 332ns

@: 12.8ms

Figure 46. Output Signal from Adaptive Filter Control

The adaptive filter control can also be demonstrated using the
internally generated cross hatch test pattern and toggling the
adaptive filter control bit [Address 15h, Bit 7].

Table XV.

Address

Register Setting

00h

FCh

01h

38h

02h

20h

10h

00h

11h

85h

15h

80h

20h

00h

38h

ACh

39h

9Ah

3Ah

88h

3Bh

28h

3Ch

3Fh

3Dh

64h

REV. 0

ADV7314

SD DIGITAL NOISE REDUCTION
[Subaddress 63h, 64h, 65h]

DNR is applied to the Y data only. A filter block selects the high
frequency, low amplitude components of the incoming signal
[DNR input select]. The absolute value of the filter output is
compared to a programmable threshold value [DNR threshold
control]. There are two DNR modes available: DNR mode and
DNR sharpness mode.

In DNR mode, if the absolute value of the filter output is smaller
than the threshold, it is assumed to be noise. A programmable
amount [coring gain border, coring gain data] of this noise
signal will be subtracted from the original signal.

In DNR sharpness mode, if the absolute value of the filter out-
put is less than the programmed threshold, it is assumed to be
noise, as before. Otherwise, if the level exceeds the threshold,
now being identified as a valid signal, a fraction of the signal
[coring gain border, coring gain data] will be added to the origi-
nal signal in order to boost high frequency components and to
sharpen the video image.

In MPEG systems, it is common to process the video information
in blocks of 8 pixels

8 pixels for MPEG2 systems, or 16 pixels

16 pixels for MPEG1 systems [block size control]. DNR can

be applied to the resulting block transition areas that are known
to contain noise. Generally, the block transition area contains
two pixels. It is possible to define this area to contain four pixels
[border area].

It is also possible to compensate for variable block positioning
or differences in YCrCb pixel timing with the use of the [DNR
block offset].

BLOCK SIZE CONTROL

BORDER AREA

BLOCK OFFSET

CORING GAIN DATA

CORING GAIN BORDER

GAIN

DNR CONTROL

FILTER

OUTPUT

> THRESHOLD ?

INPUT FILTER

BLOCK

FILTER OUTPUT

< THRESHOLD

DNR OUT

MAIN SIGNAL PATH

ADD SIGNAL
ABOVE THRESHOLD
RANGE FROM
ORIGINAL SIGNAL

DNR
SHARPNESS
MODE

NOISE
SIGNAL PATH

Y DATA

INPUT

BLOCK SIZE CONTROL

BORDER AREA

BLOCK OFFSET

CORING GAIN DATA

CORING GAIN BORDER

GAIN

DNR CONTROL

FILTER

OUTPUT

< THRESHOLD ?

INPUT FILTER

BLOCK

FILTER OUTPUT

> THRESHOLD

DNR OUT

MAIN SIGNAL PATH

SUBTRACT SIGNAL
IN THRESHOLD
RANGE FROM
ORIGINAL SIGNAL

DNR MODE

NOISE
SIGNAL PATH

Y DATA

INPUT

Figure 47. DNR Block Diagram

The digital noise reduction registers are three 8-bit registers.
They are used to control the DNR processing.

Coring Gain Border [Address 63h, Bits 30]

These four bits are assigned to the gain factor applied to
border areas.

In DNR mode, the range of gain values is 01, in increments of
1/8. This factor is applied to the DNR filter output, which lies
below the set threshold range. The result is then subtracted
from the original signal.

In DNR sharpness mode the range of gain values is 00.5, in
increments of 1/16. This factor is applied to the DNR filter
output which lies above the threshold range. The result is added
to the original signal.

Coring Gain Data [Address 63h, Bits 7-4]

These four bits are assigned to the gain factor applied to the
luma data inside the MPEG pixel block.

In DNR mode the range of gain values is 01, in increments of
1/8. This factor is applied to the DNR filter output, which lies
below the set threshold range. The result is then subtracted
from the original signal.

In DNR sharpness mode, the range of gain values is 00.5, in
increments of 1/16. This factor is applied to the DNR filter
output, which lies above the threshold range. The result is added
to the original signal.

O X X X X X X O O X X X X X X O

DNR27 DNR24 = 01H

OFFSET CAUSED
BY VARIATIONS IN
INPUT TIMING

APPLY BORDER
CORING GAIN

APPLY DATA
CORING GAIN

Figure 48. DNR Block Offset Control

DNR Threshold [Address 64h, Bits 50]

These six bits are used to define the threshold value in the range
of 0 to 63. The range is an absolute value.

Border Area [Address 64h, Bit 6]

In setting this bit to a Logic 1, the block transition area can be
defined to consist of four pixels. If this bit is set to a Logic 0,
the border transition area consists of two pixels, where one pixel
refers to two clock cycles at 27 MHz.

720 485 PIXELS

(NTSC)

8 8 PIXEL BLOCK

2 PIXEL

BORDER DATA

Figure 49. DNR Border Area

REV. 0

ADV7314

Block Size Control [Address 64h, Bit 7]

This bit is used to select the size of the data blocks to be processed.
Setting the block size control function to a Logic 1 defines a
16 pixel

¥ 16 pixel data block; a Logic 0 defines an 8 pixel ¥

8 pixel data block, where one pixel refers to two clock cycles at
27 MHz.

DNR Input Select Control [Address 65h, Bit 20]

Three bits are assigned to select the filter that is applied to the
incoming Y data. The signal that lies in the pass band of the
selected filter is the signal that will be DNR processed. Figure 50
shows the filter responses selectable with this control.

FILTER C

FILTER B

FILTER A

FILTER D

FREQUENCY (Hz)

0.2

0.4

0.6

MAGNITUDE

0.8

1.0

Figure 50. DNR Input Select

DNR Mode Control [Address 65h, Bit 4]

This bit controls the DNR mode selected. A Logic 0 selects
DNR mode; a Logic 1 selects DNR sharpness mode.

DNR works on the principle of defining low amplitude, high
frequency signals as probable noise and subtracting this noise
from the original signal.

In DNR mode, it is possible to subtract a fraction of the signal
that lies below the set threshold, assumed to be noise, from the
original signal. The threshold is set in DNR Register 1.

When DNR sharpness mode is enabled, it is possible to add a
fraction of the signal that lies above the set threshold to the
original signal, since this data is assumed to be valid data and
not noise. The overall effect is that the signal will be boosted
(similar to using extended SSAF filter).

Block Offset Control [Address 65h, Bits 74]

Four bits are assigned to this control, which allows a shift of the
data block of 15 pixels maximum. Consider the coring gain
positions fixed. The block offset shifts the data in steps of one
pixel such that the border coring gain factors can be applied at the
same position regardless of variations in input timing of the data.

REV. 0

ADV7314

SD ACTIVE VIDEO EDGE
[Subaddress 42h, Bit 7]

When the active video edge is enabled, the first three pixels and
the last three pixels of the active video on the luma channel are
scaled in such a way that maximum transitions on these pixels
are not possible. The scaling factors are

¥1/8, ¥1/2, ¥7/8. All

other active video passes through unprocessed.

100 IRE

0 IRE

100 IRE

12.5 IRE

87.5 IRE

0 IRE

50 IRE

LUMA CHANNEL WITH
ACTIVE VIDEO EDGE
DISABLED

LUMA CHANNEL WITH
ACTIVE VIDEO EDGE
ENABLED

Figure 51. Example for Active Video Edge Functionality

VOLTS

F2
L135

IRE:FLT

50

100

0.5

Figure 52. Address 42h, Bit 7 = 0

VOLTS

F2
L135

IRE:FLT

50

100

0.5

Figure 53. Address 42h, Bit 7 = 1

SAV/EAV Step Edge Control

The ADV7314 can control fast rising and falling signals at the
start and end of active video to minimize ringing.

An algorithm monitors SAV and EAV and governs when the
edges are too fast. The result will be reduced ringing at the start
and end of active video for fast transitions.

Subaddress 42h, Bit 7 = 1 enables this feature.

REV. 0

ADV7314

BOARD DESIGN AND LAYOUT CONSIDERATIONS

DAC Termination and Layout Considerations

The ADV7314 contains an on-board voltage reference. The
ADV7314 can be used with an external V

REF

(AD1580).

The R

SET

resistors are connected between the R

SET

pins and

AGND and are used to control the full-scale output current and
therefore the DAC voltage output levels. For full-scale output,
R

SET

must have a value of 3040

W. The R

SET

values should not

be changed. R

LOAD

has a value of 150

W with a 4 gain stage

for full-scale output.

Video Output Buffer and Optional Output Filter

Output buffering on all six DACs is necessary in order to drive
output devices, such as SD or HD monitors. Analog Devices
produces a range of suitable op amps for this application, for
example the AD8061. More information on line driver buffering
circuits is given in the relevant op amp data sheets.

An optional analog reconstruction low-pass filter (LPF) may be
required as an anti-imaging filter if the ADV7314 is connected
to a device that requires this filtering. The filter specifications
vary with the application.

Table XVI. External Filter Requirements

Cutoff
Frequency Attenuation

Application Oversampling

(MHz)

50 dB @ (MHz)

>6.5

20.5

>6.5

209.5

>12.5

14.5

>12.5

203.5

HDTV

>30

44.25

HDTV

>30

118.5

600

300

22pF

300

DAC OUTPUT

BNC OUTPUT

2.2 H

1.8k

Figure 54. Example for Output Filter for SD,
16 Oversampling

10

15

20

25

30

35

40

30

60

90

120

150

180

210

240

16n

14n

12n

10n

10M

100M

FREQUENCY (Hz)

CIRCUIT FREQUENCY RESPONSE

GROUP DELAY (sec)

PHASE (Deg)

MAGNITUDE (dB)

GAIN (dB)

Figure 55. Filter Plot for Output Filter for SD,
16 Oversampling

REV. 0

ADV7314

600

22pF

300

22pF

300

DAC OUTPUT

BNC OUTPUT

3.3 H

1.8k

Figure 56. Example for Output Filter for PS,
8

¥ Oversampling

82pF

33pF

DAC OUTPUT

220nH

470nH

500

BNC OUTPUT

500

300

Figure 57. Example for Output Filter for HDTV,
2

¥ Oversampling

Table XVII shows possible output rates from the ADV7314.

Table XVII.

Input Mode

PLL

Output

Address 01h, Bit 64

Address 00h, Bit 1 Rate

SD Only

Off

27 MHz (2

¥)

216 MHz (16

¥)

PS Only

Off

27 MHz (1

¥)

216 MHz (8

¥)

HDTV Only

Off

74.25 MHz (1

¥)

148.5 MHz (2

¥)

12

18

24

30

36

42

48

54

60

198

118

158

77.6

37.6

42.4

82.4

122

162

202

20n

16n

18n

14n

12n

10n

10M

100M

FREQUENCY (Hz)

CIRCUIT FREQUENCY RESPONSE

MAGNITUDE (dB)

PHASE (Deg)

GAIN (dB)

GROUP DELAY (sec)

Figure 58. Filter Plot for Output Filter for PS,
8

¥ Oversampling

10

20

30

40

50

60

480

360

240

120

240

18n

15n

12n

10M

100M

FREQUENCY (Hz)

CIRCUIT FREQUENCY RESPONSE

GROUP DELAY (sec)

PHASE (Deg)

MAGNITUDE (dB)

GAIN (dB)

Figure 59. Example for Output Filter HDTV,
2

¥ Oversampling

REV. 0

ADV7314

PC BOARD LAYOUT CONSIDERATIONS

The ADV7314 is optimally designed for lowest noise perfor-
mance, for both radiated and conducted noise. To complement
the excellent noise performance of the ADV7314, it is impera-
tive that great care be given to the PC board layout.

The layout should be optimized for lowest noise on the ADV7314
power and ground lines. This can be achieved by shielding the
digital inputs and providing good decoupling. The lead length
between groups of V

and AGND, V

and DGND, and

DD_IO

and GND_IO pins should be kept as short as possible to

minimized inductive ringing.

It is recommended that a 4-layer printed circuit board is used
with power and ground planes separating the layer of the signal
carrying traces of the components and solder side layer. Com-
ponent placement should be carefully considered in order to
separate noisy circuits, such as crystal clocks, high speed logic
circuitry, and analog circuitry.

There should be a separate analog ground plane and a separate
digital ground plane.

Power planes should encompass a digital power plane and an
analog power plane. The analog power plane should contain the
DACs and all associated circuitry, V

REF

circuitry. The digital

power plane should contain all logic circuitry.

The analog and digital power planes should be individually con-
nected to the common power plane at one single point through a
suitable filtering device, such as a ferrite bead.

DAC output traces on a PCB should be treated as transmission
lines. It is recommended that the DACs be placed as close as
possible to the output connector, with the analog output traces
being as short as possible (less than 3 inches). The DAC termi-
nation resistors should be placed as close as possible to the
DAC outputs and should overlay the PCB's ground plane. As
well as minimizing reflections, short analog output traces will
reduce noise pickup due to neighboring digital circuitry.

To avoid crosstalk between the DAC outputs, it is recommended
to leave as much space as possible between the tracks of the
individual DAC output pins. The addition of ground tracks
between outputs is also recommended.

Supply Decoupling

Noise on the analog power plane can be further reduced by the
use of decoupling capacitors.

Optimum performance is achieved by the use of 10 nF and
0.1

mF ceramic capacitors. Each of group of V

, V

, or V

DD_IO

pins should be individually decoupled to ground. This should
be done by placing the capacitors as close as possible to the
device with the capacitor leads as short as possible, thus mini-
mizing lead inductance.

A 1

mF tantalum capacitor is recommended across the V

supply

in addition to a 10 nF ceramic capacitor. See Figure 60.

Digital Signal Interconnect

The digital signal lines should be isolated as much as possible
from the analog outputs and other analog circuitry. Digital
signal lines should not overlay the analog power plane.

Due to the high clock rates used, long clock lines to the ADV7314
should be avoided to minimize noise pickup.

Any active pull-up termination resistors for the digital inputs
should be connected to the digital power plane and not to the
analog power plane.

Analog Signal Interconnect

The ADV7314 should be located as close as possible to the
output connectors, thus minimizing noise pickup and reflections
due to impedance mismatch.

For optimum performance, the analog outputs should each be
source and load terminated, as shown in Figure 60. The termi-
nation resistors should be as close as possible to the ADV7314
to minimize reflections.

For optimum performance, it is recommended that all decoupling
and external components relating to the ADV7314 be located on
the same side of the PCB and as close as possible to the ADV7314.

Any unused inputs should be tied to ground.

REV. 0

ADV7314

S_HSYNC

S0S9

S_VSYNC

S BLANK

C0C9

Y0Y9

P_HSYNC

P_VSYNC

P_BLANK

RESET

CLKIN_B

CLKIN_A

EXT_LF

GND_IO AGND DGND

SET1

SET2

ALSB

SCLK

DAC F

DAC E

DAC D

DAC C

DAC B

DAC A

REF

COMP2

COMP1

150

SDA

11, 57

3040

3.9nF

680

820pF

4.7 F

150

UNUSED INPUTS SHOULD BE GROUNDED.

4.7k

0.1 F

1 F

10nF

0.1 F

10nF

10, 56

MPU
BUS

ADV7314

POWER SUPPLY DECOUPLING FOR

EACH POWER SUPPLY GROUP

100nF

1.1k

RECOMMENDED EXTERNAL
AD1580 FOR OPTIMUM
PERFORMANCE

DD_IO

SELECTION HERE
DETERMINES
DEVICE ADDRESS

100

Figure 60. ADV7314 Circuit Layout

REV. 0

ADV7314

APPENDIX 1--COPY GENERATION
MANAGEMENT SYSTEM

PS CGMS Data Registers 20
[Subaddress 21h, 22h, 23h]

PS CGMS is available in 525p mode conforming to CGMS-A
EIA-J CPR1204-1, transfer method of video ID information using
vertical blanking interval (525p system), March 1998, and
IEC61880, 1998, Video systems (525/60)--video and accom-
panied data using the vertical blanking interval--analog
interface.

When PS CGMS is enabled [Subaddress 12h, Bit 6 = 1],
CGMS data is inserted on line 41. The PS CGMS data registers
are at Addresses 21h, 22h, and 23h.

SD CGMS Data Registers 20
[Subaddress 59h, 5Ah, 5Bh]

The ADV7314 supports Copy Generation Management System
(CGMS), conforming to the standard. CGMS data is transmit-
ted on Line 20 of the odd fields and Line 283 of even fields.
Bits C/W05 and C/W06 control whether or not CGMS data is
output on odd and even fields. CGMS data can be transmitted
only when the ADV7314 is configured in NTSC mode. The
CGMS data is 20 bits long, and the function of each of these bits
is as shown in Table XVIII. The CGMS data is preceded by a
reference pulse of the same amplitude and duration as a CGMS
bit; see Figure 62.

HD/PS CGMS [Address 12h, Bit 6]

The ADV7314 supports Copy Generation Management System
(CGMS) in HDTV mode (720p and 1080i) in accordance
with EIAJ CPR-1204-2.

The HD CGMS data registers can be found at Address 021h,
22h, 23h.

Function of CGMS Bits

Word 06 bits; Word 14 bits; Word 26 bits; CRC 6 bits
CRC polynomial = x

+ x + 1 (preset to 111111)

720p System

CGMS data is applied to Line 24 of the luminance vertical
blanking interval.

1080i System

CGMS data is applied to Line 19 and on Line 582 of the lumi-
nance vertical blanking interval.

CGMS Functionality

If SD CGMS CRC [Address 59h, Bit 4] or PS/HD CGMS CRC
[Subaddress 12h, Bit 7] is set to a Logic 1, the last six bits,
C19C14, which comprise the 6-bit CRC check sequence, are
calculated automatically on the ADV7314 based on the lower
14 bits (C0C13) of the data in the data registers and output
with the remaining 14 bits to form the complete 20 bits of the
CGMS data. The calculation of the CRC sequence is based on
the polynomial x

+ x + 1 with a preset value of 111111. If SD

CGMS CRC [Address 59h, Bit 4] or PS/HD CGMS CRC [Ad-
dress 12h, Bit 7] is set to a Logic 0, all 20 bits (C0C19) are
output directly from the CGMS registers (no CRC calculated,
must be calculated by the user).

Table XVIII.

Bit

Function

WORD0

Aspect ratio

16:9

4:3

Display format

Letterbox

Normal

Undefined

WORD0
B4, B5, B6

Identification information about video
and other signals (e.g., audio)

WORD1
B7, B8, B9, B10

Identification signal incidental to Word 0

WORD2
B11, B12, B13, B14

Identification signal and information
incidental to Word 0

REV. 0

ADV7314

C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19

CRC SEQUENCE

21.2 s 0.22 s

22T

REF

5.8 s 0.15 s

0mV

300mV

70% 10%

T = 1/(f

33) = 963ns

= HORIZONTAL SCAN FREQUENCY

T 30ns

+700mV

BIT 1 BIT 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .BIT 20

Figure 61. Progressive Scan CGMS Waveform

C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19

CRC SEQUENCE

49.1 s 0.5 s

REF

11.2 s

0 IRE

40 IRE

+70 IRE

+100 IRE

2.235 s 20ns

Figure 62. Standard Definition CGMS Waveform

CRC SEQUENCE

C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19

REF

3.128 s 90ns

17.2 s 160ns

22T

T = 1/(f

1650/58) = 781.93ns

= HORIZONTAL SCAN FREQUENCY

T 30ns

0mV

300mV

70% 10%

+700mV

BIT 1 BIT 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .BIT 20

Figure 63. HDTV 720P CGMS Waveform

C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19

CRC SEQUENCE

REF

4.15 s 60ns

22.84 s 210ns

22T

T = 1/(f

2200/77) = 1.038 s

= HORIZONTAL SCAN FREQUENCY

T 30ns

0mV

300mV

70% 10%

+700mV

BIT 1 BIT 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .BIT 20

Figure 64. HDTV 1080i CGMS Waveform

REV. 0

ADV7314

Bit

Description

Bit 0Bit 2

Aspect Ratio/Format/Position Bits

Bit 3

IS Odd Parity Check of Bit 0Bit 2

B0, B1, B2, B3

Aspect Ratio Format

Position

0 0 0 1

4:3

Full Format

Not applicable

1 0 0 0

14:9

Letterbox

Center

0 1 0 0

14:9

Letterbox

Top

1 1 0 1

16:9

Letterbox

Center

0 0 1 0

16:9

Letterbox

Top

1 0 1 1

>16:9

Letterbox

Center

0 1 1 1

14:9

Full Format

Center

1 1 1 0

16:9

N/A

B4
0

Camera Mode

Film Mode

B5
0

Standard Coding

Motion Adaptive Color Plus

Table XIX. Function of WSS Bits

Bit

Description

B6
0

No Helper

Modulated Helper

Reserved

B9 B10
0 0

No Open Subtitles

1 0

Subtitles in Active Image Area

0 1

Subtitles out of Active Image Area

1 1

Reserved

B11
0

No Surround Sound Information

Surround Sound Mode

B12

Reserved

B13

Reserved

APPENDIX 2--SD WIDE SCREEN SIGNALING
[Subaddress 59h, 5Ah, 5Bh]

The ADV7314 supports wide screen signaling (WSS) conforming
to the standard. WSS data is transmitted on Line 23. WSS data
can be transmitted only when the ADV7314 is configured in PAL
mode. The WSS data is 14 bits long, and the function of each of
these bits is as shown in Table XIX. The WSS data is preceded

W0 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13

ACTIVE

VIDEO

RUN-IN

SEQUENCE

START

CODE

500mV

11.0 s

38.4 s

42.5 s

Figure 65. WSS Waveform Diagram

by a run-in sequence and a start code (see Figure 65). If SD
WSS [Address 59h, Bit 7] is set to a Logic 1, it enables the WSS
data to be transmitted on Line 23. The latter portion of Line 23
(42.5

ms from the falling edge of HSYNC) is available for the

insertion of video.

It is possible to blank the WSS portion of Line 23 with Subaddress
61h, Bit 7.

REV. 0

ADV7314

APPENDIX 3--SD CLOSED CAPTIONING
[Subaddress 51h54h]

The ADV7314 supports closed captioning conforming to the
standard television synchronizing waveform for color transmis-
sion. Closed captioning is transmitted during the blanked active
line time of Line 21 of the odd fields and Line 284 of even fields.

Closed captioning consists of a 7-cycle sinusoidal burst that is
frequency- and phase-locked to the caption data. After the clock
run-in signal, the blanking level is held for two data bits and is
followed by a Logic Level 1 start bit. 16 bits of data follow the
start bit. These consist of two 8-bit bytes, seven data bits, and
one odd parity bit. The data for these bytes is stored in the SD
closed captioning registers [Address 53h54h].

The ADV7314 also supports the extended closed captioning
operation, which is active during even fields and is encoded on
Scan Line 284. The data for this operation is stored in the SD
closed captioning registers [Address 51h52h].

All clock run-in signals and timing to support closed captioning
on Lines 21 and 284 are generated automatically by the ADV7314.
All pixels inputs are ignored during Lines 21 and 284 if closed
captioning is enabled.

FCC Code of Federal Regulations (CFR) 47 section 15.119
and EIA608 describe the closed captioning information for
Lines 21 and 284.

The ADV7314 uses a single buffering method. This means that
the closed captioning buffer is only one byte deep, therefore
there will be no frame delay in outputting the closed captioning
data unlike other two byte deep buffering systems. The data
must be loaded one line before (Line 20 or Line 283) it is out-
put on Line 21 and Line 284. A typical implementation of this
method is to use

VSYNC to interrupt a microprocessor, which

in turn will load the new data (two bytes) every field. If no new
data is required for transmission, 0s must be inserted in both
data registers, which is called nulling. It is also important to load
control codes, all of that are double bytes on Line 21 or a televi-
sion will not recognize them. If there is a message like Hello
World that has an odd number of characters, it is important
to pad it out to even in order to get end-of-caption 2-byte
control code to land in the same field.

S
T
A
R
T

D0D6

10.5

0.25 s

12.91 s

7 CYCLES OF

0.5035MHz

CLOCK RUN-IN

REFERENCE COLOR BURST

(9 CYCLES)

FREQUENCY = F

= 3.579545MHz

AMPLITUDE = 40 IRE

50 IRE

40 IRE

10.003 s

27.382 s

33.764 s

BYTE 1

BYTE 0

TWO 7-BIT + PARITY

ASCII CHARACTERS

(DATA)

Figure 66. Closed Captioning Waveform, NTSC

REV. 0

ADV7314

APPENDIX 4--TEST PATTERNS

The ADV7314 can generate SD and HD test patterns.

CH2 200mV

M 10.0 s

A CH2 1.20V

30.6000 s

Figure 67. NTSC Color Bars

CH2 200mV

M 10.0 s

A CH2 1.21V

30.6000 s

Figure 68. PAL Color Bars

CH2 100mV

M 10.0 s

CH2 EVEN

1.82600ms

Figure 69. NTSC Black Bar (21 mV, 0 mV, 3.5 mV,
7 mV, 10.5 mV, 14 mV, 18 mV, 23 mV)

CH2 100mV

M 10.0 s

CH2 EVEN

1.82600ms

Figure 70. PAL Black Bar (21 mV, 0 mV, 3.5 mV,
7 mV, 10.5 mV, 14 mV, 18 mV, 23 mV)

CH2 200mV

M 4.0 s

CH2 EVEN

1.82944ms

Figure 71. 525p Hatch Pattern

CH2 200mV

M 4.0 s

CH2 EVEN

1.84208ms

Figure 72. 625p Hatch Pattern

REV. 0

ADV7314

CH2 200mV

M 4.0 s

CH2 EVEN

1.82872ms

Figure 73. 525p Field Pattern

CH2 200mV

M 4.0 s

CH2 EVEN

1.84176ms

Figure 74. 525p Black Bar (35 mV, 0 mV, 7 mV,
14 mV, 21 mV, 28 mV, 35 mV)

CH2 100mV

M 4.0 s

CH2 EVEN

1.82936ms

Figure 75. 625p Field Pattern

CH2 100mV

M 4.0 s

CH2 EVEN

1.84176ms

Figure 76. 625p Black Bar (35 mV, 0 mV, 7 mV,
14 mV, 21 mV, 28 mV, 35 mV)

The following register settings are used to generate an SD NTSC
CVBS output on DAC A.

Register

Subaddress

Setting

00h

80h

40h

10h

42h

40h

44h

40h

4Ah

08h

*All other registers are set to default/normal settings.

For PAL CVBS output on DAC A, the same settings are used
except that Subaddress 40h is changed to 11h.

The following register settings are used to generate an SD NTSC
black bar pattern output on DAC A.

Register

Subaddress

Setting

00h

80h

02h

04h

40h

10h

42h

40h

44h

40h

4Ah

08h

*All other registers are set to default/normal settings.

For PAL black bar pattern output on DAC A, the same settings
are used except that subaddress = 40h and register setting = 11h.

The following register settings are used to generate a 525p hatch
pattern on DAC D.

Register

Subaddress

Setting

00h

80h

01h

10h

40h

11h

05h

16h

A0h

17h

80h

18h

80h

*All other registers are set to default/normal settings.

For 625p hatch pattern on DAC D, the same register settings
are used except that subaddress = 10h and register setting = 50h.

For a 525p black bar pattern output on DAC D, the same settings
are used as for a 525p hatch pattern except that subaddress = 02h
and register setting = 24h.

For 625p black bar pattern output on DAC D, the same settings
are used as for a 625p hatch pattern except that subaddress = 02h
and register setting = 24h; and subaddress = 10h and register
setting = 50h.

REV. 0

ADV7314

APPENDIX 5--SD TIMING MODES
[Subaddress 4Ah]

Mode 0 (CCIR-656)--Slave Option
(Timing Register 0 TR0 = X X X X X 0 0 0)

The ADV7314 is controlled by the SAV (start active video) and
EAV (end active video) time codes in the pixel data. All timing
information is transmitted using a 4-byte synchronization pat-
tern. A synchronization pattern is sent immediately before and
after each line during active picture and retrace.

S_VSYNC,

S_HSYNC, and S_BLANK (if not used) pins should be tied
high during this mode. Blank output is available.

F
F

0
0

X
Y

8
0

1
0

8
0

1
0

F
F

0
0

F
F

A
B

8
0

1
0

8
0

1
0

F
F

0
0

X
Y

C
b

Y C

C
b

EAV CODE

SAV CODE

ANCILLARY DATA

(HANC)

4 CLOCK

268 CLOCK

1440 CLOCK

4 CLOCK

280 CLOCK

1440 CLOCK

END OF ACTIVE

VIDEO LINE

START OF ACTIVE

VIDEO LINE

ANALOG

VIDEO

INPUT PIXELS

NTSC /PAL M SYSTEM

PAL SYSTEM

(525 LINES/60Hz)

(625 LINES/50Hz)

Figure 77. SD Slave Mode 0

REV. 0

ADV7314

Mode 0 (CCIR-656)--Master Option
(Timing Register 0 TR0 = X X X X X 0 0 1)

The ADV7314 generates H, V, and F signals required for the
SAV (start active video) and EAV (end active video) time
codes in the CCIR656 standard. The H bit is output on
S_HSYNC, the V bit is output on S_BLANK, and the F bit is
output on

S_VSYNC pin.

522

523

524

525

DISPLAY

VERTICAL BLANK

ODD FIELD

EVEN FIELD

260

261

262

263

264

265

266

267

268

269

270

271

272

273

274

283

284

285

ODD FIELD

EVEN FIELD

DISPLAY

VERTICAL BLANK

Figure 78. SD Master Mode 0 (NTSC)

622

623

624

625

DISPLAY

VERTICAL BLANK

ODD FIELD

EVEN FIELD

309

310

311

312

314

315

316

317

318

319

320

334

335

336

DISPLAY

VERTICAL BLANK

ODD FIELD

EVEN FIELD

313

Figure 79. SD Master Mode 0 (PAL)

REV. 0

ADV7314

Mode 1--Slave Option
(Timing Register 0 TR0 = X X X X X 0 1 0)

In this mode, the ADV7314 accepts horizontal SYNC and
odd/even field signals. A transition of the field input when

HSYNC

is low indicates a new frame, i.e., vertical retrace. The

BLANK

signal is optional. When the

BLANK input is disabled, the

ADV7314 automatically blanks all normally blank lines as per
CCIR-624.

HSYNC is input on HSYNC, BLANK on S_BLANK,

and FIELD on

S_VSYNC.

ANALOG

VIDEO

Figure 80. SD Master Mode 0, Data Transitions

260

261

262

263

264

265

266

267

268

269

270

271

272

273

274

283

284

285

ODD FIELD

EVEN FIELD

DISPLAY

VERTICAL BLANK

522

523

524

525

DISPLAY

VERTICAL BLANK

ODD FIELD

EVEN FIELD

FIELD

HSYNC

BLANK

FIELD

HSYNC

BLANK

Figure 81. SD Slave Mode 1 (NTSC)

REV. 0

ADV7314

Mode 1--Master Option
(Timing Register 0 TR0 = X X X X X 0 1 1)

In this mode, the ADV7314 can generate horizontal sync and odd/
even field signals. A transition of the field input when

HSYNC is

low indicates a new frame i.e., vertical retrace. The

BLANK

signal is optional. When the

BLANK input is disabled, the

ADV7314 automatically blanks all normally blank lines as per
CCIR-624. Pixel data is latched on the rising clock edge following
the timing signal transitions.

HSYNC is output on the S_HSYNC,

BLANK on S_BLANK, and FIELD on S_VSYNC.

622

623

624

625

DISPLAY

VERTICAL BLANK

ODD FIELD

EVEN FIELD

FIELD

DISPLAY

309

310

311

312

313

314

315

316

317

318

319

334

335

336

DISPLAY

VERTICAL BLANK

ODD FIELD

EVEN FIELD

DISPLAY

320

HSYNC

BLANK

FIELD

HSYNC

BLANK

Figure 82. SD Slave Mode 1 (PAL)

FIELD

PIXEL

DATA

PAL = 12 CLOCK/2

NTSC = 16 CLOCK/2

PAL = 132 CLOCK/2

NTSC = 122 CLOCK/2

HSYNC

BLANK

Figure 83. SD Timing Mode 1--Odd/Even Field Transitions Master/Slave

REV. 0

ADV7314

Mode 2--Slave Option
(Timing Register 0 TR0 = X X X X X 1 0 0)

In this mode, the ADV7314 accepts horizontal and vertical sync
signals. A coincident low transition of both

HSYNC and VSYNC

inputs indicates the start of an odd field. A

VSYNC low transi-

tion when

HSYNC is high indicates the start of an even field.

The

BLANK signal is optional. When the BLANK input is

disabled the ADV7314 automatically blanks all normally blank
lines as per CCIR-624.

HSYNC is input S_HSYNC, BLANK

S_BLANK, and VSYNC on S_VSYNC.

522

523

524

525

DISPLAY

VERTICAL BLANK

ODD FIELD

EVEN FIELD

260

261

262

263

264

265

266

267

268

269

270

271

272

273

274

283

284

285

ODD FIELD

EVEN FIELD

DISPLAY

VERTICAL BLANK

HSYNC

BLANK

VSYNC

HSYNC

BLANK

VSYNC

Figure 84. SD Slave Mode 2 (NTSC)

622

623

624

625

DISPLAY

VERTICAL BLANK

ODD FIELD

EVEN FIELD

HSYNC

BLANK

VSYNC

DISPLAY

309

310

311

312

313

314

315

316

317

318

319

334

335

336

DISPLAY

VERTICAL BLANK

ODD FIELD

EVEN FIELD

DISPLAY

320

HSYNC

BLANK

VSYNC

Figure 85. SD Slave Mode 2 (PAL)

REV. 0

ADV7314

PAL = 12 CLOCK/2

NTSC = 16 CLOCK/2

PAL = 132 CLOCK/2

NTSC = 122 CLOCK/2

HSYNC

VSYNC

BLANK

PIXEL

DATA

Figure 86. SD Timing Mode 2 Even-to-Odd Field Transition Master/Slave

PAL = 864 CLOCK/2

NTSC = 858 CLOCK/2

PAL = 132 CLOCK/2

NTSC = 122 CLOCK/2

HSYNC

VSYNC

BLANK

PIXEL

DATA

PAL = 12 CLOCK/2

NTSC = 16 CLOCK/2

Figure 87. SD Timing Mode 2 Odd-to-Even Field Transition Master/Slave

Mode 2--Master Option
(Timing Register 0 TR0 = X X X X X 1 0 1)

In this mode, the ADV7314 can generate horizontal and vertical
sync signals. A coincident low transition of both

HSYNC and

VSYNC inputs indicates the start of an odd field. A VSYNC low
transition when

HSYNC is high indicates the start of an even

field. The

BLANK signal is optional. When the BLANK input is

disabled, the ADV7314 automatically blanks all normally blank
lines as per CCIR-624.

HSYNC is output on S_HSYNC, BLANK

S_BLANK, and VSYNC on S_VSYNC.

REV. 0

ADV7314

Mode 3--Master/Slave Option
(Timing Register 0 TR0 = X X X X X 1 1 0 or X X X X X 1 1 1)

In this mode, the ADV7314 accepts or generates horizontal
sync and odd/even field signals. A transition of the field input
when

HSYNC is high indicates a new frame i.e., vertical re-

trace. The

BLANK signal is optional. When the BLANK input

is disabled, the ADV7314 automatically blanks all normally
blank lines as per CCIR-624.

HSYNC is output in master mode

and input in slave mode on

S_HSYNC, BLANK on S_BLANK,

and

VSYNC on S_VSYNC.

260

261

262

263

264

265

266

267

268

269

270

271

272

273

274

283

284

285

ODD FIELD

EVEN FIELD

DISPLAY

VERTICAL BLANK

522

523

524

525

DISPLAY

VERTICAL BLANK

ODD FIELD

EVEN FIELD

HSYNC

BLANK

FIELD

HSYNC

BLANK

FIELD

Figure 88. SD Timing Mode 3 (NTSC)

622

623

624

625

DISPLAY

VERTICAL BLANK

ODD FIELD

EVEN FIELD

HSYNC

BLANK

FIELD

DISPLAY

309

310

311

312

313

314

315

316

317

318

319

334

335

336

DISPLAY

VERTICAL BLANK

ODD FIELD

EVEN FIELD

HSYNC

BLANK

FIELD

DISPLAY

320

Figure 89. SD Timing Mode 3 (PAL)

REV. 0

ADV7314

APPENDIX 6--HD TIMING

1124

1125

560

561

562

563

564

565

566

567

568

569

570

583

584

585

1123

FIELD 1

FIELD 2

VERTICAL BLANKING INTERVAL

P_VSYNC

P_HSYNC

P_VSYNC

P_HSYNC

DISPLAY

Figure 90. 1080i

HSYNC and VSYNC Input Timing

REV. 0

ADV7314

APPENDIX 7--VIDEO OUTPUT LEVELS
HD YPrPb Output Levels

INPUT CODE

940

EIA-770.2, STANDARD FOR Y

OUTPUT VOLTAGE

300mV

700mV

960

EIA-770.2, STANDARD FOR Pr/Pb

OUTPUT VOLTAGE

512

Figure 91. EIA 770.2 Standard Output Signals
(525p/625p)

782mV

714mV

286mV

700mV

INPUT CODE

940

EIA-770.1, STANDARD FOR Y

OUTPUT VOLTAGE

960

EIA-770.1, STANDARD FOR Pr/Pb

OUTPUT VOLTAGE

512

Figure 92. EIA 770.1 Standard Output Signals
(525p/625p)

300mV

INPUT CODE

940

EIA-770.3, STANDARD FOR Y

OUTPUT VOLTAGE

700mV

600mV

960

EIA-770.3, STANDARD FOR Pr/Pb

OUTPUT VOLTAGE

512

Figure 93. EIA 770.3 Standard Output Signals
(1080i, 720p)

300mV

700mV

INPUT CODE

1023

YOUTPUT LEVELS FOR

FULL INPUT SELECTION

OUTPUT VOLTAGE

1023

Pr/PbOUTPUT LEVELS FOR

FULL INPUT SELECTION

OUTPUT VOLTAGE

INPUT CODE

Figure 94. Output Levels for Full Input Selection

REV. 0

ADV7314

300mV

700mV

550mV

700mV

550mV

Figure 95. HD RGB Output Levels

300mV

0mV

300mV

0mV

300mV

0mV

700mV

550mV

700mV

550mV

700mV

550mV

Figure 96. HD RGB Output Levels--RGB Sync Enabled

300mV

700mV

550mV

700mV

550mV

Figure 97. SD RGB Output Levels--RGB Sync Disabled

300mV

0mV

300mV

0mV

300mV

0mV

700mV

550mV

700mV

550mV

700mV

550mV

Figure 98. SD RGB Output Levels--RGB Sync Enabled

RGB Output Levels

REV. 0

ADV7314

YPrPb Output Levels

160mV

220mV

WHITE

YELLOW

CYAN

GREEN

MAGENTA

RED

BLUE

BLACK

60mV

110mV

280mV

332mV

Figure 99. U Levels--NTSC

160mV

220mV

WHITE

YELLOW

CYAN

GREEN

MAGENTA

RED

BLUE

BLACK

60mV

110mV

280mV

332mV

Figure 100. U Levels--PAL

1000mV

WHITE

YELLOW

CYAN

GREEN

MAGENTA

RED

BLUE

BLACK

1260mV

140mV

200mV

2150mV

900mV

Figure 101. U Levels--NTSC

1000mV

WHITE

YELLOW

CYAN

GREEN

MAGENTA

RED

BLUE

BLACK

1260mV

140mV

200mV

2150mV

900mV

Figure 102. U Levels--PAL

WHITE

YELLOW

CYAN

GREEN

MAGENTA

RED

BLUE

BLACK

300mV

Figure 103. Y Levels--NTSC

WHITE

YELLOW

CYAN

GREEN

MAGENTA

RED

BLUE

BLACK

300mV

Figure 104. Y Levels--PAL

REV. 0

ADV7314

0.5

VOLTS

APL = 44.5%
525 LINE NTSC
SLOW CLAMP TO 0.00V AT 6.72 s

MICROSECONDS

PRECISION MODE OFF

SYNCHRONOUS

SYNC = A

FRAMES SELECTED

1 2

F1
L76

IRE:FLT

100

50

Figure 105. NTSC Color Bars 75%

VOLTS

NOISE REDUCTION: 15.05dB
APL NEEDS SYNC-SOURCE!
525 LINE NTSC NO FILTERING
SLOW CLAMP TO 0.00 AT 6.72 s

MICROSECONDS

PRECISION MODE OFF

SYNCHRONOUS

SYNC = B

FRAMES SELECTED

1 2

F1
L76

IRE:FLT

50

0.4

0.2

0.4

Figure 106. NTSC Chroma

REV. 0

ADV7314

VOLTS

NOISE REDUCTION: 15.05dB
APL = 44.3%
525 LINE NTSC NO FILTERING
SLOW CLAMP TO 0.00 AT 6.72 s

MICROSECONDS

PRECISION MODE OFF

SYNCHRONOUS

SYNC = SOURCE

FRAMES SELECTED

1 2

F2
L238

IRE:FLT

0.4

0.2

0.6

0.2

Figure 107. NTSC Luma

VOLTS

NOISE REDUCTION: 0.00dB
APL = 39.1%
625 LINE NTSC NO FILTERING
SLOW CLAMP TO 0.00 AT 6.72 s

MICROSECONDS

PRECISION MODE OFF

SYNCHRONOUS

SOUND-IN-SYNC OFF

FRAMES SELECTED

1 2 3 4

L608

0.4

0.2

0.6

0.2

Figure 108. PAL Color Bars 75%

REV. 0

ADV7314

VOLTS

APL NEEDS SYNC SOURCE!
625 LINE PAL NO FILTERING
SLOW CLAMP TO 0.00 AT 6.72 s

MICROSECONDS

NO BUNCH SIGNAL

PRECISION MODE OFF

SYNCHRONOUS

SOUND-IN-SYNC OFF

FRAMES SELECTED

L575

0.5

Figure 109. PAL Chroma

VOLTS

APL NEEDS SYNC SOURCE!
625 LINE PAL NO FILTERING
SLOW CLAMP TO 0.00 AT 6.72 s

MICROSECONDS

NO BUNCH SIGNAL

PRECISION MODE OFF

SYNCHRONOUS

SOUND-IN-SYNC OFF

FRAMES SELECTED

L575

0.5

Figure 110. PAL Luma

REV. 0

ADV7314

F
V

F
F

272T

1920T

EAV CODE

SAV CODE

DIGITAL

ACTIVE LINE

4 CLOCK

2112

2116 2156

2199

188

192

2111

0
0

F
F

F
V

FVH* = FVH AND PARITY BITS
SAV/EAV: LINE 1562: F = 0
SAV/EAV: LINE 5631125: F = 1
SAV/EAV: LINE 120; 561583; 11241125: V = 1
SAV/EAV: LINE 21560; 5841123: V = 0

FOR A FIELD RATE OF 30Hz: 40 SAMPLES
FOR A FIELD RATE OF 25Hz: 480 SAMPLES

INPUT PIXELS

ANALOG WAVEFORM

SAMPLE NUMBER

SMPTE 274M

DIGITAL HORIZONTAL BLANKING

ANCILLARY DATA

(OPTIONAL) OR BLANKING CODE

DATUM

Figure 111. EAV/SAV Input Data Timing Diagram--SMPTE 274M

EAV CODE

ANCILLARY DATA

(OPTIONAL)

SAV CODE

DIGITAL

ACTIVE LINE

719

723

736

799

853

FVH* = FVH AND PARITY BITS
SAV: LINE 43525 = 200H
SAV: LINE 142 = 2AC
EAV: LINE 43525 = 274H
EAV: LINE 142 = 2D8

4 CLOCK

857

719

DATUM

DIGITAL HORIZONTAL BLANKING

0
0

F
V

SMPTE 293M

INPUT PIXELS

ANALOG WAVEFORM

SAMPLE NUMBER

F
F

F
V

Figure 112. EAV/SAV Input Data Timing Diagram--SMPTE 293M

APPENDIX 8--VIDEO STANDARDS

REV. 0

ADV7314

VERTICAL BLANK

522

523

524

525

ACTIVE

VIDEO

ACTIVE

VIDEO

Figure 113. SMPTE 293M (525p)

VERTICAL BLANK

ACTIVE

VIDEO

ACTIVE

VIDEO

622

623

624

625

Figure 114. ITU-R BT.1358 (625p)

747

748

749

750

744

745

DISPLAY

VERTICAL BLANKING INTERVAL

Figure 115. SMPTE 296M (720p)

DISPLAY

1124

1125

560

FIELD 1

DISPLAY

561

562

563

564

567

568

569

570

584

566

565

583

585

1123

FIELD 2

VERTICAL BLANKING INTERVAL

Figure 116. SMPTE 274M (1080i)

REV. 0

ADV7314

OUTLINE DIMENSIONS

64-Lead Low Profile Quad Flat Package [LQFP]

(ST-64)

Dimensions shown in millimeters

TOP VIEW

(PINS DOWN)

0.27
0.22
0.17

0.50

BSC

10.00

BSC SQ

1.60
MAX

SEATING

PLANE

0.75

0.60

0.45

VIEW A

12.00 BSC

0.20
0.09

1.45
1.40
1.35

0.10 MAX
COPLANARITY

VIEW A

ROTATED 90 CCW

SEATING
PLANE

6
2

3.5

0.15
0.05

PIN 1

COMPLIANT TO JEDEC STANDARDS MS-026BCD

C0374908/03(0)

Document Outline

FEATURES
GENERAL FEATURES
APPLICATIONS
SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION
DETAILED FEATURES
DETAILED FUNCTIONAL BLOCK DIAGRAM
TABLE OF CONTENTS
SPECIFICATIONS
DYNAMIC SPECIFICATIONS
TIMING SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
THERMAL CHARACTERISTICS
ORDERING GUIDE
PIN CONFIGURATION
PIN FUNCTION DESCRIPTIONS
TERMINOLOGY
MPU PORT DESCRIPTION
REGISTER ACCESS
- Register Programming
- Subaddress Register (SR7…SR0)
INPUT CONFIGURATION
- Standard Definition Only
- Progressive Scan Only or HDTV Only
- Simultaneous Standard Definition and
- Progressive Scan at 27 MHz (Dual Edge) or 54 MHz
OUTPUT CONFIGURATION
TIMING MODES
- HD Async Timing Mode
- HD Timing Reset
- SD Real-Time Control, Subcarrier Reset, and Timing Reset
- Reset Sequence
- SD VCR FF/RW Sync
- Vertical Blanking Interval
- SD Subcarrier Frequency Registers
FILTER SECTION
- HD Sinc Filter
- SD Internal Filter Response
- Typical Performance Characteristics
COLOR CONTROLS AND RGB MATRIX
- HD/PS Y Level, Cr Level, Cb Level
- HD RGB Matrix
- Programming the RGB Matrix
- SD Luma and Color Control
- SD Hue Adjust Value
- SD Brightness Control
- SD Brightness Detect
- Double Buffering
PROGRAMMABLE DAC GAIN CONTROL
- Gamma Correction
- HD Sharpness Filter Control and Adaptive Filter Control
- HD Sharpness Filter and Adaptive Filter Application Examples
SD DIGITAL NOISE REDUCTION
- Coring Gain Border [Address 63h, Bits 3…0]
- Coring Gain Data [Address 63h, Bits 7-4]
- DNR Threshold [Address 64h, Bits 5…0]
- Border Area [Address 64h, Bit 6]
- Block Size Control [Address 64h, Bit 7]
- DNR Input Select Control [Address 65h, Bit 2…0]
- DNR Mode Control [Address 65h, Bit 4]
- Block Offset Control [Address 65h, Bits 7…4]
SD ACTIVE VIDEO EDGE
- SAV/EAV Step Edge Control
BOARD DESIGN AND LAYOUT CONSIDERATIONS
- DAC Termination and Layout Considerations
- Video Output Buffer and Optional Output Filter
PC BOARD LAYOUT CONSIDERATIONS
- Supply Decoupling
- Digital Signal Interconnect
- Analog Signal Interconnect
APPENDIX 1„COPY GENERATION MANAGEMENT SYSTEM
- PS CGMS Data Registers 2…0
- SD CGMS Data Registers 2…0
- HD/PS CGMS [Address 12h, Bit 6]
- Function of CGMS Bits
- CGMS Functionality
APPENDIX 2„SD WIDE SCREEN SIGNALING
APPENDIX 3„SD CLOSED CAPTIONING
APPENDIX 4„TEST PATTERNS
APPENDIX 5„SD TIMING MODES
- Mode 0 (CCIR-656)„Slave Option
- Mode 0 (CCIR-656)„Master Option
- Mode 1„Slave Option
- Mode 1„Master Option
- Mode 2„Slave Option
- Mode 2„Master Option
- Mode 3„Master/Slave Option
APPENDIX 6„HD TIMING
APPENDIX 7„VIDEO OUTPUT LEVELS
- HD YPrPb Output Levels
- RGB Output Levels
- YPrPb Output Levels
APPENDIX 8„VIDEO STANDARDS
OUTLINE DIMENSIONS

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: ADV7314KST

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: ADV7314KST