/home/web/htmldatasheet/RUSSIAN/html/ad/146071

Multiformat 216 MHz

Video Encoder with Six NSV

12-Bit DACs

ADV7320/ADV7321

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700

www.analog.com

Fax: 781.326.8703

FEATURES

High definition input formats

16-/20-, 24-/30-bit (4:2:2, 4:4:4) parallel YCrCb

Fully compliant with:

SMPTE 274M (1080i, 1080p @ 74.25 MHz)
SMPTE 296M (720p)
SMPTE 240M (1035i)
RGB in 3- × 10-bit 4:4:4 input format

HDTV RGB supported:

RGB, RGBHV
Other high definition formats using async

timing mode

Enhanced definition input formats

8-/10-, 16-/20-, 24-/30-bit (4:2:2, 4:4:4) parallel YCrCb
SMPTE 293M (525p)
BTA T-1004 EDTV2 (525p)
ITU-R BT.1358 (625p/525p)
ITU-R BT.1362 (625p/525p)
RGB in 3- × 10-bit 4:4:4 input format

Standard definition input formats

CCIR-656 4:2:2 8-/10-bit or 16-/20-bit parallel input

High definition output formats

YPrPb HDTV (EIA 770.3)
RGB, RGBHV
CGMS-A (720p/1080i)

Enhanced definition output formats

Macrovision Rev 1.2 (525p/625p) (ADV7320 only)
CGMS-A (525p/625p)
YPrPb progressive scan (EIA-770.1, EIA-770.2)
RGB, RGBHV

Standard definition output formats

Composite NTSC M/N
Composite PAL M/N/B/D/G/H/I, PAL-60
SMPTE 170M NTSC-compatible composite video
ITU-R BT.470 PAL-compatible composite video
S-video (Y/C)
EuroScart RGB
Component YPrPb (Betacam, MII, SMPTE/EBU N10)
Macrovision Rev 7.1.L1 (ADV7320 only)

CGMS/WSS
Closed captioning

GENERAL FEATURES

Simultaneous SD/HD, PS/SD inputs and outputs
Oversampling up to 216 MHz

Programmable DAC gain control
Sync outputs in all modes
On-board voltage reference
Six 12-bit NSV (noise shaped video) precision video DACs
2-wire serial I

C® interface, open-drain configuration

Dual I/O supply 2.5 V/3.3 V operation
Analog and digital supply 2.5 V
On-board PLL
64-lead LQFP package
Lead (Pb) free product

APPLICATIONS

EVD players (enhanced versatile disk)
High end /SD/PS DVD recorders/players
SD/progressive scan/HDTV display devices
SD/HDTV set top boxes
Professional video systems

CLKIN_A

CLKIN_B

HSYNC

VSYNC

BLANK

Y9Y0

C9C0

S9S0

TIMING

GENERATOR

PLL

INTERFACE

STANDARD DEFINITION

CONTROL BLOCK

COLOR CONTROL

BRIGHTNESS

DNR

GAMMA

PROGRAMMABLE

FILTERS

SD TEST PATTERN

HIGH DEFINITION

CONTROL BLOCK

HD TEST PATTERN

COLOR CONTROL

ADAPTIVE FILTER CTRL

SHARPNESS FILTER

PROGRAMMABLE

RGB MATRIX

12-BIT

DAC

12-BIT

DAC

12-BIT

DAC

12-BIT

DAC

12-BIT

DAC

12-BIT

DAC

ADV7320/

ADV7321

05067-001

Figure 1. Simplified Functional Block Diagram

GENERAL DESCRIPTION

The ADV®7320/ADV7321 are high speed, digital-to-analog
encoders on single monolithic chips. They include six high
speed NSV video D/A converters with TTL compatible inputs.
They have separate 8-/10-, 16-/20-, and 24-/30-bit input ports
that accept data in high definition and/or standard definition
video format. For all standards, external horizontal, vertical,
and blanking signals or EAV/SAV timing codes control the
insertion of appropriate synchronization signals into the digital
data stream and, therefore, the output signal.

ADV7320/ADV7321

Rev. 0 | Page 2 of 88

TABLE OF CONTENTS

Specifications..................................................................................... 6

Dynamic Specifications ................................................................... 7

Timing Specifications....................................................................... 8

Timing Diagrams.............................................................................. 9

Absolute Maximum Ratings.......................................................... 16

Thermal Characteristics ............................................................ 16

ESD Caution................................................................................ 16

Pin Configuration and Function Descriptions........................... 17

Typical Performance Characteristics ........................................... 19

MPU Port Description................................................................... 23

Subaddress Register (SR7 to SR0) ............................................ 25

Input Configuration ....................................................................... 38

Standard Definition Only.......................................................... 38

Progressive Scan Only or HDTV Only ................................... 38

Simultaneous Standard Definition and
Progressive Scan or HDTV ....................................................... 38

Progressive Scan at 27 MHz (Dual Edge) or 54 MHz ........... 39

Features ............................................................................................ 41

Output Configuration................................................................ 41

HD Async Timing Mode ........................................................... 42

HD Timing Reset........................................................................ 43

SD Real-Time Control, Subcarrier Reset, and
Timing Reset ............................................................................... 43

Reset Sequence............................................................................ 45

SD VCR FF/RW Sync................................................................. 45

Vertical Blanking Interval ......................................................... 46

Subcarrier Frequency Registers ................................................ 46

Square Pixel Timing Mode........................................................ 47

Filters............................................................................................ 48

Color Controls and RGB Matrix .............................................. 49

Programmable DAC Gain Control .......................................... 53

Gamma Correction .................................................................... 53

HD Sharpness Filter and Adaptive Filter Controls................ 55

HD Sharpness Filter and Adaptive Filter
Application Examples ................................................................ 56

SD Digital Noise Reduction...................................................... 57

Coring Gain Border ................................................................... 58

Coring Gain Data ....................................................................... 58

DNR Threshold .......................................................................... 58

Border Area................................................................................. 58

Block Size Control...................................................................... 58

DNR Input Select Control......................................................... 58

DNR Mode Control ................................................................... 59

Block Offset Control .................................................................. 59

SD Active Video Edge................................................................ 59

SAV/EAV Step Edge Control .................................................... 59

HSYNC/VSYNC Output Control ............................................ 61

Board Design and Layout.............................................................. 62

DAC Termination and Layout Considerations ...................... 62

Video Output Buffer and Optional Output Filter.................. 62

PCB Board Layout...................................................................... 63

Appendix 1--Copy Generation Management System .............. 65

PS CGMS..................................................................................... 65

HD CGMS................................................................................... 65

SD CGMS .................................................................................... 65

Function of CGMS Bits ............................................................. 65

CGMS Functionality.................................................................. 65

Appendix 2--SD Wide Screen Signaling .................................... 68

Appendix 3--SD Closed Captioning ........................................... 69

Appendix 4--Test Patterns............................................................ 70

Appendix 5--SD Timing Modes .................................................. 73

ADV7320/ADV7321

Rev. 0 | Page 3 of 88

Mode 0 (CCIR-656)--Slave Option
(Timing Register 0 TR0 = X X X X X 0 0 0) ............................73

Mode 0 (CCIR-656)--Master Option
(Timing Register 0 TR0 = X X X X X 0 0 1) ............................74

Mode 1--Slave Option
(Timing Register 0 TR0 = X X X X X 0 1 0) ............................76

Mode 1--Master Option
(Timing Register 0 TR0 = X X X X X 0 1 1) ............................77

Mode 2-- Slave Option
(Timing Register 0 TR0 = X X X X X 1 0 0) ............................78

Mode 2--Master Option
(Timing Register 0 TR0 = X X X X X 1 0 1) ............................79

Mode 3--Master/Slave Option
(Timing Register 0 TR0 = X X X X X 1 1 0 or X X X X X 1 1 1)

.......................................................................................................80

Appendix 6--HD Timing ..............................................................81

Appendix 7--Video Output Levels...............................................82

HD YPrPb Output Levels ..........................................................82

RGB Output Levels .....................................................................83

YPrPb Levels--SMPTE/EBU N10............................................84

Appendix 8--Video Standards ......................................................86

Outline Dimensions........................................................................88

Ordering Guide ...........................................................................88

REVISION HISTORY

10/04--Revision 0: Initial Version

ADV7320/ADV7321

Rev. 0 | Page 4 of 88

DETAILED FEATURES

High definition programmable features (720p/1080i/1035i)

2× oversampling (148.5 MHz)
Internal test pattern generator

Color hatch, black bar, flat field/frame

Fully programmable YCrCb to RGB matrix
Gamma correction
Programmable adaptive filter control
Programmable sharpness filter control
CGMS-A (720p/1080i)

Enhanced definition programmable features (525p/625p)

8× oversampling (216 MHz output)
Internal test pattern generator

Color hatch, black bar, flat frame

Individual Y and PrPb output delay
Gamma correction
Programmable adaptive filter control
Fully programmable YCrCb to RGB matrix
Undershoot limiter
Macrovision Rev 1.2 (525p/625p) (ADV7320 only)
CGMS-A (525p/625p)

Standard definition programmable features

16× oversampling (216 MHz)
Internal test pattern generator

Color bars, black bar

Controlled edge rates for start and end of active video
Individual Y and PrPb output delay
Undershoot limiter
Gamma correction
Digital noise reduction (DNR)
Multiple chroma and luma filters

Luma-SSAFTM filter with programmable gain/attenuation

PrPb SSAFTM

Separate pedestal control on component and

composite/S-video output

VCR FF/RW sync mode
Macrovision Rev 7.1.L1 (ADV7320 only)

CGMS/WSS
Closed captioning

Table 1. Standards Directly Supported

Resolution

Interlace/
Prog.

Frame
Rate
(Hz)

Clk
Input
(MHz)

Standard

720 × 480

29.97

ITU-R
BT.656

720 × 576

ITU-R
BT.656

720 × 480

29.97

24.54

NTSC
Square
Pixel

720 × 576

29.5

PAL Square
Pixel

720 × 483

59.94

SMPTE
293M

720 × 483

59.94

BTA T-1004

720 × 483

59.94

ITU-R
BT.1358

720 × 576

ITU-R
BT.1358

720 × 483

59.94

ITU-R
BT.1362

720 × 576

ITU-R
BT.1362

30 74.25

1920 × 1035

29.97 74.1758

SMPTE
240M

60, 50,
30, 25,
24,

74.25,

1280 × 720

23.97,
59.94,
29.97

74.1758

SMPTE
296M

30, 25

74.25

1920 × 1080

29.97 74.1758

SMPTE
274M

30, 25, 24

74.25

1920 × 1080

23.98,
29.97,

74.1758

SMPTE
274M

Other standards are supported in async timing mode.

ADV7320/ADV7321

Rev. 0 | Page 5 of 88

CLKIN_A

P_HSYNC

P_VSYNC

P_BLANK

S_HSYNC

S_VSYNC

S_BLANK

CLKIN_B

HD PIXEL

INPUT

SD PIXEL

INPUT

LUMA

AND

CHROMA

FILTERS

TEST

PATTERN

DNR

GAMMA

SYNC

INSERTION

PS 8

HDTV 2

RGB

MATRIX

SD 16

OVER-

SAMPLING

DAC

MODU-

LATION

CGMS

WSS

COLOR

CONTROL

DE-

INTER-

LEAVE

DE-

INTER-

LEAVE

TEST

PATTERN

Y COLOR

CR COLOR

CB COLOR

TIMING

GENERATOR

TIMING

GENERATOR

CLOCK

CONTROL

AND PLL

4:2:2

4:4:4

SHARPNESS

AND

ADAPTIVE

FILTER

CONTROL

05067-002

UV SSAF

Figure 2. Detailed Functional Block Diagram

TERMINOLOGY

SD: standard definition video, conforming to
ITU-R BT.601/ITU-R BT.656.

HD: high definition video, i.e., 720p/1080i/1035i.

EDTV: enhanced definition television (525p/625p)

PS: progressive scan video, conforming to SMPTE 293M,
ITU-R BT.1358, BTAT-1004EDTV2, or ITU-R BT.13621362.

HDTV: high definition television video, conforming to SMPTE
274M, or SMPTE 296M and SMPTE240M.

YCrCb SD, PS, or HD component: digital video.

YPrPb SD, PS, or HD component: analog video.

ADV7320/ADV7321

Rev. 0 | Page 6 of 88

SPECIFICATIONS

= 2.375 V to 2.625 V, V

DD_IO

= 2.375 V to 3.6 V, V

REF

= 1.235 V, R

SET

= 3040 , R

LOAD

= 300 . All

specifications T

MIN

to T

MAX

(0°C to 70°C), unless otherwise noted.

Table 2.

Parameter

Min

Typ

Max

Unit

Test Conditions

STATIC PERFORMANCE

Resolution

Bits

Integral Nonlinearity

1.5

LSB

Differential Nonlinearity,

+ve

0.25

LSB

Differential Nonlinearity,

-ve

1.5

LSB

DIGITAL OUTPUTS

Output Low Voltage, V

0.4 [0.4]

V I

SINK

= 3.2 mA

Output High Voltage, V

2.4 [2.0]

V I

SOURCE

= 400 µA

Three-State Leakage Current

±1.0

µA V

= 0.4 V, 2.4 V

Three-State Output Capacitance

DIGITAL AND CONTROL INPUTS

Input High Voltage, V

Input Low Voltage, V

0.8 V

Input Leakage Current

µA V

= 2.4 V

Input Capacitance, C

ANALOG OUTPUTS

Full-Scale Output Current

4.1

4.33

4.6

Output Current Range

4.1

4.33

4.6

DAC to DAC Matching

1.0

Output Compliance Range, V

0 1.0

1.4 V

Output Capacitance, C

OUT

VOLTAGE REFERENCE

Internal Reference Range, V

REF

1.15 1.235

1.3 V

External Reference Range, V

REF

1.15 1.235

1.3 V

REF

Current

±10

µA

POWER REQUIREMENTS

Normal Power Mode

137

SD only (16×)

PS only (8×)

HDTV only (2×)

140

190

SD (16×, 10 bit) + PS (8×, 20 bit)

DD_IO

1.0

Sleep Mode

µA

DD_IO

250

µA

POWER SUPPLY REJECTION RATIO

0.01

%/%

Oversampling disabled. Static DAC performance will be improved with increased oversampling ratios.

DNL measures the deviation of the actual DAC output voltage step from the ideal. For +ve DNL, the actual step value lies above the ideal step value; for -ve DNL, the

actual step value lies below the ideal step value.

Value in brackets for V

DD_IO

= 2.375 V to 2.75 V.

External current required to overdrive internal V

REF

, the circuit current, is the continuous current required to drive the digital core.

Guaranteed maximum by characterization.

All DACs on.

is the total current required to supply all DACs including the V

REF

circuitry and the PLL circuitry.

ADV7320/ADV7321

Rev. 0 | Page 7 of 88

DYNAMIC SPECIFICATIONS

= 2.375 V to 2.625 V, V

DD_IO

= 2.375 V to 3.6 V, V

REF

= 1.235 V, R

SET

= 3040 , R

LOAD

= 300 . All

specifications T

MIN

to T

MAX

(0°C to 70°C), unless otherwise noted.

Table 3.

Parameter

Min

Typ

Max

Unit

Test Conditions

PROGRESSIVE SCAN MODE

Luma Bandwidth

12.5

MHz

Chroma Bandwidth

5.8

MHz

SNR

65.6

Luma ramp unweighted

Flat field full bandwidth

HDTV MODE

Luma Bandwidth

MHz

Chroma Bandwidth

13.75

MHz

STANDARD DEFINITION MODE

Hue Accuracy

0.2

Degrees

Color Saturation Accuracy

0.20

Chroma Nonlinear Gain

0.84

±%

Referenced to 40 IRE

Chroma Nonlinear Phase

-0.2

± Degrees

Chroma/Luma Intermodulation

±%

Chroma/Luma Gain Inequality

96.7

±%

Chroma/Luma Delay Inequality

-1.0

Luminance Nonlinearity

0.2

±%

Chroma AM Noise

Chroma PM Noise

75.3

Differential Gain

0.25

NTSC

Differential Phase

0.2

Degrees

NTSC

SNR

63.5

Luma ramp

77.7

Flat field full bandwidth

ADV7320/ADV7321

Rev. 0 | Page 8 of 88

TIMING SPECIFICATIONS

= 2.375 V to 2.625 V, V

DD_IO

= 2.375 V to 3.6 V, V

REF

= 1.235 V, R

SET

= 3040 , R

LOAD

= 300 . All

specifications T

MIN

to T

MAX

(0°C to 70°C), unless otherwise noted.

Table 4.

Parameter

Min Typ Max

Unit

Test Conditions

MPU PORT

SCLOCK Frequency

400 kHz

SCLOCK High Pulse Width, t

0.6

µs

SCLOCK Low Pulse Width, t

1.3

µs

Hold Time (Start Condition), t

0.6

µs

First clock generated after this period relevant for
repeated start condition

Setup Time (Start Condition), t

0.6

µs

Data Setup Time, t

100

SDATA, SCLOCK Rise Time, t

300 ns

SDATA, SCLOCK Fall Time, t

300 ns

Setup Time (Stop Condition), t

0.6

µs

RESET Low Time

100

ANALOG OUTPUTS

Analog Output Delay

Output Skew

CLOCK CONTROL AND PIXEL PORT

CLK

29.5

MHz

SD PAL square pixel mode

CLK

MHz

PS/HD async mode

Clock High Time, t

% of one clk cycle

Clock Low Time, t

% of one clk cycle

Data Setup Time, t

2.0

Data Hold Time, t

2.0

SD Output Access Time, t

15 ns

SD Output Hold Time, t

5.0

HD Output Access Time, t

14 ns

HD Output Hold Time, t

5.0

PIPELINE DELAY

clk cycles

SD (2×, 16×)

clk cycles

SD component mode (16×)

clk cycles

PS (1×)

clk cycles

PS (8×)

clk cycles

HD (2×, 1×)

Guaranteed by characterization.

Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of DAC output full-scale transition.

Data: C[9:0]; Y[9:0], S[9:0]

Control: P_HSYNC, P_VSYNC, P_BLANK, S_HSYNC, S_VSYNC, S_BLANK

SD, PS = 27 MHz, HD = 74.25 MHz.

ADV7320/ADV7321

Rev. 0 | Page 10 of 88

CLKIN_A

C9C0

P_HSYNC,

P_VSYNC,

P_BLANK

CONTROL

INPUTS

Y9Y0

CONTROL

OUTPUTS

= CLOCK HIGH TIME

= CLOCK LOW TIME

= DATA SETUP TIME

= DATA HOLD TIME

S9S0

05067-005

Figure 5. HD RGB 4:4:4 Input Mode (Input Mode 010)

CLKIN_B*

*CLKIN_B MUST BE USED IN THIS PS MODE.

Y9Y0

= CLOCK HIGH TIME

= CLOCK LOW TIME

= DATA SETUP TIME

= DATA HOLD TIME

CONTROL

INPUTS

CONTROL

OUTPUTS

Yxxx

Crxxx

Cr0

Cb0

P_HSYNC,

P_VSYNC,

P_BLANK

05067-006

Figure 6. PS 4:2:2 10-Bit Interleaved at 27 MHz HSYNC/VSYNC Input Mode (Input Mode 100)

CLKIN_A

Y9Y0

= CLOCK HIGH TIME

= CLOCK LOW TIME

= DATA SETUP TIME

= DATA HOLD TIME

CONTROL

INPUTS

CONTROL

OUTPUTS

Yxxx

Crxxx

Cr0

Cb0

P_VSYNC,

P_HSYNC,
P_BLANK

05067-007

Figure 7. PS 4:2:2 10-Bit Interleaved at 54 MHz HSYNC /VSYNC Input Mode (Input Mode 111)

ADV7320/ADV7321

Rev. 0 | Page 11 of 88

CLKIN_B*

*CLKIN_B USED IN THIS PS ONLY MODE.

Y9Y0

= CLOCK HIGH TIME

= CLOCK LOW TIME

= DATA SETUP TIME

= DATA HOLD TIME

CONTROL

OUTPUTS

Cr0

Cb0

3FF

05067-008

Figure 8. PS Only 4:2:2 10-Bit Interleaved at 27 MHz EAV/SAV Input Mode (Input Mode 100)

CLKIN_A

Y9Y0

= CLOCK HIGH TIME

= CLOCK LOW TIME

= DATA SETUP TIME

= DATA HOLD TIME

CONTROL

OUTPUTS

NOTE: Y0, Cb0 SEQUENCE AS PER SUBADDRESS 0x01 BIT-1

3FF

Cb0

Cr0

05067-009

Figure 9. PS Only 4:2:2 10-Bit Interleaved at 54 MHz EAV/SAV Input Mode (Input Mode 111)

HD INPUT

SD INPUT

S9S0

CONTROL

INPUTS

CLKIN_A

CLKIN_B

Y9Y0

CONTROL

INPUTS

C9C0

P_HSYNC,

P_VSYNC,

P_BLANK

Cb1

Cr0

Cb0

S_HSYNC,

S_VSYNC,

S_BLANK

Cr4

Cb4

Cr2

Cb2

Cr0

Cb0

05067-010

Figure 10. HD 4:2:2 and SD (10-Bit) Simultaneous Input Mode (Input Mode 101: SD Oversampled) (Input Mode 110: HD Oversampled)

ADV7320/ADV7321

Rev. 0 | Page 16 of 88

ABSOLUTE MAXIMUM RATINGS

Table 5.

Parameter

Value

to AGND

-0.3 V to +3.0 V

to DGND

-0.3 V to +3.0 V

DD_IO

to GND_IO

-0.3 V to +4.6 V

Digital Input Voltage to DGND

-0.3 V to V

DD_IO

+0.3 V

to V

-0.3 V to +0.3 V

AGND to DGND

-0.3 V to +0.3 V

DGND to GND_IO

-0.3 V to +0.3 V

AGND to GND_IO

-0.3 V to +0.3 V

Ambient Operating Temperature (T

)

0°C to 70°C

Storage Temperature (T

)

65°C to +150°C

Infrared Reflow Soldering (20 s)

260°C

Analog output short circuit to any power supply or common can be of
an indefinite duration.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL CHARACTERISTICS

= 11°C/W

= 47°C/W

The ADV7320/ADV7321 is a Pb-free environmentally friendly
product. It is manufactured using the most up-to-date materials
and processes. The coating on the leads of each device is 100%
pure Sn electroplate. The device is suitable for Pb-free
applications and is able to withstand surface-mount soldering
up to 255°C (±5°C).

In addition, it is backward-compatible with conventional SnPb
soldering processes. This means that the electroplated Sn
coating can be soldered with Sn/Pb solder pastes at
conventional reflow temperatures of 220°C to 235°C.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
this product features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

ADV7320/ADV7321

Rev. 0 | Page 17 of 88

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

GND_

CLKIN_

DGND

S_H

SYN

S_VSYN

SET1

REF

COMP1

DAC C

DAC B

DAC A

S_BLANK

AGND

DAC D

DAC F

COMP2

SET2

EXT_LF

RESET

DAC E

DD_IO

DGND

ALS

P_H

SYN

P_VSYN

BLANK

RTC_

CR_

CLKIN_

PIN 1

ADV7320/ADV7321

TOP VIEW

(Not to Scale)

05067-019

Figure 19. Pin Configuration

Table 6. Pin Function Descriptions

Pin No.

Mnemonic

Input/Output Description

11, 57

DGND

Digital Ground.

AGND

Analog Ground.

CLKIN_A

Pixel Clock Input for HD (74.25 MHz Only, PS Only (27 MHz), SD Only (27 MHz).

CLKIN_B

Pixel Clock Input. Requires a 27 MHz reference clock for progressive scan mode or a 74.25 MHz
(74.1758 MHz) reference clock in HDTV mode. This clock is only used in dual modes.

45, 36

COMP1,
COMP2

Compensation Pin for DACs. Connect 0.1 µF capacitor from COMP pin to V

DAC A

CVBS/Green/Y/Y Analog Output.

DAC B

Chroma/Blue/U/Pb Analog Output.

DAC C

Luma/Red/V/Pr Analog Output.

DAC D

In SD Only Mode: CVBS/Green/Y Analog Output; in HD Only Mode and Simultaneous HD/SD
Mode: Y/Green [HD] Analog Output.

DAC E

In SD Only Mode: Luma/Blue/U Analog Output; in HD Only Mode and Simultaneous HD/SD
Mode: Pr/Red Analog Output.

DAC F

In SD Only Mode: Chroma/Red/V Analog Output; in HD Only Mode and Simultaneous HD/SD
Mode: Pb/Blue [HD] Analog Output.

P_HSYNC

Video Horizontal Sync Control Signal for HD in Simultaneous SD/HD Mode and HD Only Mode.

P_VSYNC

Video Vertical Sync Control Signal for HD in Simultaneous SD/HD Mode and HD Only Mode.

P_BLANK

Video Blanking Control Signal for HD in Simultaneous SD/HD Mode and HD Only Mode.

S_BLANK

I/O

Video Blanking Control Signal for SD Only.

S_VSYNC

I/O

Video Vertical Sync Control Signal for SD Only.

S_HSYNC

I/O

Video Horizontal Sync Control Signal for SD Only.

13,12,
92

Y9 to Y0

SD or Progressive Scan/HDTV Input Port for Y Data. Input port for interleaved progressive scan
data. The LSB is set up on Pin Y0. For 8-bit data input, LSB is set up on Y2.

3026,
1814

C9 to C0

Progressive Scan/HDTV Input Port 4:4:4 Input Mode. This port is used for the Cb[Blue/U] data.
The LSB is set up on Pin C0. For 8-bit data input, LSB is set up on C2.

ADV7320/ADV7321

Rev. 0 | Page 18 of 88

Pin No.

Mnemonic

Input/Output Description

6258,
5551

S9 to S0

SD or Progressive Scan/HDTV Input Port for Cr[Red/V] Data in 4:4:4 Input Mode. LSB is set up
on Pin S0. For 8-bit data input, LSB is set up on S2.

RESET

This input resets the on-chip timing generator and sets the ADV7320/ADV7321 into default
register setting. RESET is an active low signal.

47, 35

SET1

, R

SET2

A 3040 resistor must be connected from this pin to AGND and is used to control the
amplitudes of the DAC outputs.

SCLK

C Port Serial Interface Clock Input.

SDA

I/O

C Port Serial Data Input/Output.

ALSB

TTL Address Input. This signal sets up the LSB of the I

C address. When this pin is tied low, the

C filter is activated, which reduces noise on the I

C interface.

1 V

DD_IO

Power Supply for Digital Inputs and Outputs.

10, 56

Digital Power Supply.

41 V

Analog Power Supply.

46 V

REF

I/O

Optional External Voltage Reference Input for DACs or Voltage Reference Output (1.235 V).

EXT_LF

External Loop Filter for the Internal PLL.

RTC_SCR_TR I

Multifunctional Input. Real-time control (RTC) input, timing reset input, subcarrier reset input.

19 I

This input pin must be tied high (V

DD_IO

) for the ADV7320/ADV7321 to interface over the I

C port.

GND_IO

Digital Input/Output Ground.

ADV7320/ADV7321

Rev. 0 | Page 19 of 88

TYPICAL PERFORMANCE CHARACTERISTICS

FREQUENCY (MHz)

PROG SCAN Pr/Pb RESPONSE. LINEAR INTERP FROM 4:2:2 TO 4:4:4

GAIN (

70

60

50

40

30

20

10

80

200

100

120 140

160 180

05067-045

Figure 20. PS--UV 8× Oversampling Filter (Linear)

FREQUENCY (MHz)

PROG SCAN Pr/Pb RESPONSE. SSAF INTERP FROM 4:2:2 TO 4:4:4

GAIN (

70

60

50

40

30

20

10

80

200

100 120

140 160

180

05067-046

Figure 21. PS--UV 8× Oversampling Filter (SSAF)

FREQUENCY (MHz)

Y RESPONSE IN PS OVERSAMPLING MODE

GAIN (

70

60

50

40

30

20

10

80

200

100

120 140

160 180

05067-047

Figure 22. PS--Y 8× Oversampling Filter

FREQUENCY (MHz)

Y PASS BAND IN PS OVERSAMPLING MODE

GAIN (

2.5

2.0

1.5

1.0

0.5

1.0

3.0

05067-048

Figure 23. PS--Y 8× Oversampling Filter (Pass Band)

FREQUENCY (MHz)

Pr/Pb RESPONSE IN HDTV OVERSAMPLING MODE

GAIN (

70

60

50

40

30

20

10

80

140

100

120

05067-049

Figure 24. HDTV--UV 2× Oversampling Filter

FREQUENCY (MHz)

Y RESPONSE IN HDTV OVERSAMPLING MODE

GAIN (

70

60

50

40

30

20

10

80

140

100

120

05067-050

Figure 25. HDTV--Y 2× Oversampling Filter

ADV7320/ADV7321

Rev. 0 | Page 20 of 88

FREQUENCY (MHz)

MAGNITUDE

(dB)

10

30

50

60

70

20

40

05067-051

Figure 26. Luma NTSC Low-Pass Filter

FREQUENCY (MHz)

MAG

UDE

(dB)

10

30

50

60

70

20

40

05067-052

Figure 27. Luma PAL Low-Pass Filter

FREQUENCY (MHz)

MAGNITUDE

(dB)

10

30

50

60

70

20

40

05067-053

Figure 28. Luma NTSC Notch Filter

FREQUENCY (MHz)

MAGNITUDE

(dB)

10

30

50

60

70

20

40

05067-054

Figure 29. Luma PAL Notch Filter

FREQUENCY (MHz)

Y RESPONSE IN SD OVERSAMPLING MODE

GAIN (

50

80

100 120 140 160 180 200

10

40

60

70

20

30

05067-055

Figure 30. Y--16× Oversampling Filter

FREQUENCY (MHz)

MAGNITUDE

(dB)

10

30

50

60

70

20

40

05067-056

Figure 31. Luma SSAF Filter up to 12 MHz

ADV7320/ADV7321

Rev. 0 | Page 22 of 88

FREQUENCY (MHz)

MAGNITUDE

(dB)

10

30

50

60

70

20

40

05067-063

Figure 38. Chroma 2.0 MHz Low-Pass Filter

FREQUENCY (MHz)

MAGNITUDE

(dB)

10

30

50

60

70

20

40

05067-064

Figure 39. Chroma 1.3 MHz Low-Pass Filter

FREQUENCY (MHz)

MAGNITUDE

(dB)

10

30

50

60

70

20

40

05067-065

Figure 40. Chroma 1.0 MHz Low-Pass Filter

FREQUENCY (MHz)

MAG

UDE

(dB)

10

30

50

60

70

20

40

05067-066

Figure 41. Chroma 0.65 MHz Low-Pass Filter

FREQUENCY (MHz)

MAGNITUDE

(dB)

10

30

50

60

70

20

40

05067-067

Figure 42. Chroma CIF Low-Pass Filter

FREQUENCY (MHz)

MAGNITUDE

(dB)

10

30

50

60

70

20

40

05067-068

Figure 43. Chroma QCIF Low-Pass Filter

ADV7320/ADV7321

Rev. 0 | Page 23 of 88

MPU PORT DESCRIPTION

The ADV7320/ADV7321 support a 2-wire serial (I

C-

compatible) microprocessor bus driving multiple peripherals.
This port operates in an open-drain configuration. Two inputs,
serial data (SDA) and serial clock (SCL), carry information
between any device connected to the bus and the ADV7320/
ADV7321. Each slave device is recognized by a unique address.
The ADV7320/ADV7321 have four possible slave addresses for
both read and write operations. These are unique addresses for
each device and are illustrated in Figure 44. The LSB sets either
a read or write operation. Logic 1 corresponds to a read
operation, while Logic 0 corresponds to a write operation. A1 is
enabled by setting the ALSB pin of the ADV7320/ADV7321 to
Logic 0 or Logic 1. When ALSB is set to 1, there is greater input
bandwidth on the I

C lines, which allows high speed data

transfers on this bus. When ALSB is set to 0, there is reduced
input bandwidth on the I

C lines, which means that pulses of

less than 50 ns will not pass into the I

C internal controller. This

mode is recommended for noisy systems.

ADDRESS

CONTROL

SET UP BY

ALSB

READ/WRITE

CONTROL

0 WRITE

1 READ

05067-020

Figure 44. ADV7320 Slave Address = 0xD4

ADDRESS

CONTROL

SET UP BY

ALSB

READ/WRITE

CONTROL

0 WRITE

1 READ

05067-021

Figure 45. ADV7321 Slave Address = 0x54

To control the various devices on the bus, the following
protocol must be followed. First, the master initiates a data
transfer by establishing a start condition, defined by a high-to-
low transition on SDA while SCL remains high. This indicates
that an address/data stream will follow. All peripherals respond
to the start condition and shift the next eight bits (7-bit address
+ R/W bit). The bits are transferred from MSB down to LSB.
The peripheral that recognizes the transmitted address
responds by pulling the data line low during the ninth clock
pulse. This is known as an acknowledge bit. All other devices
withdraw from the bus at this point and maintain an idle
condition. The idle condition is where the device monitors the
SDA and SCL lines waiting for the start condition and the

correct transmitted address. The R/W bit determines the
direction of the data.

Logic 0 on the LSB of the first byte means that the master will
write information to the peripheral. Logic 1 on the LSB of the
first byte means that the master will read information from the
peripheral.

The ADV7320/ADV7321 act as standard slave devices on the
bus. The data on the SDA pin is eight bits long, supporting the
7-bit addresses plus the R/W bit. It interprets the first byte as
the device address and the second byte as the starting
subaddress. There is a subaddress auto-increment facility. This
allows data to be written to or read from registers in ascending
subaddress sequence starting at any valid subaddress. A data
transfer is always terminated by a stop condition. The user can
also access any unique subaddress register on a one-by-one
basis without updating all the registers.

Stop and start conditions can be detected at any stage during
the data transfer. If these conditions are asserted out of
sequence with normal read and write operations, then they
cause an immediate jump to the idle condition. During a given
SCL high period, the user should only issue a start condition, a
stop condition, or a stop condition followed by a start
condition. If an invalid subaddress is issued by the user, the
ADV7320/ADV7321 will not issue an acknowledge and will
return to the idle condition. If the user utilizes the auto-
increment method of addressing the encoder and exceeds the
highest subaddress, the following actions are taken:

· In read mode, the highest subaddress register contents are

output until the master device issues a no acknowledge. This
indicates the end of a read. A no acknowledge condition is
when the SDA line is not pulled low on the ninth pulse.

· In write mode, the data for the invalid byte is not loaded into

any subaddress register, a no acknowledge is issued by the
ADV7320/ADV7321, and the part returns to the idle
condition.

Before writing to the subcarrier frequency registers, it is required
to reset ADV7320/ADV7321 at least once after power-up.

The four subcarrier frequency registers must be updated,
starting with Subcarrier Frequency Register 0 and ending with
Subcarrier Frequency Register 3. The subcarrier frequency will
only update after the last subcarrier frequency register byte has
been received by the ADV7320/ADV7321.

Figure 46 illustrates an example of data transfer for a write
sequence and the start and stop conditions. Figure 47 shows bus
write and read sequences.

ADV7320/ADV7321

Rev. 0 | Page 25 of 88

The MPU can write to or read from all registers of the
ADV7320/ADV7321 except the subaddress registers, which are
write only registers. The subaddress register determines which
register the next read or write operation will access. All
communication with the part through the bus starts with an
access to the subaddress register. A read/write operation is then
performed from/to the target address, which increments to the
next address until a stop command is performed on the bus.

REGISTER PROGRAMMING

The following tables describe the functionality of each register.
All registers can be read from as well as written to, unless
otherwise stated.

SUBADDRESS REGISTER (SR7 TO SR0)

The communication register is an 8-bit write only register. After
the encoder's bus is accessed and a read/write operation is
selected, the subaddress is set up. The subaddress register
determines to or from which register the operation takes place.

Table 7. Registers 0x00 to 0x01

SR7
SR0

Register

Bit Description

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Register Setting

Reg. Reset
Values
(Shaded)

Sleep

mode

off.

0xFC

Sleep Mode. With this
control enabled, the
current consumption is
reduced to µA level. All
DACs and the internal PLL
cct are disabled. I

registers can be read from
and written to in sleep
mode.

Sleep mode on.

PLL

on.

PLL and Oversampling
Control. This control
allows the internal PLL cct
to be powered down and
the oversampling to be
switched off.

PLL

off.

DAC

off.

DAC F: Power On/Off.

DAC F on.

DAC

off.

DAC E: Power On/Off.

DAC

on.

DAC

off.

DAC D: Power On/Off.

DAC D on.

DAC

off.

DAC C: Power On/Off.

DAC

on.

DAC B off.

DAC B: Power On/Off.

DAC B on.

DAC

off.

0x00

Power
Mode
Register

DAC A: Power On/Off.

DAC

on.

Reserved.

clocked

upon

rising

edge.

Clock Edge.

Y clocked upon rising
edge.

Only for PS
interleaved
input at 27 MHz.

Reserved.

Clock Align.

Must be set if the phase
delay between the two
input clocks is <9.25 ns
or >27.75 ns.

Only if two
input clocks are
used.

SD input only.

0x38

PS input only.

HDTV input only.

SD and PS (20-bit).

SD and PS (10-bit).

SD and HDTV (SD
oversampled).

SD and HDTV (HDTV
oversampled).

Input Mode.

PS only (at 54 MHz).

0x01 Mode

Select
Register

Y/C/S Bus Swap.

Allows data to be
applied to data ports in
various configurations
(SD feature only).

See Table 21.

ADV7320/ADV7321

Rev. 0 | Page 26 of 88

Table 8. Registers 0x02 to 0x0F

SR7
SR0

Register

Bit Description

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Register Setting

Reset Values

Reserved

Zero must be written to
these bits.

0x20

Disabled.

Test Pattern Black
Bar

Enabled.

0x11, Bit 2 must
also be enabled.

Disable

manual

RGB

matrix

adjust.

Manual RGB
Matrix Adjust

Enable

manual

RGB

matrix

adjust.

No sync.

Sync on RGB

Sync on all RGB outputs.

RGB component outputs.

RGB/YPrPb
Output

YPrPb component outputs.

No sync output.

SD Sync

Output SD syncs on
S_HSYNC, S_VSYNC,
S_BLANK pins.

No sync output.

0x02

Mode Register 0

HD Sync

Output HD, ED, syncs on
S_HSYNC, S_VSYNC.

0x03

RGB Matrix 0

LSB for GY.

0x03

LSB for RV.

0xF0

LSB for BU.

LSB for GV.

0x04

RGB Matrix 1

LSB for GU.

0x05

RGB Matrix 2

Bits 9 to 2 for GY.

0x4E

0x06

RGB Matrix 3

Bits 9 to 2 for GU.

0x0E

0x07

RGB Matrix 4

Bits 9 to 2 for GV.

0x24

0x08

RGB Matrix 5

Bits 9 to 2 for BU.

0x92

0x09

RGB Matrix 6

Bits 9 to 2 for RV.

0x7C

0x0A

DAC A, B, C Output
Level

Positive Gain to
DAC Output
Voltage

0x00

+0.018%

+0.036%

...

+7.382%

+7.5%

Negative

Gain

DAC Output
Voltage

-7.5%

-7.382%

-7.364%

...

-0.018%

0x0B

DAC D, E, F Output
Level

Positive Gain to
DAC Output
Voltage

0x00

+0.018%

+0.036%

...

+7.382%

+7.5%

Negative

Gain

DAC Output
Voltage

-7.5%

-7.382%

-7.364%

...

-0.018%

0x0C

Reserved

0x00

0x0D

Reserved

0x00

0x0E

Reserved

0x00

0x0F

Reserved

0x00

For more detail, refer to Appendix 7.

For more detail on the programmable output levels, refer to the Programmable DAC Gain Control section.

ADV7320/ADV7321

Rev. 0 | Page 27 of 88

Table 9. Registers 0x10 to 0x11

SR7
SR0

Register

Bit Description

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Register Setting

Note

Reset
Values

EIA770.2

output

0x00

EIA770.1

output

Output levels for
full input range

HD Output
Standard

Reserved

HSYNC, VSYNC,
BLANK

Input Sync
Format

EAV/SAV

codes

0 0 0 0 0 SMPTE 293M, ITU-

BT 1358

525p @
59.94 Hz

0 0 0 0 1 Async

mode

0 0 0 1 0 BTA-1004, ITU-

BT 1362

525p @
59.94 Hz

0 0 0 1 1 ITU-BT

1358 625p @

50 Hz

0 0 1 0 0 ITU-BT

1362 625p @

50 Hz

0 0 1 0 1 SMPTE

296M-1,

720p @
60/59.94 Hz

0 0 1 1 0 SMPTE

296M-3

720p @
50 Hz

0 0 1 1 1 SMPTE

296M-4,

720p @
30/29.97 Hz

0 1 0 0 0 SMPTE

296M-6

720p @
25 Hz

0 1 0 0 1 SMPTE

296M-7,

720p @
24/23.98 Hz

0 1 0 1 0 SMPTE

240M

1035i @

60/59.94 Hz

0 1 0 1 1 Reserved

0 1 1 0 0 Reserved

0 1 1 0 1 SMPTE

274M-4,

1080i @
30/29.97 Hz

0 1 1 1 0 SMPTE

274M-6

1080i @
25 Hz

0 1 1 1 1 SMPTE

274M-7,

1080p @
30/29.97 Hz

1 0 0 0 0 SMPTE

274M-9

1080p @
25 Hz

1 0 0 0 1 SMPTE 274M-

10, 11

1080p @
24/23.98 Hz

0x10

HD Mode
Register 1

HD/ED Input
Mode

1001011111

Reserved

Pixel

data

valid

off

Pixel

data

valid

0x00

HD Pixel Data
Valid

Reserved

test

pattern

off

HD Test Pattern
Enable

test

pattern

Hatch

HD Test Pattern
Hatch/Field

Field/frame

Disabled

HD VBI Open

Enabled

Disabled

-11 IRE

-6 IRE

HD Undershoot
Limiter

-1.5 IRE

Only
available in
EDTV
(525p/625p)

Disabled

0x11

HD Mode
Register 2

HD Sharpness
Filter

Enabled

ADV7320/ADV7321

Rev. 0 | Page 28 of 88

Table 10. Register 0x12

SR7
SR0

Register

Bit Description

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Register Setting

Reset
Values

0 clk cycles

0x00

1 clk cycles

2 clk cycles

3 clk cycles

HD Y Delay with Respect
to Falling Edge of HSYNC

4 clk cycles

0 clk cycles

1 clk cycle

2 clk cycles

3 clk cycles

HD Color Delay with
Respect to Falling Edge of
HSYNC

4 clk cycles

Disabled

HD CGMS

Enabled

Disabled

0x12

HD Mode
Register 3

HD CGMS CRC

Enabled

Table 11. Registers 0x13 to 0x14

SR7
SR0

Register

Bit Description

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Register Setting

Reset
Values

Cb after falling edge of HSYNC.

0x4C

HD Cr/Cb Sequence

after

falling

edge

HSYNC.

Reserved

0 must be written to this bit.

8-bit

input.

HD Input Format

10-bit

input.

Disabled.

Sinc Filter on DAC D, E, F

Enabled.

Reserved

0 must be written to this bit.

Disabled.

HD Chroma SSAF

Enabled.

4:4:4

HD Chroma Input

4:2:2

Disabled.

0x13

HD Mode
Register 4

HD Double Buffering

Enabled.

HD Timing Reset

A low-high-low transition
resets the internal HD timing
counters.

0x00

HD Hsync Generation

HD Vsync Generation

Refer to the / Output Control
section.

BLANK active high.

HD Blank Polarity

BLANK active low.

Macrovision

disabled.

HD Macrovision for 525p
and 625p

Macrovision

enabled.

Reserved

0 must be written to these bits.

field

input.

HD VSYNC/Field Input

VSYNC input.

Update

field/line

counter.

0x14

HD Mode
Register 5

Horizontal/Vertical
Counters

Field/line

counter

free

running.

Used in conjunction with HD_SYNC in Register 0x02, Bit 7 set to 1.

When set to 0, the horizontal/vertical counters automatically wrap around at the end of the line/field/frame of the standard selected. When set to 1, the

horizontal/vertical counters are free running and wrap around when external sync signals indicate to do so.

ADV7320/ADV7321

Rev. 0 | Page 30 of 88

Table 13. Registers 0x16 to 0x37

SR7
SR0

Register

Bit Description

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset
Values

0x16

HD Y Level

Y level value

0xA0

0x17

HD Cr Level

Cr level value

0x80

0x18

HD Cb Level

Cb level value

0x80

0x19

Reserved

0x00

0x1A

Reserved

0x00

0x1B

Reserved

0x00

0x1C

Reserved

0x00

0x1D

Reserved

0x00

0x1E

Reserved

0x00

0x1F

Reserved

0x00

Gain A = 0

0x00

Gain A = +1

...

... ...

...

Gain A = +7

Gain A = -8

...

... ...

...

HD Sharpness Filter Gain Value A

Gain A = -1

Gain B = 0

Gain B = +1

... ... ... ...

...

Gain B = +7

Gain B = -8

... ... ... ...

...

0x20

HD Sharpness
Filter Gain

HD Sharpness Filter Gain Value B

Gain B = -1

0x21

HD CGMS Data 0

HD CGMS Data Bits

C19

C18

C17

C16

CGMS 19 to 16

0x00

0x22

HD CGMS Data 1

HD CGMS Data Bits

C15

C14

C13

C12

C11

C10

CGMS 15 to 8

0x00

0x23

HD CGMS Data 2

HD CGMS Data Bits

CGMS 7 to 0

0x00

0x24

HD Gamma A

HD Gamma Curve A Data Points

0x00

0x25

HD Gamma A

HD Gamma Curve A Data Points

0x00

0x26

HD Gamma A

HD Gamma Curve A Data Points

0x00

0x27

HD Gamma A

HD Gamma Curve A Data Points

0x00

0x28

HD Gamma A

HD Gamma Curve A Data Points

0x00

0x29

HD Gamma A

HD Gamma Curve A Data Points

0x00

0x2A

HD Gamma A

HD Gamma Curve A Data Points

0x00

0x2B

HD Gamma A

HD Gamma Curve A Data Points

0x00

0x2C

HD Gamma A

HD Gamma Curve A Data Points

0x00

0x2D

HD Gamma A

HD Gamma Curve A Data Points

0x00

0x2E

HD Gamma B

HD Gamma Curve B Data Points

0x00

0x2F

HD Gamma B

HD Gamma Curve B Data Points

0x00

0x30

HD Gamma B

HD Gamma Curve B Data Points

0x00

0x31

HD Gamma B

HD Gamma Curve B Data Points

0x00

0x32

HD Gamma B

HD Gamma Curve B Data Points

0x00

0x33

HD Gamma B

HD Gamma Curve B Data Points

0x00

0x34

HD Gamma B

HD Gamma Curve B Data Points

0x00

0x35

HD Gamma B

HD Gamma Curve B Data Points

0x00

0x36

HD Gamma B

HD Gamma Curve B Data Points

0x00

0x37

HD Gamma B

HD Gamma Curve B Data Points

0x00

For use with internal test pattern only.

ADV7320/ADV7321

Rev. 0 | Page 31 of 88

Table 14. Registers 0x38 to 0x3D

SR7
SR0

Register

Bit Description

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset
Values

Gain A = 0

0x00

Gain A = +1

...

Gain A = +7

Gain A = -8

...

HD Adaptive Filter
Gain 1 Value A

Gain A = -1

Gain B = 0

Gain B = +1

... ... ... ...

...

Gain B = +7

Gain B = -8

... ... ... ...

...

0x38

HD Adaptive Filter
Gain 1

HD Adaptive Filter
Gain 1 Value B

Gain B = -1

Gain A = 0

0x00

Gain A = +1

...

Gain A = +7

Gain A = -8

...

HD Adaptive Filter
Gain 2 Value A

Gain A = -1

Gain B = 0

Gain B = +1

... ... ... ...

...

Gain B = +7

Gain B = -8

... ... ... ...

...

0x39

HD Adaptive Filter
Gain 2

HD Adaptive Filter
Gain 2 Value B

Gain B = -1

Gain A = 0

0x00

Gain A = +1

...

Gain A = +7

Gain A = -8

...

HD Adaptive Filter
Gain 3 Value A

Gain A = -1

Gain B = 0

Gain B = +1

... ... ... ...

...

Gain B = +7

Gain B = -8

... ... ... ...

...

0x3A

HD Adaptive Filter
Gain 3

HD Adaptive Filter
Gain 3 Value B

Gain B = -1

0x3B

HD Adaptive Filter
Threshold A

Threshold A

0x00

0x3C

HD Adaptive Filter
Threshold B

Threshold B

0x00

0x3D

HD Adaptive Filter
Threshold C

Threshold C

0x00

ADV7320/ADV7321

Rev. 0 | Page 32 of 88

Table 15. Registers 0x3E to 0x43

SR7
SR0

Register

Bit Description

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Register Setting

Reset
Values

0x3E

Reserved

0x00

0x3F

Reserved

0x00

NTSC

0x00

PAL B, D, G, H, I

PAL M

SD Standard

PAL N

LPF NTSC

LPF PAL

Notch NTSC

Notch PAL

SSAF luma

Luma CIF

Luma QCIF

SD Luma Filter

Reserved

1.3 MHz

0.65 MHz

1.0 MHz

2.0 MHz

Reserved

Chroma CIF

Chroma QCIF

0x40

SD Mode Register 0

SD Chroma Filter

3.0 MHz

0x41

Reserved

0x00

Disabled

SD PrPb SSAF

Enabled

0x08

Refer to output
configuration section

SD DAC Output 1

Refer to output
configuration section

SD DAC Output 2

Disabled

SD Pedestal

Enabled

Disabled

SD Square Pixel

Enabled

Disabled

SD VCR FF/RW Sync

Enabled

Disabled

SD Pixel Data Valid

Enabled

Disabled

0x42

SD Mode Register 1

SD SAV/EAV Step
Edge Control

Enabled

No pedestal on YUV

SD Pedestal YPrPb
Output

7.5

IRE

pedestal

YUV

0x00

Y = 700 mV/300 mV

SD Output Levels Y

Y = 714 mV/286 mV

700 mV p-p (PAL); 1000
mV p-p (NTSC)

700 mV p-p

1000 mV p-p

SD Output Levels PrPb

648 mV p-p

Disabled

SD VBI Open

Enabled

disabled

CC on odd field only

CC on even field only

SD CC Field Control

CC on both fields

0x43

SD Mode Register 2

Reserved

ADV7320/ADV7321

Rev. 0 | Page 33 of 88

Table 16. Registers 0x44 to 0x49

SR7
SR0

Register

Bit Description

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Register Setting

Reset
Values

Disabled

SD VSYNC-3H

VSYNC= 2.5 lines (PAL),
VSYNC= 3 lines (NTSC)

0x00

Genlock

disabled

Subcarrier

Reset

Timing

Reset

SD RTC/TR/SCR

RTC

enabled

720

pixels

SD Active Video Length

710

(NTSC)/702

(PAL)

Chroma

enabled

SD Chroma

Chroma

disabled

Enabled

SD Burst

Disabled

SD Color Bars

Enabled

DAC A = luma, DAC B = chroma

0x44 SD

Mode

SD DAC Swap

DAC A = chroma, DAC B = luma

0x45

Reserved

0x00

5.17

5.31

(default)

0x01

5.59

(must

set

for

Macrovision compliance)

0x46 SD

Mode

NTSC Color Subcarrier
Adjust (Falling Edge of
HS to Start of Color
Burst)

Reserved

Disabled

SD PrPb Scale

Enabled

0x00

Disabled

SD Y Scale

Enabled

Disabled

SD Hue Adjust

Enabled

Disabled

SD Brightness

Enabled

Disabled

SD Luma SSAF Gain

Enabled

Reserved

0 must be written to this bit

Reserved

0 must be written to this bit

0x47 SD

Mode

Reserved

0 must be written to this bit

Reserved

0x00

Reserved

0 must be written to this bit

Disabled

SD Double Buffering

Enabled

8-bit input

16-bit input

10-bit input

SD Input Format

20-bit input

Disabled

SD Digital Noise
Reduction

Enabled

Disabled

SD Gamma Control

Enabled

Gamma

Curve

0x48 SD

Mode

SD Gamma Curve

Gamma

Curve

Disabled

0x00

-11

IRE

-6 IRE

SD Undershoot Limiter

-1.5 IRE

Reserved

0 must be written to this bit

Disabled

SD Black Burst Output on
DAC Luma

Enabled

Disabled

4 clk cycles

8 clk cycles

SD Chroma Delay

Reserved

0 must be written to this bit

0x49 SD

Mode

Reserved

0 must be written to this bit

NTSC color bar adjust should be set to 10 b for macrovision compliance (ADV7320 only).

ADV7320/ADV7321

Rev. 0 | Page 34 of 88

Table 17. Registers 0x4A to 0x58

SR7
SR0

Register

Bit Description

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Register Setting

Reset
Value

Slave mode.

SD Slave/Master
Mode

Master

mode.

0x08

Mode 0.

Mode 1.

Mode 2.

SD Timing Mode

Mode 3.

Enabled.

SD BLANK Input

Disabled.

delay.

2 clk cycles.

4 clk cycles.

SD Luma Delay

6 clk cycles.

-40 IRE.

SD Min. Luma
Value

-7.5

IRE.

0x4A SD

Timing

SD Timing Reset

A low-high-low transition will
reset the internal SD timing
counters.

= 1 clk cycle.

= 4 clk cycles.

= 16 clk cycles.

SD HSYNC Width

= 128 clk cycles.

0x00

= 0 clk cycle.

= 4 clk cycles.

= 8 clk cycles.

SD HSYNCto
VSYNC Delay

= 18 clk cycles.

= T

SD HSYNC to VSYNC
Rising Edge Delay
(Mode 1 Only)

= T

+ 32 µs.

1 clk cycle.

4 clk cycles.

16 clk cycles.

VSYNC Width
(Mode 2 Only)

128 clk cycles.

clk

cycles.

clk

cycle.

clk

cycles.

0x4B SD

Timing

HSYNC to Pixel
Data Adjust

clk

cycles.

0x4C SD

Subcarrier Frequency Bits 7 to 0.

0x1E

0x4D SD

Subcarrier Frequency Bits 15 to 8.

0x7C

0x4E SD

Subcarrier Frequency Bits 23 to 16.

0xF0

0x4F SD

Subcarrier Frequency Bits 31 to 24.

0x21

0x50 SD

Phase

Subcarrier Phase Bits 9 to 2.

0x00

0x51 SD

Closed

Captioning

Extended Data on
Even Fields

Extended Data Bits 7 to 0.

0x00

0x52 SD

Closed

Captioning

Extended Data on
Even Fields

Extended Data Bits 15 to 8.

0x00

0x53 SD

Closed

Captioning

Data on Odd Fields

Data Bits 7 to 0.

0x00

0x54 SD

Closed

Captioning

Data on Odd Fields

Data Bits 15 to 8.

0x00

0x55 SD

Pedestal

Pedestal on Odd
Fields

Setting any of these bits to 1 will
disable pedestal on the line num-
ber indicated by the bit settings.

0x00

0x56 SD

Pedestal

Pedestal on Odd
Fields

0x00

0x57 SD

Pedestal

Pedestal on Even
Fields

0x00

0x58 SD

Pedestal

Pedestal on Even
Fields

0x00

For precise NTSC Fsc, this register should be programmed to 0x1F.

LINE 313

LINE 314

LINE 1

05067-024

HSYNC

VSYNC

Figure 48. Timing Register 1 in PAL Mode

ADV7320/ADV7321

Rev. 0 | Page 35 of 88

Table 18. Registers 0x59 to 0x64

SR7
SR0

Register

Bit Description

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Register Setting

Reset
Values

SD CGMS Data

CGMS Data Bits C19 to C16

0x00

Disabled

SD CGMS CRC

Enabled

Disabled

SD CGMS on Odd
Fields

Enabled

Disabled

SD CGMS on Even
Fields

Enabled

Disabled

0x59

SD CGMS/WSS 0

SD WSS

Enabled

CGMS Data Bits C13 to C8,
or WSS Data Bits C13 to C8

0x00

0x5A

SD CGMS/WSS 1

SD CGMS/WSS Data

CGMS Data Bits C15 to C14

0x00

0x5B

SD CGMS/WSS 2

SD CGMS/WSS Data

CGMS/WSS Data Bits C7 to
C0

0x00

SD LSB for Y Scale
Value

SD Y Scale Bits 1 to 0

SD LSB for Cb Scale
Value

SD Cb Scale Bits 1 to 0

SD LSB for Cr Scale
Value

SD Cr Scale Bits 1 to 0

0x5C

SD LSB Register

SD LSB for F

Phase

x x Subcarrier

Phase

Bits

0x5D

SD Y Scale
Register

SD Y Scale Value

SD Y Scale Bits 7 to 2

0x00

0x5E

SD Cb Scale
Register

SD Cb Scale Value

SD Cb Scale Bits 7 to 2

0x00

0x5F

SD Cr Scale
Register

SD Cr Scale Value

SD Cr Scale Bits 7 to 2

0x00

0x60

SD Hue Register

SD Hue Adjust Value

SD Hue Adjust Bits 7 to 0

0x00

SD Brightness Value

SD Brightness Bits 6 to 0

0x00

Disabled

0x61 SD

Brightness/

WSS

SD Blank WSS Data

Enabled

Line 23

-4 dB

0 dB

0x62

SD Luma SSAF

SD Luma SSAF
Gain/Attenuation

+4 dB

0x00

No gain

0x00

+1/16 [1/8]

+2/16 [2/8]

+3/16 [3/8]

+4/16 [4/8]

+5/16 [5/8]

+6/16 [6/8]

+7/16 [7/8]

Coring Gain Border

+8/16 [1]

In DNR
mode,
the
values in
brackets
apply.

No gain

+1/16 [1/8]

+2/16 [2/8]

+3/16 [3/8]

+4/16 [4/8]

+5/16 [5/8]

+6/16 [6/8]

+7/16 [7/8]

0x63

SD DNR 0

Coring Gain Data

+8/16 [1]

...

DNR Threshold

0x00

pixels

Border Area

pixels

0x64

SD DNR 1

Block Size Control

pixels

ADV7320/ADV7321

Rev. 0 | Page 36 of 88

Table 19. Registers 0x65 to 0x7C

SR7
SR0

Register

Bit Description

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Register Setting

Reset
Values

Filter

Filter B

Filter

DNR Input Select

Filter D

0x00

DNR

mode

DNR Mode

DNR

sharpness

mode

0 pixel offset

1 pixel offset

...

14 pixel offset

0x65

SD DNR 2

DNR Block Offset

15 pixel offset

0x66

SD Gamma A

SD Gamma Curve A Data Points

0x00

0x67

SD Gamma A

SD Gamma Curve A Data Points

0x00

0x68

SD Gamma A

SD Gamma Curve A Data Points

0x00

0x69

SD Gamma A

SD Gamma Curve A Data Points

0x00

0x6A

SD Gamma A

SD Gamma Curve A Data Points

0x00

0x6B

SD Gamma A

SD Gamma Curve A Data Points

0x00

0x6C

SD Gamma A

SD Gamma Curve A Data Points

0x00

0x6D

SD Gamma A

SD Gamma Curve A Data Points

0x00

0x6E

SD Gamma A

SD Gamma Curve A Data Points

0x00

0x6F

SD Gamma A

SD Gamma Curve A Data Points

0x00

0x70

SD Gamma B

SD Gamma Curve B Data Points

0x00

0x71

SD Gamma B

SD Gamma Curve B Data Points

0x00

0x72

SD Gamma B

SD Gamma Curve B Data Points

0x00

0x73

SD Gamma B

SD Gamma Curve B Data Points

0x00

0x74

SD Gamma B

SD Gamma Curve B Data Points

0x00

0x75

SD Gamma B

SD Gamma Curve B Data Points

0x00

0x76

SD Gamma B

SD Gamma Curve B Data Points

0x00

0x77

SD Gamma B

SD Gamma Curve B Data Points

0x00

0x78

SD Gamma B

SD Gamma Curve B Data Points

0x00

0x79

SD Gamma B

SD Gamma Curve B Data Points

0x00

0x7A

SD Brightness
Detect

SD Brightness Value

Read only

Field Count

Read only

Reserved

0x7B

Field Count
Register

Revision

Code

Read

only

0x8x

0x7C

Reserved

0x00

ADV7320/ADV7321

Rev. 0 | Page 37 of 88

Table 20. Registers 0x7D to 0x91

SR7-
SR0

Register

Bit Description

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Register Setting

Reset
Values

0x7D

Reserved

0x7E

Reserved

0x7F

Reserved

0x80 Macrovision

MV Control Bits

0x00

0x81

Macrovision

MV Control Bits

0x00

0x82

Macrovision

MV Control Bits

0x00

0x83

Macrovision

MV Control Bits

0x00

0x84

Macrovision

MV Control Bits

0x00

0x85

Macrovision

MV Control Bits

0x00

0x86

Macrovision

MV Control Bits

0x00

0x87

Macrovision

MV Control Bits

0x00

0x88

Macrovision

MV Control Bits

0x00

0x89

Macrovision

MV Control Bits

0x00

0x8A

Macrovision

MV Control Bits

0x00

0x8B

Macrovision

MV Control Bits

0x00

0x8C

Macrovision

MV Control Bits

0x00

0x8D

Macrovision

MV Control Bits

0x00

0x8E

Macrovision

MV Control Bits

0x00

0x8F

Macrovision

MV Control Bits

0x00

0x90

Macrovision

MV Control Bits

0x00

0x91

Macrovision

MV Control Bit

0 must be written to these bits

0x00

Macrovision registers only on the ADV7320.

ADV7320/ADV7321

Rev. 0 | Page 38 of 88

INPUT CONFIGURATION

When 10-bit input data is applied, the following bits must be set
to 1:

Address 0x13, Bit 2 (HD 10-bit enable)
Address 0x48, Bit 4 (SD 10-bit enable)

Note that the ADV7320 defaults to simultaneous standard
definition and progressive scan upon power-up (Address[0x01]:
Input Mode = 011).

STANDARD DEFINITION ONLY

Address[0x01]: Input Mode = 000

The 8-/10-bit, multiplexed input data is input on Pins S9 to S0
(or Pins Y9 to Y0, depending on Register Address 0x01, Bit 7),
with S0 being the LSB in 10-bit input mode (see Table 21). Input
standards supported are ITU-R BT.601/656. In 16-/20-bit input
mode, the Y pixel data is input on Pins S9 to S2 and CrCb data
is input on Pins Y9 to Y2 (see Table 21).

16-/20-Bit Mode Operation

When Register 0x01 Bit 7 = 0, CrCb data is input on the Y bus
and Y data is input on the S bus. When Register 0x01 Bit 7 = 1,
CrCb data is input on the C bus and Y data is input on Y bus.

The 27 MHz clock input must be input on Pin CLKIN_A. Input
sync signals are input on the S_VSYNC, S_HSYNC, and
S_BLANK pins.

Table 21. SD 8-/10-Bit and 16-/20-Bit Configuration

Configuration

Parameter

8-/10-Bit Mode

16-/20-Bit Mode

Y Bus

CrCb

S Bus

656/601, YCrCb

C Bus

Y Bus

656/601, YCrCb

S Bus

C Bus

CrCb

MPEG2

DECODER

CLKIN_A

S[9:0] OR Y[9:0]*

27MHz

YCrCb

ADV7320/

ADV7321

*SELECTED BY ADDRESS 0x01 BIT 7

05067-025

S_VSYNC,

S_HSYNC,
S_BLANK

Figure 49. SD Only Input Mode

PROGRESSIVE SCAN ONLY OR HDTV ONLY

Address[0x01]: Input Mode = 001 or 010, Respectively

YCrCb progressive scan, HDTV, or any other HD YCrCb data
can be input in 4:2:2 or 4:4:4. In 4:2:2 input mode, the Y data is
input on Pins Y9 to Y0 and the CrCb data is input on Pins C9 to
C0. In 4:4:4 input mode, Y data is input on Pins Y9 to Y0, Cb data
is input on Pins C9 to C0, and Cr data is input on Pins S9 to S0.
If the YCrCb data does not conform to SMPTE 293M (525p),
ITU-R BT.1358M (625p), SMPTE 274M (1080i), SMPTE 296M
(720p), SMPTE 240M (1035i), or BTA-T1004/1362, the async
timing mode must be used. RGB data can only be input in
4:4:4 format in PS or HDTV input modes when HD RGB input
is enabled. G data is input on Pins Y9 to Y0, R data is input on
Pins S9 to S0, and B data is input on Pins C9 to C0. The clock
signal must be input on Pin CLKIN_A.

MPEG2

DECODER

CLKIN_A

C[9:0]

S[9:0]

Y[9:0]

INTERLACED TO

PROGRESSIVE

YCrCb

27MHz

ADV7320/

ADV7321

05067-026

P_VSYNC,

P_HSYNC,
P_BLANK

Figure 50. Progressive Scan Input Mode

SIMULTANEOUS STANDARD DEFINITION AND
PROGRESSIVE SCAN OR HDTV

Address[0x01]: Input Mode 011 (SD 10-Bit, PS 20-Bit) or 101
(SD and HD, SD Oversampled), 110 (SD and HD, HD
Oversampled), Respectively

YCrCb PS and HD data must be input in 4:2:2 format. In 4:2:2
input mode, the HD Y data is input on Pins Y9 to Y0 and the
HD CrCb data is input on Pins C9 to C0. If PS 4:2:2 data is
interleaved onto a single 10-bit bus, Pins Y9 to Y0 are used for
the input port. The input data is to be input at 27 MHz, with the
data being clocked upon the rising and falling edges of the input
clock. The input mode register at Address 0x01 is set
accordingly. If the YCrCb data does not conform to SMPTE
293M (525p), ITU-R BT.1358M (625p), SMPTE 274M (1080i),
SMPTE 296M (720p), SMPTE 240M (1035i), or BTA-T1004,
the async timing mode must be used.

The 8- or 10-bit standard definition data must be compliant
with ITU-R BT.601/656 in 4:2:2 format. Standard definition
data is input on Pins S9 to S0, with S0 being the LSB. Using
8-bit input format, the data is input on Pins S9 to S2. The clock
input for SD must be input on CLKIN_A, and the clock input
for HD must be input on CLKIN_B. Synchronization signals are

ADV7320/ADV7321

Rev. 0 | Page 39 of 88

optional. SD syncs are input on Pins S_VSYNC, S_HSYNC, and
S_BLANK. HD syncs are input on Pins P_VSYNC, P_HSYNC,
and P_BLANK.

CLKIN_A

CLKIN_B

MPEG2

DECODER

27MHz

YCrCb

INTERLACED TO

PROGRESSIVE

CrCb

27MHz

S[9:0]

C[9:0]

Y[9:0]

ADV7320/

ADV7321

05067-027

S_VSYNC,

S_HSYNC,
S_BLANK

P_VSYNC,

P_HSYNC,
P_BLANK

Figure 51. Simultaneous PS and SD Input

CLKIN_A

CLKIN_B

SDTV

DECODER

27MHz

YCrCb

CrCb

74.25MHz

1080i

720p

1035i

S[9:0]

C[9:0]

Y[9:0]

ADV7320/

ADV7321

HDTV

DECODER

05067-028

S_VSYNC,

S_HSYNC,
S_BLANK

P_VSYNC,

P_HSYNC,
P_BLANK

Figure 52. Simultaneous HD and SD Input

In simultaneous SD/HD input mode, if the two clock phases
differ by less than 9.25 ns or more than 27.75 ns, the clock align
bit [Address 0x01, Bit 3] must be set accordingly. If the
application uses the same clock source for both SD and PS, the
clock align bit must be set because the phase difference between
both inputs is less than 9.25 ns.

CLKIN_A

CLKIN_B

05067-029

DELAY

9.25ns OR

DELAY

27.75ns

Figure 53. Clock Phase with Two Input Clocks

PROGRESSIVE SCAN AT 27 MHZ (DUAL EDGE)
OR 54 MHZ

Address[0x01]: Input Mode 100 or 111, Respectively

YCrCb progressive scan data can be input at 27 MHz or
54 MHz. The input data is interleaved onto a single 8-/10-bit
bus and is input on Pins Y9 to Y0. When a 27 MHz clock is
supplied, the data is clocked in upon the rising and falling edges
of the input clock, and the clock edge bit [Address 0x01, Bit 1]
must be set accordingly.

Table 22 provides an overview of all possible input configurations.
Figure 54, Figure 55, and Figure 56 show the possible conditions:
Cb data on the rising edge, and Y data on the rising edge.

3FF

Cr0

CLKIN_B

CLOCK EDGE ADDRESS 0x00 BIT 1 SHOULD BE SET TO 0 IN THIS CASE.

Y9Y0

Cb0

05067-030

Figure 54. Input Sequence in PS Bit Interleaved Mode (EAV/SAV)

3FF

Cb0

Cr0

CLKIN_B

Y9Y0

CLOCK EDGE ADDRESS 0x00 BIT 1 SHOULD BE SET TO 1 IN THIS CASE.

05067-031

Figure 55. Input Sequence in PS Bit Interleaved Mode (EAV/SAV)

PIXEL INPUT

DATA

3FF

Cb0

Cr0

CLKIN_B

WITH A 54MHz CLOCK, THE DATA IS LATCHED ON EVERY RISING EDGE.

05067-032

Figure 56. Input Sequence in PS Bit Interleaved Mode (EAV/SAV)

MPEG2

DECODER

CLKIN_A

Y[9:0]

INTERLACED

PROGRESSIVE

YCrCb

27MHz OR 54MHz

YCrCb

ADV7320/

ADV7321

P_VSYNC,

P_HSYNC,
P_BLANK

05067-033

Figure 57. 10-Bit PS at 27 MHz or 54 MHz

ADV7320/ADV7321

Rev. 0 | Page 40 of 88

Table 22. Input Configurations

Input Format

Total Bits

Input Video

Input Pins

Subaddress

Register Setting

0x01 0x00

4:2:2

YCrCb

S9 to S2 (MSB = S9)

0x48 0x00
0x01 0x00

4:2:2

YCrCb

S9 to S0 (MSB = S9)

0x48 0x10

S9 to S2 (MSB = S9)

0x01

0x00

4:2:2

CrCb

Y9 to Y2 (MSB = Y9)

0x48

0x08

S9 to S0 (MSB = S9)

0x01

0x00

4:2:2

CrCb

Y9 to Y0 (MSB = Y9)

0x48

0x18

0x01 0x80

4:2:2

YCrCb

Y9 to Y2 (MSB = Y9)

0x48 0x00
0x01 0x80

ITU-R BT.656 (See Table 21)

4:2:2

YCrCb

Y9 to Y0 (MSB = Y9)

0x48 0x10
0x01 0x10

8 (27 MHz clock)

4:2:2

YCrCb

Y9 to Y2 (MSB = Y9)

0x13 0x40
0x01 0x10

10 (27 MHz clock)

4:2:2

YCrCb

Y9 to Y0 (MSB = Y9)

0x13 0x44
0x01 0x70

8 (54 MHz clock)

4:2:2

YCrCb

Y9 to Y2 (MSB = Y9)

0x13 0x40
0x01 0x70

10 (54 MHz clock)

4:2:2

YCrCb

Y9 to Y0 (MSB = Y9)

0x13 0x44

Y9 to Y2 (MSB = Y9)

0x01

0x10

4:2:2

CrCb

C9 to C2 (MSB = C9)

0x13

0x40

Y9 to Y0 (MSB = Y9)

0x01

0x10

4:2:2

CrCb

C9 to C0 (MSB = C9)

0x13

0x44

Y9 to Y2 (MSB = Y9)

0x01

0x10

C9 to C2 (MSB = C9)

4:4:4

S9 to S2 (MSB = S9)

0x13 0x00

Y9 to Y0 (MSB = Y9)

0x01

0x10

C9 to C0 (MSB = C9)

PS Only

4:4:4

S9 to S0 (MSB = S9)

0x13 0x04

Y9 to Y2 (MSB = Y9)

0x01

0x20

4:2:2

CrCb

C9 to Y2 (MSB = C9)

0x13

0x40

Y9 to Y0 (MSB = Y9)

0x01

0x20

4:2:2

CrCb

C9 to C0 (MSB = C9)

0x13

0x44

Y9 to Y2 (MSB = Y9)

0x01

0x20

C9 to C2 (MSB = C9)

4:4:4

S9 to S2 (MSB = S9)

0x13 0x00

Y9 to Y0 (MSB = Y9)

0x01

0x20

C9 to C0 (MSB = C9)

HDTV Only

4:4:4

S9 to S0 (MSB = S9)

0x13 0x04

Y9 to Y2 (MSB = Y9)

0x01

0x10 or 0x20

C9 to C2 (MSB = C9)

0x13

0x00

4:4:4

S9 to S2 (MSB = S9)

0x15

0x02

Y9 to Y0 (MSB = Y9)

0x01

0x10 or 0x20

C9 to C0 (MSB = C9)

0x13

0x04

HD RGB

4:4:4

S9 to S0 (MSB = S9)

0x15

0x02

8 (SD)

4:2:2

YCrCb

S9 to S2 (MSB = S9)

0x01

0x40

0x13 0x40

ITU-R BT.656 and PS

8 (PS)

4:2:2

YCrCb

Y9 to Y2 (MSB = Y9)

0x48 0x00

10 (SD)

4:2:2

YCrCb

S9 to S0 (MSB = S9)

0x01

0x40

0x13 0x44

ITU-R BT.656 and PS

10 (PS)

4:2:2

YCrCb

Y9 to Y0 (MSB = Y9)

0x48 0x10

4:2:2

YCrCb

S9 to S2 (MSB = S9)

0x01

0x30, 0x50, or 0x60

Y9 to Y2 (MSB = Y9)

0x13

0x40

ITU-R BT.656 and PS or HDTV

4:2:2

CrCb

C9 to C2 (MSB = C9)

0x48

0x00

4:2:2

YCrCb

S9 to S0 (MSB = S9)

0x01

0x30, 0x50, or 0x60

Y9 to Y0 (MSB = Y9)

0x13

0x44

ITU-R BT.656 and PS or HDTV

4:2:2

CrCb

C9 to C0 (MSB = C9)

0x48

0x10

ADV7320/ADV7321

Rev. 0 | Page 41 of 88

FEATURES

OUTPUT CONFIGURATION

Table 23, Table 24, and Table 25 demonstrate what output signals are assigned to the DACs when the control bits are set accordingly.

Table 23. Output Configuration in SD Only Mode

RGB/YUV Output
0x02, Bit 5

SD DAC Output 1
0x42, Bit 2

SD DAC Output 2
0x42, Bit 1

DAC A

DAC B

DAC C

DAC D

DAC E

DAC F

CVBS

Luma

Chroma

CVBS

Luma

Chroma

Luma

Chroma

CVBS

Luma

Chroma

CVBS

Luma

Chroma

CVBS

Luma

Chroma

Luma

Chroma

CVBS

Luma

Chroma

Luma/Chroma Swap 0x44, Bit 7

0 Table as above
1 Table as above, but with all luma/chroma instances swapped

Table 24. Output Configuration in HD/PS Only Mode

HD/PS Input
Format

HD/PS RGB Input
0x15, Bit 1

RGB/YPrPb Output
0x02, Bit 5

HD/PS Color Swap
0x15, Bit 3

DAC A

DAC B

DAC C

DAC D

DAC E

DAC F

YCrCb 4:2:2

N/A

YCrCb 4:2:2

N/A

YCrCb 4:2:2

N/A

YCrCb 4:2:2

N/A

YCrCb 4:4:4

N/A

YCrCb 4:4:4

N/A

YCrCb 4:4:4

N/A

YCrCb 4:4:4

N/A

RGB 4:4:4

N/A

RGB 4:4:4

N/A

RGB 4:4:4

N/A

RGB 4:4:4

N/A

Table 25. Output Configuration in Simultaneous SD and HD/PS Only Mode

Input Formats

RGB/YPrPb Output
0x02, Bit 5

HD/PS Color Swap
0x15, Bit 3

DAC A

DAC B

DAC C

DAC D

DAC E

DAC F

ITU-R.BT656 and HD
YCrCb in 4:2:2

CVBS

Luma

Chroma

ITU-R.BT656 and HD
YCrCb in 4:2:2

CVBS

Luma

Chroma

ITU-R.BT656 and HD
YCrCb in 4:2:2

CVBS

Luma

Chroma

ITU-R.BT656 and HD
YCrCb in 4:2:2

CVBS

Luma

Chroma

ADV7320/ADV7321

Rev. 0 | Page 42 of 88

HD ASYNC TIMING MODE

[Subaddress 0x10, Bits 3 and 2]

For any input data that does not conform to the standards
selectable in input mode, Subaddress 0x10, asynchronous
timing mode can be used to interface to the ADV7320/ADV7321.
Timing control signals for HSYNC, VSYNC, and BLANK must
be programmed by the user. Macrovision and programmable
oversampling rates are not available in async timing mode.

In async mode, the PLL must be turned off [Subaddress 0x00,
Bit 1 = 1]. Register 0x10 should be programmed to 0x01.

Figure 58 and Figure 59 show examples of how to program the
ADV7320/ADV7321 to accept a high definition standard other
than SMPTE 293M, SMPTE 274M, SMPTE 296M, or ITU-R
BT.1358.

Table 26 must be followed when programming the control signals
in async timing mode. For standards that do not require a trisync
level, P_BLANK must be tied low at all times.

Table 26. Async Timing Mode Truth Table

P_HSYNC P_VSYNC P_BLANK

Reference

Reference in Figure 58 and Figure 59

0 or 1

50% point of falling edge of trilevel horizontal sync signal

0 or 1

25% point of rising edge of trilevel horizontal sync signal

0 or 1

50% point of falling edge of trilevel horizontal sync signal

0 or 1

50% start of active video

0 or 1

50% end of active video

When async timing mode is enabled, P_BLANK, Pin 25, becomes an active high input. P_BLANK is set to active low at Address 0x10, Bit 6.

CLK

ACTIVE VIDEO

PROGRAMMABLE

INPUT TIMING

ANALOG

OUTPUT

243

1920

HORIZONTAL SYNC

SET ADDRESS 0x14,

BIT 3 = 1

05067-034

P_HSYNC

P_VSYNC

P_BLANK

Figure 58. Async Timing Mode--Programming Input Control Signals for SMPTE 295M Compatibility

ACTIVE VIDEO

HORIZONTAL SYNC

CLK

SET ADDRESS 0x14

BIT 3 = 1

ANALOG OUTPUT

05067-035

P_VSYNC

P_BLANK

P_HSYNC

Figure 59. Async Timing Mode--Programming Input Control Signals for Bilevel Sync Signal

ADV7320/ADV7321

Rev. 0 | Page 43 of 88

HD TIMING RESET

A timing reset is achieved by toggling the HD timing reset control
bit [Subaddress 0x14, Bit 0] from 0 to 1. In this state, the horizontal
and vertical counters remain reset. When this bit is set back to 0,
the internal counters resume counting.

The minimum time the pin must be held high is one clock
cycle; otherwise, this reset signal might not be recognized. This
timing reset applies to the HD timing counters only.

SD REAL-TIME CONTROL, SUBCARRIER RESET,
AND TIMING RESET

[Subaddress 0x44, Bits 2 and 1]

Together with the RTC_SCR_TR pin and SD Mode Register 3
[Address 0x44, Bits 1 and 2], the ADV7320/ADV7321 can be
used in (a) timing reset mode, (b) subcarrier phase reset mode,
or (c) RTC mode.

a. A timing reset is achieved in a low-to-high transition

on the RTC_SCR_TR pin (Pin 31). In this state, the
horizontal and vertical counters remain reset. Upon
releasing this pin (set to low), the internal counters
resume counting, starting with Field 1, and the
subcarrier phase is reset.

The minimum time the pin must be held high is one
clock cycle; otherwise, this reset signal might not be
recognized. This timing reset applies to the SD timing
counters only.

b. In subcarrier phase reset, a low-to-high transition on

the RTC_SCR_TR pin (Pin 31) resets the subcarrier
phase to zero on the field following the subcarrier
phase reset when the SD RTC/TR/SCR control bits at
Address 0x44 are set to 01.

This reset signal must be held high for a minimum of
one clock cycle.

Because the field counter is not reset, it is
recommended that the reset signal is applied in Field 7
(PAL) or Field 3 (NTSC). The reset of the phase will
then occur on the next field, i.e., Field 1, lined up
correctly with the internal counters. The field count
register at Address 0x7B can be used to identify the
number of the active field.

c. In RTC mode, the ADV7320/ADV7321 can be used to

lock to an external video source. The real-time control
mode allows the ADV7320/ADV7321 to automatically
alter the subcarrier frequency to compensate for line
length variations. When the part is connected to a
device, such as an ADV7183A video decoder (see
Figure 62), that outputs a digital data stream in the
RTC format, the part will automatically change to the
compensated subcarrier frequency on a line-by-line
basis. This digital data stream is 67 bits wide and the
subcarrier is contained in Bits 0 to 21. Each bit is two
clock cycles long. Write 0x00 into all four subcarrier
frequency registers when this mode is used.

DISPLAY

NO TIMING RESET APPLIED

TIMING RESET APPLIED

START OF FIELD 4 OR 8

PHASE = FIELD 4 OR 8

PHASE = FIELD 1

TIMING RESET PULSE

307

310

307

313

320

DISPLAY

START OF FIELD 1

05067-036

Figure 60. Timing Reset Timing Diagram

ADV7320/ADV7321

Rev. 0 | Page 44 of 88

NO F

RESET APPLIED

PHASE = FIELD 4 OR 8

307

310

313

320

DISPLAY

START OF FIELD 4 OR 8

RESET APPLIED

RESET PULSE

PHASE = FIELD 1

307

310

313

320

DISPLAY

START OF FIELD 4 OR 8

05067-037

Figure 61. Subcarrier Reset Timing Diagram

LCC1

GLL

P19P10

ADV7183A

VIDEO

DECODER

COMPOSITE

VIDEO

CLKIN_A

RTC_SCR_TR

DAC A

DAC B

DAC C

DAC D

DAC E

DAC F

Y9Y0/S9S0

RTC

LOW

H/L TRANSITION

COUNT START

128

TIME SLOT 01

14 BITS

SUBCARRIER

PHASE

PLL INCREMENT

VALID

SAMPLE

INVALID

SAMPLE

6768

4 BITS

RESERVED

SEQUENCE

BIT

RESET

BIT

RESERVED

ADV7320/

ADV7321

NOTES

i.e., VCR OR CABLE

PLL INCREMENT IS 22 BITS LONG. VALUE LOADED INTO ADV7320/ADV7321 F

DDS REGISTER IS F

PLL INCREMENTS BITS 21:0

PLUS BITS 0:9 OF SUBCARRIER FREQUENCY REGISTERS. ALL ZEROS SHOULD BE WRITTEN TO THE SUBCARRIER FREQUENCY REGISTERS
OF THE ADV7320/ADV7321.

SEQUENCE BIT

PAL: 0 = LINE NORMAL, 1 = LINE INVERTED
NTSC: 0 = NO CHANGE

RESET ADV7320/ADV7321 DDS

SELECTED BY REGISTER ADDRESS 0x01 BIT 7

05067-038

8/LINE

LOCKED

CLOCK

5 BITS

RESERVED

Figure 62. RTC Timing and Connections

ADV7320/ADV7321

Rev. 0 | Page 45 of 88

RESET SEQUENCE

A reset is activated with a high-to-low transition on the RESET
pin (Pin 33) according to the timing specifications, and the
ADV7320/ADV7321 reverts to the default output
configuration. Figure 63 illustrates the RESET timing sequence.

SD VCR FF/RW SYNC

[Subaddress 0x42, Bit 5]

In DVD record applications where the encoder is used with a
decoder, the VCR FF/RW sync control bit can be used for
nonstandard input video, i.e., in fast forward or rewind modes.

In fast forward mode, the sync information at the start of a new
field in the incoming video usually occurs before the correct
number of lines/fields are reached; in rewind mode, this sync

signal usually occurs after the total number of lines/fields are
reached. Conventionally this means that the output video will
have corrupted field signals, because one signal is generated by
the incoming video and another is generated when the internal
lines/field counters reach the end of a field.

When the VCR FF/RW sync control is enabled [Subaddress 0x42,
Bit 5], the lines/fields counters are updated according to the
incoming VSYNC signal, and the analog output matches the
incoming VSYNC signal.

This control is available in all slave timing modes except Slave
Mode 0.

XXXXXX

OFF

DIGITAL TIMING SIGNALS SUPPRESSED

VALID VIDEO

TIMING ACTIVE

RESET

DIGITAL TIMING

DACs

A, B, C

PIXEL DATA

VALID

05067-039

Figure 63. RESET Timing Sequence

ADV7320/ADV7321

Rev. 0 | Page 46 of 88

VERTICAL BLANKING INTERVAL

The ADV7320/ADV7321 accepts input data that contains VBI
data (such as CGMS, WSS, VITS) in SD and HD modes.

For the SMPTE 293M (525p) standard, VBI data can be
inserted on Lines 13 to 42 of each frame, or on Lines 6 to 43 for
the ITU-R BT.1358 (625p) standard.

This data can be present on Lines 10 to 20 for SD NTSC and on
Lines 7 to 22 for PAL.

If VBI is disabled [Address 0x11, Bit 4 for HD; Address 0x43,
Bit 4 for SD], VBI data is not present at the output and the
entire VBI is blanked. These control bits are valid in all master
and slave modes.

In Slave Mode 0, if VBI is enabled, the blanking bit in the
EAV/SAV code is overwritten. It is possible to use VBI in this
timing mode as well.

In Slave Mode 1 or 2, the BLANK control bit must be enabled
[Address 0x4A, Bit 3] to allow VBI data to pass through the
ADV7320/ADV7321. Otherwise, the ADV7320/ADV7321
automatically blanks the VBI to standard.

If CGMS is enabled and VBI is disabled, the CGMS data will
nevertheless be available at the output.

See Appendix 1--Copy Generation Management System.

SUBCARRIER FREQUENCY REGISTERS

[Subaddresses 0x4C to 0x4F]

Four 8-bit registers are used to set up the subcarrier frequency.
The value of these registers is calculated using the equation

line

video

one

cycles

clk

MHz

Number

line

video

one

periods

subcarrier

Number

Frequency

Subcarrier

where the sum is rounded to the nearest integer.

For example, in NTSC mode

569408543

1716

227

Value

Subcarrier

where:
Subcarrier Register Value

= 0x21F07C1F

SD F

See the MPU Port Description section for more details on
accessing the subcarrier frequency registers.

Programming the F

The subcarrier register value is divided into 4 F

registers as

shown above. To load the value into the encoder, users must
write to the F

registers in sequence, starting with F

0. The

value is not loaded until the F

4 write is complete.

Note that the ADV7320/ADV7321 power-up value for F

0 is

0x1E. For precise NTSC F

, write 0x1F to this register.

ADV7320/ADV7321

Rev. 0 | Page 48 of 88

FILTERS

Table 27 shows an overview of the programmable filters
available on the ADV7320/ADV7321.

Table 27. Selectable Filters

Filter

Subaddress

SD Luma LPF NTSC

0x40

SD Luma LPF PAL

0x40

SD Luma Notch NTSC

0x40

SD Luma Notch PAL

0x40

SD Luma SSAF

0x40

SD Luma CIF

0x40

SD Luma QCIF

0x40

SD Chroma 0.65 MHz

0x40

SD Chroma 1.0 MHz

0x40

SD Chroma 1.3 MHz

0x40

SD Chroma 2.0 MHz

0x40

SD Chroma 3.0 MHz

0x40

SD Chroma CIF

0x40

SD Chroma QCIF

0x40

SD UV SSAF

0x42

HD Chroma Input

0x13

HD Sinc Filter

0x13

HD Chroma SSAF

0x13

SD Internal Filter Response

[Subaddress 0x40 [7:2]; Subaddress 0x42, Bit 0]

The Y filter supports several different frequency responses,
including two low-pass responses, two notch responses, an
extended (SSAF) response with or without gain boost
attenuation, a CIF response, and a QCIF response. The UV
filter supports several different frequency responses, including
six low-pass responses, a CIF response, and a QCIF response, as
shown in Figure 35 and Figure 36.

If SD SSAF gain is enabled, there are 12 response options in the
range -4 dB to +4 dB [Subaddress 0x47, Bit 4]. Choose the
desired response by programming the correct value via the I

[Subaddress 0x62]. The variation of frequency responses are
shown in Figure 32 and Figure 33.

In addition to the chroma filters listed in Table 27, the
ADV7320/ADV7321 contains an SSAF filter specifically
designed for the color difference component outputs, U and V.
This filter has a cutoff frequency of about 2.7 MHz and a gain of

40 dB at 3.8 MHz, as shown in Figure 66. This filter can be
controlled with Address 0x42, Bit 0.

FREQUENCY (MHz)

GAIN (

10

30

50

60

20

40

05067-044

EXTENDED UV FILTER MODE

Figure 66. UV SSAF Filter

If this filter is disabled, one of the chroma filters shown in
Table 28 can be selected and used for the CVBS or luma/
chroma signal.

Table 28. Internal Filter Specifications

Filter

Pass-Band
Ripple

(dB)

3 dB Bandwidth

(MHz)

Luma LPF NTSC

0.16

4.24

Luma LPF PAL

0.1

4.81

Luma Notch NTSC

0.09

2.3/4.9/6.6

Luma Notch PAL

0.1

3.1/5.6/6.4

Luma SSAF

0.04

6.45

Luma CIF

0.127

3.02

Luma QCIF

Monotonic

1.5

Chroma 0.65 MHz

Monotonic

0.65

Chroma 1.0 MHz

Monotonic

Chroma 1.3 MHz

0.09

1.395

Chroma 2.0 MHz

0.048

2.2

Chroma 3.0 MHz

Monotonic

3.2

Chroma CIF

Monotonic

0.65

Chroma QCIF

Monotonic

0.5

Pass-band ripple is the maximum fluctuation from the 0 dB response in the

pass band, measured in dB. The pass band is defined to have 0 Hz to fc (Hz)
frequency limits for a low-pass filter, and 0 Hz to f1 (Hz) and f2 (Hz) to infinity
for a notch filter, where fc, f1, and f2 are the -3 dB points.

3 dB bandwidth refers to the -3 dB cutoff frequency.

ADV7320/ADV7321

Rev. 0 | Page 49 of 88

PS/HD Sinc Filter

[Subaddress 0x13, Bit 3]

FREQUENCY (MHz)

0.5

GAIN (

0.4

0.1

0.2

0.3

0.4

0.3

0.2

0.1

05067-042

Figure 67. HD Sinc Filter Enabled

FREQUENCY (MHz)

0.5

GAIN (

0.4

0.1

0.2

0.3

0.4

0.3

0.2

0.1

05067-043

Figure 68. HD Sinc Filter Disabled

COLOR CONTROLS AND RGB MATRIX

HD Y Level, HD Cr Level, HD Cb Level

[Subaddresses 0x16 to 0x18]

Three 8-bit registers at Addresses 0x16, 0x17, and 0x18 are used
to program the output color of the internal HD test pattern
generator, be it the lines of the cross hatch pattern or the
uniform field test pattern. They are not functional as color
controls for external pixel data input. For this purpose the RGB
matrix is used.

The values for Y and the color difference signals used to obtain
white, black, and saturated primary and complementary colors
conform to the ITU-R BT.601-4 standard.

Table 29 shows sample color values that can be programmed
into the color registers when the output standard selection is
set to EIA 770.2.

Table 29. Sample Color Values for EIA 770.2
Output Standard Selection

Sample Color

Y Value

Cr Value

Cb Value

White

235 (EB)

128 (80)

Black

16 (10)

128 (80)

Red

81 (51)

240 (F0)

90 (5A)

Green

145 (91)

34 (22)

54 (36)

Blue

41 (29)

110 (6E)

240 (F0)

Yellow

210 (D2)

146 (92)

16 (10)

Cyan

170 (AA)

16 (10)

166 (A6)

Magenta

106 (6A)

222 (DE)

202 (CA)

RGB Matrix

[Subaddresses 0x03 to 0x09]

The internal RGB matrix automatically performs all YCrCb to
RGB scaling according to the input standard programmed in
the device as selected by input mode Register 0x01 [6:4]. Table 30
shows the options available in this Matrix.

Note that it is not possible to do a color space conversion from
RGB-in to YPrPb-out. Also, it is not possible to input SD RGB.

Table 30. Matrix Conversion Options

HDTV/SD/PS

Input Output

Reg 0x02,Bit 5
(YUV/RGB OUT)

Reg 0x15, Bit 1
(RGB IN/YCrCb IN,
PS/HD Only)

YCrCb YPrPb 1

YCrCb RGB

RGB

Manual RGB Matrix Adjust Feature

Normally, there is no need to enable this feature in Register 0x02,
Bit 3, because the RGB matrix automatically performs color
space conversion depending on the input mode chosen (SD/PS,
HD) and the polarity of RGB/YPrPb output in Register 0x02,
Bit 5 (see Table 30). For this reason, the manual RGB matrix
adjust feature is disabled by default. However, For HDTV
YCrCb-to-RGB conversion, the RGB matrix must be enabled to
invoke the correct coefficients for this color space. The
coefficients do not need to be adjusted.

The manual RGB matrix adjust feature provides custom
coefficient manipulation and is used in progressive scan and
high definition modes only.

When the manual RGB matrix adjust feature is enabled, the
default values in Registers 0x05 to 0x09 are correct for HDTV
color space only. The color components are converted
according to the 1080i and 720p standards (SMPTE 274M,
SMPTE 296M):

ADV7320/ADV7321

Rev. 0 | Page 50 of 88

= Y + 1.575Pr

= Y - 0.468Pr - 0.187Pb

= Y + 1.855Pb

This is reflected in the preprogrammed values for GY = 0x13B,
GU = 0x3B, GV = 0x93, BU = 0x248, and RV = 0x1F0.

If RGB matrix is enabled and another input standard (such as
SD or PS) is used, the scale values for GY, GU, GV, BU, and RV
must be adjusted according to this input standard color space.
The user should consider that the color component conversion
might use different scale values. For example, SMPTE 293M
uses the following conversion:

= Y + 1.402Pr

= Y 0.714Pr 0.344Pb

= Y + 1.773Pb

The manual RGB matrix adjust feature can be used to control
the HD output levels in cases where the video output does not
conform to the standard due to altering the DAC output stages
such as termination resistors. The programmable RGB matrix is
used for external HD/PS data and is not functional when internal
test patterns are enabled. To adjust Registers 0x05 to 0x09, the
manual RGB matrix adjust must be enabled [Register 0x02,
Bit 3 =1].

Programming the RGB Matrix

If custom manipulation of coefficients is required, enable the
RGB matrix in Address 0x02, Bit 3, set the output to RGB
[Address 0x02, Bit 5], and disable sync on PrPb (default)
[Address 0x15, Bit 2]. Enabling sync on RGB is optional
[Address 0x02, Bit 4].

GY at Addresses 0x03 and 0x05 controls the green signal output
levels. BU at Addresses 0x04 and 0x08 control the blue signal
output levels, and RV at Addresses 0x04 and 0x09 control the red
signal output levels. To control YPrPb output levels, enable the
YUV output [Address 0x02, Bit 5]. In this case GY [Address 0x05;
Address 0x03, Bits 0 and 1] is used for the Y output, RV
[Address 0x09; Address 0x04, Bits 0 and 1] is used for the Pr
output, and BU [Address 0x08; Address 0x04, Bits 2 and 3] is
used for the Pb output.

If RGB output is selected, the RGB matrix scaler uses the
following equations:

= GY × Y + GU × Pb + GV × Pr

= GY × Y + BU × Pb

= GY × Y + RV × Pr

If YPrPb output is selected, the following equations are used:

= GY × Y

= BU × Pb

= RV × Pr

Upon power-up, the RGB matrix is programmed with the
default values in Table 31.

Table 31. RGB Matrix Default Values

Address Default

0x03 0x03
0x04 0xF0
0x05 0x4E
0x06 0x0E
0x07 0x24
0x08 0x92
0x09 0x7C

When the manual RGB matrix adjust feature is not enabled, the
ADV7320/ADV7321 automatically scales YCrCb inputs to all
standards supported by this part as selected by the input mode
Register 0x01 [6:4].

SD Luma and Color Control

[Subaddresses 0x5C, 0x5D, 0x5E, 0x5F]

SD Y Scale, SD Cr Scale, and SD Cb Scale are three 10-bit-wide
control registers that scale the Y, Cb, and Cr output levels.

Each of these registers represents the value required to scale the
Cb or Cr level from 0.0 to 2.0 and the Y level from 0.0 to 1.5 of
its initial level. The value of these 10 bits is calculated using the
following equation:

Y, Cr, or Cb Scalar Value

= Scale Factor × 512

For example,

Scale Factor

= 1.18

Y, Cb, or Cr Scale Value

= 1.18 × 512 = 665.6

Y, Cb, or Cr Scale Value

= 665 (rounded to the nearest

integer

)

Y, Cb, or Cr Scale Value

= 1010 0110 01b

Address 0x5C, SD LSB Register = 0x15
Address 0x5D, SD Y Scale Register = 0xA6
Address 0x5E, SD Cb Scale Register = 0xA6
Address 0x5F, SD Cr Scale Register = 0xA6

Note that this feature affects all interlaced output signals, i.e.,
CVBS, Y-C, YPrPb, and RGB.

ADV7320/ADV7321

Rev. 0 | Page 51 of 88

SD Hue Adjust Value

[Subaddress 0x60]

The hue adjust value is used to adjust the hue on the composite
and chroma outputs.

These eight bits represent the value required to vary the hue of
the video data, i.e., the variance in phase of the subcarrier
during active video with respect to the phase of the subcarrier
during the color burst. The ADV7320/ADV7321 provides a
range of ±22.5° increments of 0.17578125°. For normal
operation (zero adjustment), this register is set to 0x80. Values
0xFF and 0x00 represent the upper and lower limits
(respectively) of adjustment attainable.

Hue Adjust (°) = 0.17578125° (HCR

- 128) for positive hue

adjust value.

For example, to adjust the hue by +4°, write 0x97 to the hue
adjust value register:

105

128

17578125

where the sum is rounded to the nearest integer.

To adjust the hue by -4°, write 0x69 to the hue adjust value
register:

105

128

17578125

where the sum is rounded to the nearest integer.

SD Brightness Control

[Subaddress 0x61]

The brightness is controlled by adding a programmable setup
level onto the scaled Y data. This brightness level may be added
onto the scaled Y data. For NTSC with pedestal, the setup can
vary from 0 IRE to 22.5 IRE. For NTSC without pedestal and
for PAL, the setup can vary from -7.5 IRE to +15 IRE.

The brightness control register is an 8-bit register. Seven bits of
this 8-bit register are used to control the brightness level, which
can be a positive or negative value.

For example,

1. To add +20 IRE brightness level to an NTSC signal with

pedestal, write 0x28 to Address 0x61, SD brightness.

0x[SD Brightness Value] =

0x[IRE Value × 2.015631] =

0x[20 × 2.015631] = 0x[40.31262] = 0x28

2. To add 7 IRE brightness level to a PAL signal, write 0x72 to

Address 0x61, SD brightness.

[IRE Value| × 2.075631

[7 × 2.015631] = [14.109417] = 0001110b

[0001110] into twos complement = [1110010]b = 0x72

Table 32. Brightness Control Values

Setup Level In
NTSC with
Pedestal

Setup Level In
NTSC No
Pedestal

Setup
Level In
PAL

SD
Brightness

22.5 IRE

15 IRE

0x1E

15 IRE

7.5 IRE

0x0F

7.5 IRE

0 IRE

0x00

0 IRE

7.5 IRE

0x71

Values in the range of 0x3F to 0x44 might result in an invalid output
signal.

ADV7320/ADV7321

Rev. 0 | Page 52 of 88

SD Brightness Detect

[Subaddress 0x7A]

The ADV7320/ADV7321 allow monitoring the brightness level
of the incoming video data. Brightness detect is a read-only
register.

Double Buffering

[Subaddress 0x13, Bit 7; Subaddress 0x48, Bit 2]

Double buffered registers are updated once per field upon the
falling edge of the Vsync signal. Double buffering improves the
overall performance because modifications to register settings
will not be made during active video, but take effect upon the
start of the active video.

Double buffering can be activated on the following HD
registers: HD gamma A and gamma B curves and HD CGMS
registers.

Double buffering can be activated on the following SD registers:
SD gamma A and gamma B curves, SD Y scale, SD U scale, SD V
scale, SD brightness, SD closed captioning, and SD Macrovision
Bits 5 to 0.

NTSC WITHOUT PEDESTAL

NO SETUP

VALUE ADDED

POSITIVE SETUP

VALUE ADDED

100 IRE

0 IRE

NEGATIVE SETUP

VALUE ADDED

7.5 IRE

+7.5 IRE

05067-069

Figure 69. Examples of Brightness Control Values

ADV7320/ADV7321

Rev. 0 | Page 53 of 88

PROGRAMMABLE DAC GAIN CONTROL

DACs A, B, and C are controlled by REG 0A.

DACs D, E, and F are controlled by REG 0B.

The I

C control registers will adjust the output signal gain up or

down from its absolute level.

CASE B

700mV

300mV

NEGATIVE GAIN PROGRAMMED IN

DAC OUTPUT LEVEL REGISTERS,

SUBADDRESS 0x0A, 0x0B

CASE A

GAIN PROGRAMMED IN DAC OUTPUT LEVEL

REGISTERS, SUBADDRESS 0x0A, 0x0B
700mV

300mV

05067-070

Figure 70. Programmable DAC Gain--Positive and Negative Gain

In case A, the video output signal is gained. The absolute level
of the sync tip and blanking level both increase with respect to
the reference video output signal. The overall gain of the signal
is increased from the reference signal.

In case B, the video output signal is reduced. The absolute level
of the sync tip and blanking level both decrease with respect to
the reference video output signal. The overall gain of the signal
is reduced from the reference signal.

The range of this feature is specified for ±7.5% of the nominal
output from the DACs. For example, if the output current of the
DAC is 4.33 mA, the DAC tune feature can change this output
current from 4.008 mA (-7.5%) to 4.658 mA (+7.5%).

The reset value of the vid_out_ctrl registers is 0x00; therefore,
nominal DAC current is output. The following table is an
example of how the output current of the DACs varies for a
nominal 4.33 mA output current.

Table 33. DAC Gain Control

Reg 0x0A or
0x0B

DAC
Current
(mA)

% Gain

Note

0100 0000 (0x40)

4.658

7.5000%

0011 1111 (0x3F)

4.653

7.3820%

0011 1110 (0x3E)

4.648

7.3640%

...

0000 0010 (0x02)

4.43

0.0360%

0000 0001 (0x01)

4.38

0.0180%

0000 0000 (0x00)

4.33

0.0000%

C Reset Value,

Nominal)

1111 1111 (0xFF)

4.25

-0.0180%

1111 1110 (0xFE)

4.23

-0.0360%

...

1100 0010 (0xC2)

4.018

-7.3640%

1100 0001 (0xC1)

4.013

-7.3820%

1100 0000 (0xC0)

4.008

-7.5000%

GAMMA CORRECTION

[Subaddresses 0x24 to 0x37 for HD,
Subaddresses 0x66 to 0x79 for SD]

Gamma correction is available for SD and HD video. For each
standard, there are twenty 8-bit-wide registers. They are used to
program the Gamma Correction Curves A and B. HD Gamma
Curve A is programmed at Addresses 0x24 to 0x2D, and HD
Gamma Curve B is programmed at 0x2E to 0x7. SD Gamma
Curve A is programmed at Addresses 0x66 to 0x6F, and SD
Gamma Curve B is programmed at Addresses 0x70 to 0x79.

Generally gamma correction is applied to compensate for the
nonlinear relationship between signal input and brightness level
output (as perceived on the CRT). It can also be applied
wherever nonlinear processing is used.

Gamma correction uses the function

(

)

OUT

Signal

where = gamma power factor.

Gamma correction is performed on the luma data only. The
user may choose either of two curves, Curve A or Curve B. At
any one time, only one of these curves can be used.

The response of the curve is programmed at 10 predefined
locations. In changing the values at these locations, the gamma
curve can be modified. Between these points, linear interpolation
is used to generate intermediate values. Considering the curve
to have a total length of 256 points, the 10 locations are at 24,
32, 48, 64, 80, 96, 128, 160, 192, and 224. Locations 0, 16, 240,
and 255 are fixed and cannot be changed.

ADV7320/ADV7321

Rev. 0 | Page 54 of 88

For the length of 16 to 240, the gamma correction curve has to
be calculated as follows:

= x

where:
y

= gamma corrected output

= linear input signal

= gamma power factor

To program the gamma correction registers, calculate the seven
values for y using the following formula:

)

240

(

)

240

(

)

(

where:
x

(n - 16)

= Value for x along x axis at points

n = 24, 32, 48, 64, 80, 96, 128, 160, 192, or 224
y

= value for y along the y axis, which must be written into the

gamma correction register

For example,

= [(8/224)0.5 × 224] + 16 = 58

= [(16/224)0.5 × 224] + 16 = 76

= [(32/224)0.5 × 224] + 16 = 101

= [(48/224)0.5 × 224] + 16 = 120

= [(64/224)0.5 × 224] + 16 = 136

= [(80/224)0.5 × 224] + 16 = 150

128

= [(112/224)0.5 × 224] + 16 = 174

160

= [(144/224)0.5 × 224] + 16 = 195

192

= [(176/224)0.5 × 224] + 16 = 214

224

= [(208/224)0.5 × 224] + 16 = 232

where the sum of each equation is rounded to the nearest
integer.

The gamma curves in Figure 71 and Figure 72 are examples only;
any user-defined curve is acceptable in the range of 16 to 240.

LOCATION

100

150

200

250

300

100

150

200

250

0.5

SIGNAL INPUT

GAMMA CORRE

CTE

AMP

LITUDE

SIGNAL OUTPUT

GAMMA CORRECTION BLOCK OUTPUT TO A RAMP INPUT

05067-071

Figure 71. Signal Input (Ramp) and Signal Output for Gamma 0.5

LOCATION

100

150

200

250

300

100

150

200

250

GAMMA CORRE

CTE

AMP

LITUDE

GAMMA CORRECTION BLOCK TO A RAMP INPUT FOR

VARIOUS GAMMA VALUES

0.3

0.5

1.5

1.8

SIG

L I

05067-072

Figure 72. Signal Input (Ramp) and Selectable Output Curves

ADV7320/ADV7321

Rev. 0 | Page 55 of 88

HD SHARPNESS FILTER AND ADAPTIVE FILTER
CONTROLS

[Subaddresses 0x20, 0x38 to 0x3D]

There are three filter modes available on the ADV7320/
ADV7321: sharpness filter mode and two adaptive filter modes.

HD Sharpness Filter Mode

To enhance or attenuate the Y signal in the frequency ranges
shown in Figure 73, the HD sharpness filter must be enabled
and the HD adaptive filter enable must be disabled.

To select one of the 256 individual responses, the corresponding
gain values, which range from 8 to +7, for each filter must be
programmed into the HD sharpness filter gain register at
Address 0x20.

HD Adaptive Filter Mode

The HD adaptive filter threshold A, B, and C registers, the HD
adaptive filter gain 1, 2, and 3 registers, and the HD sharpness
gain register are used in adaptive filter mode. To activate the
adaptive filter control, the HD sharpness filter and the HD
adaptive filter must be enabled.

The derivative of the incoming signal is compared to the three
programmable threshold values: HD Adaptive Filter Threshold
A, B, and C. The recommended threshold range is from 16 to
235, although any value in the range of 0 to 255 can be used.

The edges can then be attenuated with the settings in HD
adaptive filter gain 1, 2, and 3 registers, and HD sharpness filter
gain register.

According to the settings of the HD adaptive filter mode
control, there are two adaptive filter modes available:

1. Mode A is used when adaptive filter mode is set to 0.

In this case, Filter B (LPF) will be used in the adaptive
filter block. Also, only the programmed values for
Gain B in the HD sharpness filter gain and HD
Adaptive Filter Gain 1, 2, and 3 are applied when
needed. The Gain A values are fixed and cannot be
changed.

2. Mode B is used when adaptive filter mode is set to 1.

In this mode, a cascade of Filter A and Filter B is used.
Both settings for Gain A and Gain B in the HD
sharpness filter gain and HD Adaptive Filter Gain 1, 2,
and 3 become active when needed.

FREQUENCY (MHz)

FILTER A RESPONSE (Gain Ka)

MAG

UDE

0.5

0.6

0.7

0.8

0.9

1.0

1.1

1.2

1.3

1.4

1.5

FREQUENCY (MHz)

FILTER B RESPONSE (Gain Kb)

MAG

UDE

0.5

0.6

0.7

0.8

0.9

1.0

1.1

1.2

1.3

1.4

1.5

FREQUENCY (MHz)

ITU

E R

ESPON

SE (

inear Scale)

1.0

1.1

1.2

1.3

1.4

1.5

1.6

INPUT

SIGNAL:

STEP

FREQUENCY RESPONSE IN SHARPNESS

FILTER MODE WITH Ka = 3 AND Kb = 7

SHARPNESS AND ADAPTIVE FILTER CONTROL BLOCK

05067-073

Figure 73. Sharpness and Adaptive Filter Control Block

ADV7320/ADV7321

Rev. 0 | Page 57 of 88

Adaptive Filter Control Application

Figure 75 and Figure 76 show typical signals to be processed by
the adaptive filter control block.

05067-075

Figure 75. Input Signal to Adaptive Filter Control

05067-076

Figure 76. Output Signal after Adaptive Filter Control

The register settings in Table 35 were used to obtain the results
shown in Figure 76, i.e., to remove the ringing on the Y signal.
Input data was generated by an external signal source.

Table 35. Register Settings for Figure 76

Address

Register Setting

0x00 0xFC
0x01 0x38
0x02 0x20
0x10 0x00
0x11 0x81
0x15 0x80
0x20 0x00
0x38 0xAC
0x39 0x9A
0x3A 0x88
0x3B 0x28
0x3C 0x3F
0x3D 0x64

When changing the adaptive filter mode to Mode B
[Address 0x15, Bit 6], the output shown in Figure 77 can be
obtained.

05067-077

Figure 77. Output Signal from Adaptive Filter Control

SD DIGITAL NOISE REDUCTION

[Subaddresses 0x63, 0x64, 0x65]

DNR is applied to the Y data only. A filter block selects the high
frequency, low amplitude components of the incoming signal
(DNR input select). The absolute value of the filter output is
compared to a programmable threshold value (DNR threshold
control). There are two DNR modes available: DNR mode and
DNR sharpness mode.

In DNR mode, if the absolute value of the filter output is
smaller than the threshold, it is assumed to be noise. A
programmable amount (coring gain border, coring gain data) of
this noise signal will be subtracted from the original signal. In
DNR sharpness mode, if the absolute value of the filter output is
less than the programmed threshold, it is assumed to be noise,
as before. Otherwise, if the level exceeds the threshold, now
being identified as a valid signal, a fraction of the signal (coring
gain border, coring gain data) will be added to the original
signal to boost high frequency components and sharpen the
video image.

In MPEG systems, it is common to process the video
information in blocks of 8 pixels × 8 pixels for MPEG2 systems,
or 16 pixels × 16 pixels for MPEG1 systems (block size control).
DNR can be applied to the resulting block transition areas that
are known to contain noise. Generally, the block transition area
contains two pixels. It is possible to define this area to contain
four pixels (border area).

It is also possible to compensate for variable block positioning
or differences in YCrCb pixel timing with the use of the DNR
block offset.

The digital noise reduction registers are three 8-bit registers.
They are used to control the DNR processing.

ADV7320/ADV7321

Rev. 0 | Page 58 of 88

BLOCK SIZE CONTROL

BORDER AREA

BLOCK OFFSET

CORING GAIN DATA

CORING GAIN BORDER

GAIN

DNR CONTROL

FILTER

OUTPUT

THRESHOLD?

INPUT FILTER

BLOCK

FILTER OUTPUT

THRESHOLD

DNR OUT

MAIN SIGNAL PATH

ADD SIGNAL

ABOVE

THRESHOLD

RANGE FROM

ORIGINAL SIGNAL

DNR

SHARPNESS

MODE

NOISE

SIGNAL PATH

Y DATA

INPUT

BLOCK SIZE CONTROL

BORDER AREA

BLOCK OFFSET

CORING GAIN DATA

CORING GAIN BORDER

GAIN

DNR CONTROL

FILTER

OUTPUT

THRESHOLD?

INPUT FILTER

BLOCK

FILTER OUTPUT

THRESHOLD

DNR OUT

MAIN SIGNAL PATH

SUBTRACT SIGNAL

IN THRESHOLD

RANGE FROM

ORIGINAL SIGNAL

DNR MODE

NOISE

SIGNAL PATH

Y DATA

INPUT

05067-078

Figure 78. DNR Block Diagram

CORING GAIN BORDER

[Address 0x63, Bits 3 to 0]

These four bits are assigned to the gain factor applied to border
areas. In DNR mode, the range of gain values is 0 to 1 in
increments of 1/8. This factor is applied to the DNR filter
output, which lies below the set threshold range. The result is
then subtracted from the original signal.

In DNR sharpness mode, the range of gain values is 0 to 0.5 in
increments of 1/16. This factor is applied to the DNR filter
output, which lies above the threshold range. The result is
added to the original signal.

CORING GAIN DATA

[Address 0x63, Bits 7 to 4]

These four bits are assigned to the gain factor applied to the luma
data inside the MPEG pixel block. In DNR mode, the range of
gain values is 0 to 1 in increments of 1/8. This factor is applied
to the DNR filter output, which lies below the set threshold
range. The result is then subtracted from the original signal.

O X X X X X X O O X X X X X X O

DNR27 DNR24 = 0x01

OFFSET CAUSED

BY VARIATIONS IN

INPUT TIMING

APPLY BORDER

CORING GAIN

APPLY DATA

CORING GAIN

05067-079

Figure 79. DNR Offset Control

DNR THRESHOLD

[Address 0x64, Bits 5 to 0]

These six bits are used to define the threshold value in the range
of 0 to 63. The range is an absolute value.

BORDER AREA

[Address 0x64, Bit 6]

When this bit is set to Logic 1, the block transition area can be
defined to consist of four pixels. If this bit is set to Logic 0, the
border transition area consists of two pixels, where one pixel
refers to two clock cycles at 27 MHz.

720

485 PIXELS

(NTSC)

8 PIXEL BLOCK

2-PIXEL

BORDER DATA

8 PIXEL BLOCK

05067-080

Figure 80. DNR Border Area

BLOCK SIZE CONTROL

[Address 0x64, Bit 7]

This bit is used to select the size of the data blocks to be
processed. Setting the block size control function to Logic 1
defines a 16 pixel × 16 pixel data block, and Logic 0 defines an
8 pixel × 8 pixel data block, where one pixel refers to two clock
cycles at 27 MHz.

DNR INPUT SELECT CONTROL

[Address 0x65, Bits 2 to 0]

Three bits are assigned to select the filter, which is applied to the
incoming Y data. The signal that lies in the pass band of the
selected filter is the signal that will be DNR processed. Figure 81
shows the filter responses selectable with this control.

ADV7320/ADV7321

Rev. 0 | Page 59 of 88

FILTER C

FILTER B

FILTER A

FILTER D

FREQUENCY (Hz)

0.2

0.4

0.6

MAGNITUDE

0.8

1.0

05067-081

Figure 81. DNR Input Select

DNR MODE CONTROL

[Address 0x65, Bit 4]

This bit controls the DNR mode selected. Logic 0 selects DNR
mode; Logic 1 selects DNR sharpness mode.

DNR works on the principle of defining low amplitude, high
frequency signals as probable noise and subtracting this noise
from the original signal.

In DNR mode, it is possible to subtract a fraction of the signal
that lies below the set threshold, assumed to be noise, from the
original signal. The threshold is set in DNR Register 1.

When DNR sharpness mode is enabled, it is possible to add a
fraction of the signal that lies above the set threshold to the

original signal, since this data is assumed to be valid data and
not noise. The overall effect is that the signal will be boosted
(similar to using Extended SSAF filter).

BLOCK OFFSET CONTROL

[Address 0x65, Bits 7 to 4]

Four bits are assigned to this control, which allows a shift of the
data block of 15 pixels maximum. Consider the coring gain
positions fixed. The block offset shifts the data in steps of one
pixel such that the border coring gain factors can be applied at the
same position regardless of variations in input timing of the data.

SD ACTIVE VIDEO EDGE

[Subaddress 0x42, Bit 7]

When the active video edge feature is enabled, the first three
pixels and the last three pixels of the active video on the luma
channel are scaled so that maximum transitions on these pixels
are not possible. The scaling factors are ×1/8, ×1/2, and ×7/8.
All other active video passes through unprocessed.

SAV/EAV STEP EDGE CONTROL

The ADV7320/ADV7321 have the capability of controlling fast
rising and falling signals at the start and end of active video to
minimize ringing.

An algorithm monitors SAV and EAV and determines when the
edges are rising or falling too fast. The result is reduced ringing
at the start and end of active video for fast transitions.
Subaddress 0x42, Bit 7 = 1, enables this feature.

100 IRE

0 IRE

100 IRE

12.5 IRE

87.5 IRE

0 IRE

50 IRE

LUMA CHANNEL WITH

ACTIVE VIDEO EDGE

DISABLED

LUMA CHANNEL WITH

ACTIVE VIDEO EDGE

ENABLED

05067-082

Figure 82. Example of Active Video Edge Functionality

ADV7320/ADV7321

Rev. 0 | Page 61 of 88

HSYNC/VSYNC OUTPUT CONTROL

The ADV7320/21 has the ability to accept either embedded time codes in the input data, or external Hsync and Vsync signals on
P_HSYNC/P_VSYNC, outputting the respective signals on the P_HSYNC and P_VSYNC pins.

Table 36. Hsync Output Control

HD/ED

Slave Mode
(0x10, bit 2)

HD/ED
Sync Out Enable
(0x02, Bit 7)

SD
Sync Out Enable
(0x02, Bit 6)

I2C_HSYNC _gen_sel
(0x14, Bit 1)

Signal on S_HSYNC Pin

Duration

x 0

0 x

Tristate

x 0

1 x

Pipelined

HSYNC

See Appendix
5--SD Timing
Modes

External HSYNC
& VSYNC/Field
Mode

Pipelined Ext HD/ED HSYNC

As per HSYNC
timing

EAV/SAV Mode

Pipelined HD/ED HSYNC
based on AV code H bit

Same as line
blanking interval

x 1

Pipelined HD/ED HSYNC
based on horizontal counter

Same as
embedded
HSYNC

______________________________

In all HD/ED standards where there is an HSYNC o/p, the start of the HSYNC pulse is aligned with the falling edge of the embedded HSYNC in the output video.

ED = enhanced definition.

Table 37. VSYNC Output Control

HD/ED

Slave Mode
(0x10, Bit 2)

HD/ED
Sync out Enable
(0x02, Bit 7)

SD
Sync Out Enable
(0x02, Bit 6)

I2C_VSYNC _gen_sel
(0x14, Bit 2)

Video
Standard

Signal on
S_VSYNC Pin

Duration

x 0 0

x Tristate

x 0 1

Interlaced

Pipelined SD
VSYNC/ field

See Appendix
5--SD Timing
Modes

External HSYNC
& VSYNC/Field
Mode

1 x 0

Pipelined EXT
HD/ED VSYNC or
field signal

As per Ext VSYNC
or field signal

EAV/SAV Mode

All HD interlace
standards

External pipelined
field signal based
on AV code F bit

Field

EAV/SAV Mode

All HD/ED
progressive
standards

Pipelined VSYNC
based on AV code
V bit

Vertical blanking
interval

x 1 x

All HD/ED stan-
dards except
525p

External pipelined
HD/ED VSYNC
based on vertical
counter

Aligned with
serration lines

x 1 x

525p

External pipelined
HD/ED VSYNC
based on vertical
counter

Vertical blanking
interval

In all HD/ED standards where there is an HSYNC o/p, the start of the HSYNC pulse is aligned with the falling edge of the embedded HSYNC in the output video.

ED = enhanced definition.

ADV7320/ADV7321

Rev. 0 | Page 62 of 88

BOARD DESIGN AND LAYOUT

DAC TERMINATION AND LAYOUT
CONSIDERATIONS

The ADV7320/ADV7321 contain an on-board voltage
reference. The ADV7320/ADV7321 can be used with an
external V

REF

(AD1580).

The R

SET

resistors are connected between the R

SET

pins and

AGND and are used to control the full-scale output current
and, therefore, the DAC voltage output levels. For full-scale
output, R

SET

must have a value of 3040 . The R

SET

values should

not be changed. R

LOAD

has a value of 300 for full-scale output.

VIDEO OUTPUT BUFFER AND OPTIONAL
OUTPUT FILTER

Output buffering on all six DACs is necessary to drive output
devices, such as SD or HD monitors. Analog Devices produces
a range of suitable op amps for this application, e.g., the
AD8061. More information on line driver buffering circuits is
given in the relevant op amps' data sheets.

An optional analog reconstruction low-pass filter (LPF) may be
required as an anti-imaging filter if the ADV7320/ADV7321 are
connected to devices that require this filtering.

The filter specifications vary with the application.

Table 38. External Filter Requirements

Application Oversampling

Cutoff
Frequency
(MHz)

Attenuation
50 dB @
(MHz)

2×

>6.5

20.5

16×

>6.5

209.5

1×

>12.5

14.5

8×

>12.5

203.5

HDTV

1×

>30

44.25

HDTV

2×

>30

118.5

560

600

22pF

600

DAC

OUTPUT

BNC

OUTPUT

560

05067-085

Figure 85. Example of Output Filter for SD, 16× Oversampling

80

70

60

50

40

30

20

10

30

60

90

120

150

180

210

240

10M

100M

FREQUENCY (Hz)

CIRCUIT FREQUENCY RESPONSE

GROUP DELAY (Seconds)

PHASE (Degrees)

MAGNITUDE (dB)

21n

18n

15n

12n

24n

GAIN (

05067-086

Figure 86. Filter Plot for Output Filter for SD, 16× Oversampling

560

6.8pF

600

6.8pF

600

DAC

OUTPUT

BNC

OUTPUT

4.7

560

05067-087

Figure 87. Example of Output Filter for PS, 8× Oversampling

82pF

33pF

DAC

OUTPUT

220nH

470nH

500

BNC

OUTPUT

500

300

05067-088

Figure 88. Example of Output Filter for HDTV, 2× Oversampling

Table 39. Possible Output Rates
from the ADV7320/ADV7321

Input Mode Address
0x01, Bits 6 to 4

PLL Address
0x00, Bit 1

Output Rate
(MHz)

Off

27 (2×)

SD Only

216 (16×)

Off

27 (1×)

PS Only

216 (8×)

HDTV Only

Off On

74.25 (1×)
148.5 (2×)

ADV7320/ADV7321

Rev. 0 | Page 63 of 88

10

20

30

40

50

60

70

80

90

10M

100M

FREQUENCY (Hz)

CIRCUIT FREQUENCY RESPONSE

MAGNITUDE (dB)

GROUP DELAY (Seconds)

PHASE

(Degrees)

GAIN (

320

240

160

80

160

240

480

400

14n

12n

10n

18n

16n

05067-089

Figure 89. Filter Plot for Output Filter for PS, 8× Oversampling

10

20

30

40

50

60

480

360

240

120

240

18n

15n

12n

10M

100M

FREQUENCY (Hz)

CIRCUIT FREQUENCY RESPONSE

GROUP DELAY (Seconds)

PHASE (Degrees)

MAGNITUDE (dB)

GAIN (

05067-090

Figure 90. Filter Plot for Output Filter for HDTV, 2× Oversampling

PCB BOARD LAYOUT

The ADV7320/ADV7321 are optimally designed for lowest
noise performance of both radiated and conducted noise. To
complement the excellent noise performance of the ADV7320/
ADV7321, it is imperative that great care be given to the PC
board layout.

The layout should be optimized for lowest noise on the
ADV7320/ ADV7321 power and ground lines. This can be
achieved by shielding the digital inputs and providing good
decoupling. The lead length between groups of V

and AGND,

and DGND, and V

DD_IO

and GND_IO pins should be kept

as short as possible to minimized inductive ringing.

It is recommended that a 4-layer printed circuit board is used,
with power and ground planes separating the layer of the signal
carrying traces of the components and solder side layer. Com-
ponent placement should be carefully considered in order to
separate noisy circuits, such as crystal clocks, high speed logic
circuitry, and analog circuitry.

There should be a separate analog ground plane and a separate
digital ground plane.

Power planes should encompass a digital power plane and an
analog power plane. The analog power plane should contain the
DACs and all associated circuitry, V

REF

circuitry. The digital

power plane should contain all logic circuitry.

The analog and digital power planes should be individually
connected to the common power plane at a single point
through a suitable filtering device, such as a ferrite bead.

DAC output traces on a PCB should be treated as transmission
lines. It is recommended that the DACs be placed as close as
possible to the output connector, with the analog output traces
being as short as possible (less than 3 inches). The DAC termi-
nation resistors should be placed as close as possible to the DAC
outputs and should overlay the PCB's ground plane. As well as
minimizing reflections, short analog output traces will reduce
noise pickup due to neighboring digital circuitry.

To avoid crosstalk between the DAC outputs, it is recom-
mended that as much space as possible be left between the
tracks of the individual DAC output pins. The addition of
ground tracks between outputs is also recommended.

Supply Decoupling

Noise on the analog power plane can be further reduced by the
use of decoupling capacitors.

Optimum performance is achieved by the use of 10 nF and
0.1 µF ceramic capacitors. Each group of V

, V

, or V

DD_IO

pins should be individually decoupled to ground. This should
be done by placing the capacitors as close as possible to the
device with the capacitor leads as short as possible, thus
minimizing lead inductance.

A 1 µF tantalum capacitor is recommended across the V

supply in addition to 10 nF ceramic. See the circuit layout in
Figure 91.

Digital Signal Interconnect

The digital signal lines should be isolated as much as possible
from the analog outputs and other analog circuitry. Digital
signal lines should not overlay the analog power plane.

Due to the high clock rates used, avoid long clock lines to the
ADV7320/ADV7321 to minimize noise pickup.

Any active pull-up termination resistors for the digital inputs
should be connected to the digital power plane and not the
analog power plane.

Analog Signal Interconnect

Locate the ADV7320/ADV7321 as close as possible to the
output connectors to minimize noise pickup and reflections due
to impedance mismatch.

ADV7320/ADV7321

Rev. 0 | Page 64 of 88

For optimum performance, the analog outputs should each be
source- and load-terminated, as shown in Figure 91. The
termination resistors should be as close as possible to the
ADV7320/ADV7321 to minimize reflections.

For optimum performance, it is recommended that all
decoupling and external components relating to the
ADV7320/ADV7321 are located on the same side of the PCB
and as close as possible to the ADV7320/ADV7321. Any
unused inputs should be tied to ground.

DD_IO

COMP1, 2

DD_IO

ADV7320/

ADV7321

CLKIN_B

CLKIN_A

EXT_LF

UNUSED

INPUTS

SHOULD BE

GROUNDED

C0C9

S0S9

Y0Y9

4.7

4.7k

820pF

3.9nF

GND_ IO

AGND

DGND

11, 57

C BUS

10nF

0.1

10nF

0.1

10, 56

DD_IO

10nF

0.1

POWER SUPPLY DECOUPLING

FOR EACH POWER SUPPLY GROUP

0.1

DAC D

DAC E

DAC F

DAC A

DAC B

DAC C

REF 46

1.1k

RECOMMENDED EXTERNAL

AD1580 FOR OPTIMUM

PERFORMANCE

DD_IO

SCLK

100

680

SDA

ALSB

SET1

SET2

100

3040

SELECTION HERE

DETERMINES

DEVICE ADDRESS

3040

DD_IO

S_HSYNC

S_VSYNC

S_BLANK

P_HSYNC

P_VSYNC

P_BLANK

RESET

05067-091

100nF

ALL COMPONENTS IN DASHED BOXES MUST BE LOCATED ON THE SAME SIDE
OF THE PCB AS THE ADV7320/21 AND AS CLOSE AS POSSIBLE TO THE ADV7320/21.

300

Figure 91. ADV7320/ADV7321 Circuit Layout

ADV7320/ADV7321

Rev. 0 | Page 65 of 88

APPENDIX 1--COPY GENERATION MANAGEMENT SYSTEM

PS CGMS

Data Registers 2 to 0

[Subaddresses 0x21, 0x22, 0x23]

525p

Using the vertical blanking interval 525p system, 525p CGMS
conforms to the CGMS-A EIA-J CPR1204-1 (March 1998)
transfer method of video identification information and to the
IEC61880 (1998) 525p/60 video system's analog interface for the
video and accompanying data.

When PS CGMS is enabled [Subaddress 0x12, Bit 6 = 1], CGMS
data is inserted on Line 41. The 525p CGMS data registers are at
Addresses 0x21, 0x22, and 0x23.

625p

The 625p CGMS conforms to the IEC62375 (2004) 625p/50
video system's analog interface for the video and accompanying
data using the vertical blanking interval.

When PS CGMS is enabled [Subaddress 0x12, Bit 6 = 1], CGMS
data is inserted on Line 43. The 625p CGMS data registers are at
Addresses 0x22, and 0x23.

HD CGMS

[Address 0x12, Bit 6]

The ADV7320/ADV7321 support copy generation management
system (CGMS) in HDTV mode (720p and 1080i) in
accordance with EIAJ CPR-1204-2.

The HD CGMS data registers are found at Addresses 0x021,
0x22, and 0x23.

SD CGMS

Data Registers 2 to 0

[Subaddresses 0x59, 0x5A, 0x5B]

The ADV7320/ADV7321 support copy generation management
system (CGMS), conforming to the EIAJ CPR-1204 and ARIB
TR-B15 standards. CGMS data is transmitted on Line 20 of the
odd fields and Line 283 of even fields. Bits C/W05 and C/W06
control whether CGMS data is output on odd and even fields.
CGMS data can be transmitted only when the
ADV7320/ADV7321 is configured in NTSC mode. The CGMS
data is 20 bits long. The CGMS data is preceded by a reference
pulse of the same amplitude and duration as a CGMS bit; see
Figure 94.

FUNCTION OF CGMS BITS

For Word 0 to 6 bits, Word 1 to 4 bits, and Word 2 to 6 bits CRC
6 bits,

Polynomial

CRC

where default is preset to 111111.

720p System

CGMS data is applied to Line 24 of the luminance vertical
blanking interval.

1080i System

CGMS data is applied to Line 19 and Line 582 of the luminance
vertical blanking interval.

CGMS FUNCTIONALITY

If SD CGMS CRC [Address 0x59, Bit 4] or PS/HD CGMS CRC
[Subaddress 0x12, Bit 7] is set to Logic 1, the last six bits, C19 to
C14, which comprise the 6-bit CRC check sequence, are
automatically calculated on the ADV7320/ADV7321. This
calculation is based on the lower 14 bits (C0 to C13) of the data
in the data registers and output with the remaining 14 bits to
form the complete 20 bits of the CGMS data. The calculation of
the CRC sequence is based on the polynomial ×6 + x + 1 with a
preset value of 111111. If SD CGMS CRC [Address 0x59, Bit 4]
and PS/HD CGMS CRC [Address 0x12, Bit 7] are set to Logic 0,
all 20 bits (C0 to C19) are output directly from the CGMS
registers (CRC must be calculated by the user manually).

ADV7320/ADV7321

Rev. 0 | Page 68 of 88

APPENDIX 2--SD WIDE SCREEN SIGNALING

[Subaddresses 0x59, 0x5A, 0x5B]

The ADV7320/ADV7321 support wide screen signaling (WSS)
conforming to the ETS 300 294 standard. WSS data is
transmitted on Line 23. WSS data can be transmitted only when
the device is configured in PAL mode. The WSS data is 14 bits
long, and the function of each of these bits is shown in Table 40.

The WSS data is preceded by a run-in sequence and a start
code; see Figure 97. If SD WSS [Address 0x59, Bit 7] is set to
Logic 1, it enables the WSS data to be transmitted on Line 23.
The latter portion of Line 23 (42.5 s from the falling edge of
HSYNC) is available for the insertion of video. It is possible to
blank the WSS portion of Line 23 with Subaddress 0x61, Bit 7.

Table 40. Function of WSS Bits

Bit

Description

Bit 0 to Bit 2

Aspect Ratio/Format/Position

Bit 3

Odd Parity Check of Bit 0 to Bit 2

Aspect Ratio

Format

Position

0 0 1

4:3

Full

Format

N/A

0 0 0

14:9

Letterbox

Center

1 0 0

14:9

Letterbox

Top

1 0 1

16:9

Letterbox

Center

0 1 0

16:9

Letterbox

Top

0 1 1

>16:9

Letterbox

Center

1 1 1

14:9

Full

Format

Center

1 1 0

16:9

N/A

1 1 0

16:9

Camera Mode

Film Mode

Standard Coding

Motion Adaptive Color Plus

No Helper

Modulated Helper

Reserved

B10

No Open Subtitles

Subtitles in Active Image Area

Subtitles out of Active Image Area

Reserved

B11

No Surround Sound Information

Surround Sound Mode

B12

Reserved

B13

Reserved

ACTIVE

VIDEO

RUN-IN

SEQUENCE

START

CODE

500mV

11.0

38.4

42.5

W9 W10 W11 W12 W13

05067-097

Figure 97. WSS Waveform Diagram

ADV7320/ADV7321

Rev. 0 | Page 69 of 88

APPENDIX 3--SD CLOSED CAPTIONING

[Subaddresses 0x51 to 0x54]

The ADV7320/ADV7321 support closed captioning conforming
to the standard television synchronizing waveform for color
transmission. Closed captioning is transmitted during the
blanked active line time of Line 21 of the odd fields and Line
284 of the even fields.

Closed captioning consists of a 7-cycle sinusoidal burst that is
frequency and phase locked to the caption data. After the clock
run-in signal, the blanking level is held for two data bits and is
followed by Logic 1 start bit. Sixteen bits of data follow the start
bit. These consist of two 8-bit bytes, seven data bits, and one
odd parity bit. The data for these bytes is stored in the SD
closed captioning registers [Addresses 0x53 to 0x54].

The ADV7320/ADV7321 also support the extended closed
captioning operation, which is active during even fields and
encoded on Scan Line 284. The data for this operation is stored
in the SD closed captioning registers [Addresses 0x51 to 0x52].

All clock run-in signals and timing to support closed captioning
on Lines 21 and 284 are generated automatically by the
ADV7320/ ADV7321. All pixels inputs are ignored during
Lines 21 and 284 if closed captioning is enabled.

FCC Code of Federal Regulations (CFR) 47 section 15.119 and
EIA608 describe the closed captioning information for Line 21
and Line 284.

The ADV7320/ADV7321 use a single buffering method. This
means that the closed captioning buffer is only 1 byte deep;
therefore, there will be no frame delay in outputting the closed
captioning data, unlike other 2-byte-deep buffering systems.
The data must be loaded one line before it is output on Line 21
and Line 284. A typical implementation of this method is to use
VSYNC to interrupt a microprocessor, which in turn will load
the new data (2 bytes) in every field. If no new data is required
for transmission, 0s must be inserted in both data registers; this
is called nulling. It is also important to load control codes, all of
which are double bytes, on Line 21, or a TV will not recognize
them. If there is a message such as "Hello World" that has an
odd number of characters, it is important to add a blank
character at the end so that the end-of-caption, 2-byte control
code lands in the same field.

D0D6

10.5

0.25

12.91

7 CYCLES OF

0.5035MHz

CLOCK RUN-IN

REFERENCE COLOR BURST

(9 CYCLES)

FREQUENCY = F

= 3.579545MHz

AMPLITUDE = 40 IRE

50 IRE

40 IRE

10.003

27.382

33.764

BYTE 1

BYTE 0

TWO 7-BIT + PARITY

ASCII CHARACTERS

(DATA)

05067-098

Figure 98. Closed Captioning Waveform, NTSC

ADV7320/ADV7321

Rev. 0 | Page 72 of 88

The register settings in Table 41 are used to generate an SD
NTSC CVBS output on DAC A, S-video on DACs B and C, and
YPrPb on DACs D, E, and F. Upon power-up, the subcarrier
registers are programmed with the appropriate values for
NTSC. All other registers are set as normal/default.

Table 41. NTSC Test Pattern Register Writes

Subaddress

Register Setting

0x00 0xFC
0x40 0x10
0x42 0x40
0x44

0x40 (internal test pattern on)

0x4A 0x08

For PAL CVBS output on DAC A, the same settings are used,
except that Subaddress 0x40 is programmed to 0x11 and the F

registers are programmed as shown in Table 42.

Table 42. PAL F

Register Writes

Subaddress

Description

Register Setting

0x4C F

0 0xCB

0x4D F

1 0x8A

0x4E F

2 0x09

0x4F F

3 0x2A

Note that when programming the F

registers, the user must

write the values in the sequence F

0, F

1, F

2, F

3. The full

value to be written is only accepted after the F

3 write is

complete.

The register settings in Table 43 are used to generate a 525p
hatch pattern on DAC D, E, and F. All other registers are set as
normal/default.

Table 43. 525p Test Pattern Register Writes.

Subaddress

Register Setting

Ox00 0xFC
0x01 0x10
0x10 0x00
0x11 0x05
0x16 0xA0
0x17 0x80
0x18 0x80

For 625p hatch pattern on DAC D, the same register settings are
used except that Subaddress 0x10 = 0x18.

ADV7320/ADV7321

Rev. 0 | Page 73 of 88

APPENDIX 5--SD TIMING MODES

[Subaddress 0x4A]

MODE 0 (CCIR-656)--SLAVE OPTION
(TIMING REGISTER 0 TR0 = X X X X X 0 0 0)

The ADV7320/ADV7321 are controlled by the SAV (start active
video) and EAV (end active video) time codes in the pixel data.
All timing information is transmitted using a 4-byte
synchronization pattern. A synchronization pattern is sent
immediately before and after each line during active picture and
retrace. If Pins S_VSYNC, S_HSYNC, and S_BLANK are not
used, they should be tied high during this mode. Blank output
is available.

Y F

Y C

EAV CODE

SAV CODE

ANCILLARY DATA

(HANC)

4 CLOCK

268 CLOCK

1440 CLOCK

4 CLOCK

280 CLOCK

1440 CLOCK

END OF ACTIVE

VIDEO LINE

START OF ACTIVE

VIDEO LINE

ANALOG

VIDEO

INPUT PIXELS

NTSC/PAL M SYSTEM

(525 LINES/60Hz)

PAL SYSTEM

(625 LINES/50Hz)

05067-109

Figure 109. SD Slave Mode 0

ADV7320/ADV7321

Rev. 0 | Page 77 of 88

MODE 1--MASTER OPTION
(TIMING REGISTER 0 TR0 = X X X X X 0 1 1)

In this mode, the ADV7320/ADV7321 can generate horizontal
sync and odd/even field signals. When HSYNC is low, a
transition of the field input indicates a new frame, i.e., vertical
retrace. The BLANK signal is optional. When the BLANK input
is disabled, ADV7320/ADV7321 automatically blank all
normally blank lines as per CCIR-624. Pixel data is latched on
the rising clock edge following the timing signal transitions.
HSYNC, BLANK, and FIELD are output on S_HSYNC,
S_BLANK, and S_VSYNC.

622

623

624

625

DISPLAY

VERTICAL BLANK

ODD FIELD

EVEN FIELD

FIELD

DISPLAY

309

310

311

312

313

314

315

316

317

318

319

334

335

336

DISPLAY

VERTICAL BLANK

ODD FIELD

EVEN FIELD

DISPLAY

320

FIELD

HSYNC

BLANK

HSYNC

BLANK

05067-114

Figure 114. SD Slave Mode 1 (PAL)

FIELD

PIXEL

DATA

PAL = 12

CLOCK/2

NTSC = 16

CLOCK/2

HSYNC

BLANK

PAL = 132

CLOCK/2

NTSC = 122

CLOCK/2

05067-115

Figure 115. SD Timing Mode 1--Odd/Even Field Transitions Master/Slave

ADV7320/ADV7321

Rev. 0 | Page 78 of 88

MODE 2-- SLAVE OPTION
(TIMING REGISTER 0 TR0 = X X X X X 1 0 0)

In this mode, the ADV7320/ADV7321 accept horizontal and
vertical sync signals. A coincident low transition of both HSYNC
and VSYNC inputs indicates the start of an odd field. A VSYNC
low transition when HSYNC is high indicates the start of an even
field. The BLANK signal is optional. When the BLANK input is
disabled, ADV7320/ADV7321 automatically blank all normally
blank lines as per CCIR-624. HSYNC, BLANK, and VSYNC are
input on S_HSYNC, S_BLANK, and S_VSYNC, respectively.

522

523

524

525

DISPLAY

VERTICAL BLANK

ODD FIELD

EVEN FIELD

260

261

262

263

264

265

266

267

268

269

270

271

272

273

274

283

284

285

ODD FIELD

EVEN FIELD

DISPLAY

VERTICAL BLANK

HSYNC

BLANK

VSYNC

HSYNC

BLANK

VSYNC

05067-116

Figure 116. SD Slave Mode 2 (NTSC)

622

623

624

625

DISPLAY

VERTICAL BLANK

ODD FIELD

EVEN FIELD

DISPLAY

309

310

311

312

313

314

315

316

317

318

319

334

335

336

DISPLAY

VERTICAL BLANK

ODD FIELD

EVEN FIELD

DISPLAY

320

HSYNC

BLANK

VSYNC

HSYNC

BLANK

VSYNC

05067-117

Figure 117. SD Slave Mode 2 (PAL)

ADV7320/ADV7321

Rev. 0 | Page 79 of 88

MODE 2--MASTER OPTION
(TIMING REGISTER 0 TR0 = X X X X X 1 0 1)

In this mode, the ADV7320/ADV7321 can generate horizontal
and vertical sync signals. A coincident low transition of both
HSYNC and VSYNC inputs indicates the start of an odd field.

A VSYNC low transition when HSYNC is high indicates the
start of an even field. The BLANK signal is optional. When the
BLANK input is disabled, the ADV7320/ADV7321
automatically blank all normally blank lines as per CCIR-624.
HSYNC, BLANK, and VSYNC are output on S_HSYNC,
S_BLANK, and S_VSYNC, respectively.

05067-118

PIXEL

DATA

HSYNC

BLANK

VSYNC

PAL = 12

CLOCK/2

NTSC = 16

CLOCK/2

PAL = 132

CLOCK/2

NTSC = 122

CLOCK/2

Figure 118. SD Timing Mode 2 Even-to-Odd Field Transition Master/Slave

PIXEL

DATA

HSYNC

BLANK

VSYNC

PAL = 12

CLOCK/2

NTSC = 16

CLOCK/2

PAL = 132

CLOCK/2

NTSC = 122

CLOCK/2

PAL = 864

CLOCK/2

NTSC = 858

CLOCK/2

05067-119

Figure 119. SD Timing Mode 2 Odd-to-Even Field Transition

ADV7320/ADV7321

Rev. 0 | Page 80 of 88

MODE 3--MASTER/SLAVE OPTION
(TIMING REGISTER 0 TR0 =
X X X X X 1 1 0 OR X X X X X 1 1 1)

In this mode, the ADV7320/ADV7321 accept or generate hori-
zontal sync and odd/even field signals. When HSYNC is high, a
transition of the field input indicates a new frame, i.e., vertical
retrace. The BLANK signal is optional. When the BLANK input
is disabled, ADV7320/ADV7321 automatically blank all
normally blank lines as per CCIR-624. HSYNC, BLANK, and
VSYNC are output in master mode and input in slave mode on
S_VSYNC, S_BLANK, and S_VSYNC, respectively.

260

261

262

263

264

265

266

267

268

269

270

271

272

273

274

283

284

285

ODD FIELD

EVEN FIELD

DISPLAY

VERTICAL BLANK

522

523

524

525

DISPLAY

VERTICAL BLANK

ODD FIELD

EVEN FIELD

HSYNC

BLANK

FIELD

05067-120

HSYNC

BLANK

FIELD

Figure 120. SD Timing Mode 3 (NTSC)

622

623

624

625

DISPLAY

VERTICAL BLANK

ODD FIELD

EVEN FIELD

FIELD

DISPLAY

309

310

311

312

313

314

315

316

317

318

319

334

335

336

DISPLAY

VERTICAL BLANK

ODD FIELD

EVEN FIELD

FIELD

DISPLAY

320

HSYNC

BLANK

HSYNC

BLANK

05067-121

Figure 121. SD Timing Mode 3 (PAL)

ADV7320/ADV7321

Rev. 0 | Page 82 of 88

APPENDIX 7--VIDEO OUTPUT LEVELS

HD YPrPb OUTPUT LEVELS

INPUT CODE

940

EIA-770.2, STANDARD FOR Y

OUTPUT VOLTAGE

300mV

700mV

960

EIA-770.2, STANDARD FOR Pr/Pb

OUTPUT VOLTAGE

512

05067-123

Figure 123. EIA 770.2 Standard Output Signals (525p/625p)

782mV

714mV

286mV

700mV

INPUT CODE

940

EIA-770.1, STANDARD FOR Y

OUTPUT VOLTAGE

960

EIA-770.1, STANDARD FOR Pr/Pb

OUTPUT VOLTAGE

512

05067-124

Figure 124. EIA 770.1 Standard Output Signals (525p/625p)

300mV

INPUT CODE

940

EIA-770.3, STANDARD FOR Y

OUTPUT VOLTAGE

700mV

600mV

960

EIA-770.3, STANDARD FOR Pr/Pb

OUTPUT VOLTAGE

512

05067-125

Figure 125. EIA 770.3 Standard Output Signals (1080i/720p)

300mV

700mV

INPUT CODE

1023

YOUTPUT LEVELS FOR

FULL INPUT SELECTION

OUTPUT VOLTAGE

1023

Pr/PbOUTPUT LEVELS FOR

FULL INPUT SELECTION

OUTPUT VOLTAGE

INPUT CODE

05067-126

Figure 126. Output Levels for Full Input Selection

ADV7320/ADV7321

Rev. 0 | Page 85 of 88

0.5

APL = 44.5%

525 LINE NTSC

SLOW CLAMP TO 0.00V AT 6.72

L76

100

50

VOLTS IRE:FLT

MICROSECONDS

PRECISION MODE OFF

SYNCHRONOUS SYNC = A

FRAMES SELECTED 1, 2

05067-137

Figure 137. NTSC Color Bars 75%

05067-138

NOISE REDUCTION: 15.05dB

APL NEEDS SYNC SOURCE.

525 LINE NTSC NO FILTERING

SLOW CLAMP TO 0.00 AT 6.72

L76

50

0.4

0.2

0.4

MICROSECONDS

PRECISION MODE OFF

SYNCHRONOUS SYNC = B

FRAMES SELECTED 1, 2

VOLTS IRE:FLT

Figure 138. NTSC Chroma

05067-139

NOISE REDUCTION: 15.05dB

APL = 44.3%

525 LINE NTSC NO FILTERING

SLOW CLAMP TO 0.00 AT 6.72

L238

0.4

0.2

0.6

0.2

MICROSECONDS

PRECISION MODE OFF

SYNCHRONOUS SYNC = SOURCE

FRAMES SELECTED 1, 2

VOLTS IRE:FLT

Figure 139. NTSC Luma

05067-140

VOLTS

NOISE REDUCTION: 0.00dB

APL = 39.1%

625 LINE NTSC NO FILTERING

SLOW CLAMP TO 0.00 AT 6.72

L608

0.4

0.2

0.6

0.2

MICROSECONDS

PRECISION MODE OFF

SYNCHRONOUS SOUND-IN-SYNC OFF

FRAMES SELECTED 1, 2, 3, 4

Figure 140. PAL Color Bars 75%

05067-141

VOLTS

APL NEEDS SYNC SOURCE.

625 LINE PAL NO FILTERING

SLOW CLAMP TO 0.00 AT 6.72

L575

0.5

MICROSECONDS NO BUNCH SIGNAL

PRECISION MODE OFF

SYNCHRONOUS SOUND-IN-SYNC OFF

FRAMES SELECTED 1

Figure 141. PAL Chroma

05067-142

VOLTS

APL NEEDS SYNC SOURCE.

625 LINE PAL NO FILTERING

SLOW CLAMP TO 0.00 AT 6.72

L575

0.5

MICROSECONDS NO BUNCH SIGNAL

PRECISION MODE OFF

SYNCHRONOUS SOUND-IN-SYNC OFF

FRAMES SELECTED 1

Figure 142. PAL Luma

ADV7320/ADV7321

Rev. 0 | Page 86 of 88

APPENDIX 8--VIDEO STANDARDS

272T

1920T

EAV CODE

SAV CODE

DIGITAL

ACTIVE LINE

4 CLOCK

2112

2116 2156

2199

188

192

2111

FVH* = FVH AND PARITY BITS

SAV/EAV: LINE 1562: F = 0

SAV/EAV: LINE 5631125: F = 1

SAV/EAV: LINE 120; 561583; 11241125: V = 1

SAV/EAV: LINE 21560; 5841123: V = 0

FOR A FRAME RATE OF 30Hz: 40 SAMPLES

FOR A FRAME RATE OF 25Hz: 480 SAMPLES

INPUT PIXELS

ANALOG WAVEFORM

SAMPLE NUMBER

SMPTE 274M

DIGITAL HORIZONTAL BLANKING

ANCILLARY DATA

(OPTIONAL) OR BLANKING CODE

DATUM

05067-143

Figure 143. EAV/SAV Input Data Timing Diagram--SMPTE 274M

EAV CODE

ANCILLARY DATA

(OPTIONAL)

SAV CODE

DIGITAL

ACTIVE LINE

719

723 736

799

853

FVH* = FVH AND PARITY BITS

SAV: LINE 43525 = 200H

SAV: LINE 142 = 2AC

EAV: LINE 43525 = 274H

EAV: LINE 142 = 2D8

4 CLOCK

857

719

DATUM

DIGITAL HORIZONTAL BLANKING

SMPTE 293M

INPUT PIXELS

ANALOG WAVEFORM

SAMPLE NUMBER

05067-144

Figure 144. EAV/SAV Input Data Timing Diagram--SMPTE 293M

ADV7320/ADV7321

Rev. 0 | Page 88 of 88

OUTLINE DIMENSIONS

TOP VIEW

(PINS DOWN)

0.27
0.22
0.17

0.50

BSC

10.00

BSC SQ

1.60

MAX

SEATING

PLANE

0.75
0.60
0.45

VIEW A

12.00

BSC SQ

0.20
0.09

1.45
1.40
1.35

0.08 MAX

COPLANARITY

VIEW A

ROTATED 90° CCW

SEATING

PLANE

10°

6°
2°

7°

3.5°

0°

0.15
0.05

PIN 1

COMPLIANT TO JEDEC STANDARDS MS-026BCD

Figure 149. 64-Lead Low Profile Quad Flat Package [LQFP]

(ST-64-2)

Dimensions shown in millimeters

ORDERING GUIDE

Model

Temperature Range

Package Description

Package Option

ADV7320KSTZ

0°C to 70°C

64-Lead Low Profile Quad Flat
Package [LQFP]

ST-64-2

ADV7321KSTZ

0°C to 70°C

64-Lead Low Profile Quad Flat
Package [LQFP]

ST-64-2

EVAL-ADV7320EB

Evaluation Board

EVAL-ADV7321EB

Evaluation Board

Z = Pb-free part.

registered trademarks are the property of their respective owners.

D05067010/04(0)

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: ADV7320

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: ADV7320

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: ADV7320