ANALOG
DEVICES
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regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights
of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106, U.S.A.
www.analog.com/video
Tel:1-800-ANALOGD (262-5643) Fax:781-461-3700
Analog Devices,Inc., 2001
Features
SURFTM (Spatial Ultra-efficient Recursive Filtering)
patented technology enables high-performance,
low-power, and low-cost JPEG2000 compression/
decompression.
Lossless compression at >10 Mpixels/second
Reversible and irreversible 5/3 wavelet transform.
Lossless and Lossy compression modes. Supports
8 or 10-bit pixel components in reversible mode and
8 to 14-bit pixel components in irreversible mode.
Programmable tile size up to 160 x 128 in three-
component interleaved mode, up to 256 x 256 in
single-component mode.
Flexible pixel/component interface.
Coding pass distortion metrics provided for precise
control of compressed image size.
A single 16-bit asynchronous SRAM style interface
allows glue-less connection to most microcontrollers
and ASICs.
3.3v I/O and 1.5-1.8v core supply.
7mm x 7mm 48-ball fpBGA.
Applications
Digital Still Cameras
Networked video and image distribution systems
Wireless video and image distribution
Image archival/retrieval
Digital CCTV and surveillance systems
Video editing systems
General Description
The ADV-JP2000 is a high-performance image com-
pression co-processor that implements the computa-
tionally intensive operations of the JPEG2000 (J2K)
image compression standard. The ADV-JP2000 can
process images at a rate of >10 Mpixels/sec in lossless
mode, and at significantly higher rates when used in
lossy mode. The chip supports lossless compression
of 8 or 10-bit component data and can support lossy
compression of component data up to 14-bits. This
chip, along with a minimal amount of software on the
user's host processor, will provide a complete high per-
formance JPEG2000 image compression and decom-
pression solution. The chip contains a full custom
wavelet processor and entropy codec as well as asso-
ciated interface and control functions. The wavelet
processor implements the 5/3 wavelet transform in
either reversible or irreversible modes. The entropy
codec supports the key features in the current
JPEG2000 specification. The ADV-JP2000 provides a
very flexible interface that supports a wide variety of
pixel and component formats.
The ADV-JP2000 provides a single simple asynchro-
nous interface for all communications between itself
and a host CPU or system ASIC. The ADV-JP2000
supports both single and dual-address DMA transfers
to and from on-chip FIFOs. A complete definition of the
DMA process is described in "DMA Access Modes," on
page 5. Control and status registers within the ADV-
JP2000 are addressed directly using the address bus,
JPEG2000 Co-processor
Preliminary Technical Data
ADV-JP2000
SURF is a trademark of Analog Devices, Inc.
Wavelet Pipe &
Quantizer
SRAM
Entropy CODEC
Attribute FIFO
Control & Status
Data FIFO
PLL
ADDR
DATA
CTRL
STATUS
CLKIN
Hos
t
In
ter
f
ac
e
16-May-2001
Rev. PrA
PRELIMINARY TECHNICAL DATA
16-May-2001
2
Rev. PrA
ADV-JP2000
the chip select, and the appropriate read or write
strobe.
Operational Overview
The ADV-JP2000 has two basic modes of opera-
tion, encode and decode. In encode (compres-
sion), the ADV-JP2000 accepts a single
uncompressed image tile and creates a stream of
J2K compliant code-blocks. In decode (decom-
pression), this process is reversed. Both encode
and decode are broken down into two separate
processes, Wavelet processing, which includes
quantization, and Entropy processing.
The ADV-JP2000 operates on a rectangular sec-
tion of an image called a tile. The maximum tile
size supported depends on the number of compo-
nents in the tile and the maximum desired width.
For component interleaved tiles (i.e., tiles contain-
ing both luminance and chrominance data) the
ADV-JP2000's maximum tile size is 160 x 128. For
single-component tiles, the maximum tile size is
256 x 256. The minimum tile size supported is 8 x
8.
During encode, the ADV-JP2000 also generates a
stream of attributes for each code-block. The
code-block attributes are used by the host's soft-
ware to create packet headers for the final J2K bit
stream. The chip can also be programmed to pro-
vide distortion metrics for each coding pass. The
distortion metrics can be used by the host software
to precisely control the resultant file size when
operating in lossy mode.
During decode, the ADV-JP2000 requires a mini-
mal set of attributes to be loaded prior to process-
ing each code-block. Details of the attribute data
are describe in "Code-block Attribute Formats," on
page 3
The encode process consists of five basic steps:
(1) load configuration and operating parameters,
(2) load a single uncompressed tile into the ADV-
JP2000, (3) issue a start command, (4) wait for
output data to become ready, and (5) unload J2K
compressed code-blocks and attributes. The
attributes can be read after each code-block is
completed, or the user can allow them to accumu-
late in the attribute FIFO to be read at a later time.
Note: If the ADV-JP2000 is configured for code-
block termination and distortion metric output is not
enabled, then all of the attribute data for the com-
plete tile will fit in the on-chip FIFO. This allows the
host software to wait until it has unloaded all code-
block data before having to unload the attribute
data.
The decode process also consists of five basic
steps: (1) load configuration and operating param-
eters, (2) load a set of J2K compressed code-
blocks and attributes for a single tile into the ADV-
JP2000, (3) issue a start command, (4) wait for
output data to become ready, and (5) unload the
uncompressed tile. Each code-block's attributes
must have been written to the ADV-JP2000 prior to
loading its associated code-block. A code-block's
attributes can be written immediately prior to load-
ing the code-block, or several code-blocks worth of
attributes can be written in advance provided there
is room for them in the attribute FIFO.
Data FIFO Formats
This FIFO is used to transfer either uncompressed
tile data or J2K compressed code-blocks. The
data type and access direction are implied from the
mode and load state of the ADV-JP2000. The
Data FIFO is comprised of 128 words (16-bits).
Pixel Formats
The ADV-JP2000 supports three component
modes: (1) three-component interleaved, (2) two-
component interleaved, and (3) single-compo-
nent. Three-component mode supports 4:2:2 tiles
in which Y, Cb and Cr are interleaved. The two-
component interleaved mode is used when pro-
cessing a chrominance (Cb/Cr) only tile when
using 4:2:2 pixel data formats. Single-component
supports a tile with only one component, such as
luminance. It can also be used to process 4:4:4
data, one component at a time. Uncompressed tile
data is always transferred in raster order starting
from the upper-left corner of the tile.
The ADV-JP2000 supports both reversible and
irreversible wavelet transforms. The reversible
transform supports either 8 or 10-bit pixel compo-
nent input. The irreversible transform supports
fixed precision 8 and 10-bit pixel components as
well as a variable precision format that supports up
to 14-bits. The user may optionally specify zero,
one or two guard bits when using 8 or 10-bit data.
8 and 10-bit pixel components are right (lsb) justi-
fied on the 16-bit data bus. The ADV-JP2000 also
supports several packing modes to allow two 8-bit
components to be transferred in a single 16-bit
word. For three-component 4:2:2 mode, this repre-
sents pairs of Y/Cb and Y/Cr. For two-component
interleaved mode, pairs of Cb and Cr are packed
PRELIMINARY TECHNICAL DATA
ADV-JP2000
Rev. PrA
3
16-May-2001
into one word. For single-component mode, two
components of the same type can be packed into
one word. For non-packed formats, the user must
provide the data in a properly interleaved fashion.
For example, for three-component 4:2:2 non-
packed mode, the data must be presented in the
following order Y
0
,Cb
0
,Y
1
,Cr
0
,Y
2
,Cb
2
,Y
3
,Cb
2
,...
The ADV-JP2000 also features a raw pixel compo-
nent mode that supports up to 14-bits per compo-
nent. In raw mode the pixel components must be
left (msb) justified on the 16-bit data bus and all
scaling, guard bit adjustment, and sign extension
must be done by the user. Input data of less then
14-bits must be padded out to 14-bits by inserting
zeros into the lsbs. The alignment of all pixel for-
mats is shown in Figure 1, "Pixel Component For-
mats," on pag e3.
Compressed Byte Stream Format
The ADV-JP2000 encodes or decodes JPEG2000
byte stream code-blocks. The code-blocks are
always 64 by 64 unless the wavelet sub-band is
smaller then that dimension. In that case, the
code-block's size will be equal to the sub-band
size. The bytes are packed into 16-bit words in
big-endian order. If a compressed code-block
ends on an odd byte boundary, then the first com-
pressed byte of the next codeblock will be packed
into the low byte. The exception to this is at the end
of the last codeblock in the tile. In this case, the low
byte in the last word will be padded with zeroes.
Code-block Attribute Formats
During encode, the Attribute FIFO is used to trans-
fer the code-block attributes to the host CPU so
that the software can create the necessary J2K
packet headers. When the ADV-JP2000 is in
encode mode, it will output two header words for
each code-block and a segment length count for
each coding pass. Optionally, if distortion metrics
are enabled, then each segment length count will
also be paired with the corresponding distortion
metric for the particular coding pass.
During decode, this FIFO is used to transfer code-
block attributes to the ADV-JP2000 so that the
compressed code-blocks can be properly extracted
and decompressed. When the JP2000 is in
decode, the host CPU must not insert distortion
metrics into the Attribute FIFO. The Attribute FIFO
is comprised of 128 words (16-bits).
Ignored
MSB(9)
Y, Cb or Cr
LSB(0)
(15:10)
(9:0)
MSB(7)
Y
LSB(0)
MSB(7)
Cb or Cr
LSB(0)
(15:8)
(7:0)
Ignored
MSB(7)
Y, Cb or Cr
LSB(0)
(15:8)
(7:0)
MSB(7)
Cb
LSB(0)
MSB(7)
Cr
LSB(0)
(15:8)
(7:0)
MSB(13)
Y/Cb/Cr
LSB(0)
(15:2)
Ignored
FIGURE 1. Pixel Component Formats
(1:0)
MSB(7)
Y or Cb
LSB(0)
MSB(7)
Y or Cr
LSB(0)
(15:8)
(7:0)
PMODE=4
PMODE=0
PMODE=1
PMODE=2
PMODE=2
PMODE=7
8-bit packed
Y/Cb, Y/Cr interleaved
8-bit packed
single component or
YY, Cb/Cr interleaved
8-bit packed
Chroma only
10-bit
8-bit
Raw
PRELIMINARY TECHNICAL DATA
16-May-2001
4
Rev. PrA
ADV-JP2000
Code-block Header 1
First word of code-block attribute packet for each code-block.
Code-block Header 2
Second word of code-block attribute packet for each code-block.
Code-block Distortion Metric
The distortion metric for each code-word segment. This data is optional in encode mode and must be
omitted in decode mode.
Code-word Segment Length
The length of the code-word segment in bytes.
Bit(s)
Name
Description
Note:
1:0
CBY
Code-block Y index
3:2
CBX
Code-block X index
5:4
SBID
Sub-band ID; 0=LL, 1=LH, 2=HL, 3=HH
7:6
LEV
Transform Level; 0=lowest
9:8
COMP
Component; 0=Y, 1=Cb, 2=Cr
13:10
NZBP
Number of leading zero bit-planes
14
LCB
Last code-block flag, must be set to 1 for last code-block, 0 other-
wise.
15
CHF
Code header flag, set to 1 to indicate this is a header word
Bit(s)
Name
Description
Note:
5:0
NCP
Number of coding passes in code-block
11:6
NCS
Number of code-word segments
12
RCE
Byte length running counts; 0=delta counts, 1=running count
Encode
only
13
BLE
Byte lengths included; 0=not include, 1=included
Encode
only
14
DME
Distortion metrics included; 0=not included, 1=included
Encode
only
15
CHF
Code header flag, set to 1 to indicate this is a header word
Bit(s)
Name
Description
Note:
7:0
MANT
Mantissa
14:8
EXP
Exponent
15
CHF
Code block header flag, Must always be zero for this word
Bit(s)
Name
Description
Note:
14:0
CSL
Number of bytes in code-word segment
15
CHF
Code block header flag, Must always be zero for this word
PRELIMINARY TECHNICAL DATA
ADV-JP2000
Rev. PrA
5
16-May-2001
DMA Access Modes
In addition to normal addressed read and write
operations, the ADV-JP2000 supports self initiated
DMA and host initiated DMA accesses.
Both single and dual-address DMA modes are sup-
ported for self initiated DMA. The dual-address
mode is very similar to the addressed read and
write operations except the ADV-JP2000 initiates a
data transfer by asserting DREQ. In single-
address DMA mode, the ADV-JP2000 also initiates
the data transfer by asserting DREQ, but it deter-
mines the direction and type of transfer based on
the load-state and access mode of the chip.
The ADV-JP2000 operates in one of two modes,
encode or decode. Furthermore, each of these
modes has two load-states, load or unload. When
the ADV-JP2000 is in single-address DMA mode, it
is capturing data in fly-by mode. In this mode the
ADV-JP2000 is capturing data off of the data bus
while sharing a common set of read/write enables
with another peripheral. This makes it necessary
for the ADV-JP2000 to have different interpreta-
tions of the RD and WE signals. For instance,
when the ADV-JP2000 is in Encode, Single-
address DMA mode, and expecting data to be
loaded, it is actually watching the data bus for
reads (RD) issued by the host CPU and ignores
any writes. When it sees a read on the data bus, it
actually interprets this as a write. Conversely, when
the ADV-JP2000 is expecting data to be unloaded,
it will interpret writes (WE) issued by the host CPU
as reads and ignore any writes.
The functionality of the RD, WE and DACK pins for
single-address DMA mode is described in Table 1,
"Single-address DMA mode pin functionality.," on
page 5 below.
* DACK acts as chip select (CS)
Table 1: Single-address DMA mode pin functionality.
CS
Mode
Access Mode
Load-State
RD
WE
DACK
0
Don't
care
Don't care
Don't care
Register read
Register write
Normal
1
ENC
Single
Load
Pixel write
Ignored
*
1
ENC
Single
Unload
Ignored
Code-block read
*
1
DEC
Single
Load
Code-block write
Ignored
*
1
DEC
Single
Unload
Ignored
Pixel read
*
CPU CPU
DMA ASIC readDMA ASIC read
CPU
CPU
DMA ASIC write
IN
IN
DATA OUT
Load Operation
Unload Operation
CLKIN
DREQ
DACK
ADDR
CS
RD
WE
JP DATA IO
LD
FIGURE 1. Example of Single-address DMA Operation
PRELIMINARY TECHNICAL DATA
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