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Semiconductor Components Industries, LLC, 2004

July, 2004 - Rev. 5

Publication Order Number:

AND8020/D

AND8020/D

Termination of ECL

Logic Devices with

EF (Emitter Follower)

OUTPUT Structure

Prepared by: Paul Shockman
ON Semiconductor Logic Applications Engineering

CONTENTS OF APPLICATION NOTE

Introduction - DC Termination Analysis

Vt1

Vt2

External

Internal

Near (Standard Pair)

Far (Standard Pair)

Vt1

Vt2

(Open)

(Shorted)

Near (Standard Pair)

Section 2. Parallel Termination - External and Internal

Section 1. Unterminated Lines

Section 3. Thevenin Equivalent/Parallel Termination

Section 4. Series (Back) Termination

Driver

Receiver

*All Media

Section 5. Diode Termination

Section 6. Capacitive Coupling

APPLICATION NOTE

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INTRODUCTION
Static DC Termination Analysis

A standard Emitter Coupled Logic (ECL) output driver

typically uses a current switching differential with an emitter
follower for level shifting the output and the internal CML
levels to familiar ECL levels. This output driver architecture
presents about 6-8

W internal impedance in both LOW and

HIGH states when properly current biased. This results in a
typical V

signal of 800 mV

(measured single-endedly on

each line) swinging around a DC voltage point of
V

1.3

V when properly terminated and operating

correctly as shown in Figure 1.

Driver

Receiver

Internal Output

Impedance

Figure 1. Typical ECL Output with Emitter Follower Output Structure,

Typical Termination, and Typical ECL Input Interconnect

For proper static and dynamic operation, the output

emitter follower transistor must remain in the active region
of operation which requires an external resistive path be
provided from the output pin to a voltage more negative than
worst case V

, such as V

. The resistor, R

, is considered

a current bias for the Emitter Follower output structure.

When properly terminated and current biased (loaded),

the outputs will generate both: (1) static state voltage levels
V

(LOW) or V

(HIGH) and (2) a dynamic transition

edge (tr or tf) between state levels.

Static State Voltage Levels

Figure 2 illustrates the typical relationship of static signal

levels and dynamic transition edges between an Output
Driver Signal and a Receiver Input Signal. Both outputs of
a differential driver should always be terminated and loaded
as identically as possible to preserve minimum skew and
jitter operation of the device.

Figure 2. State Levels V

, V

and Dynamic Transitions at Q or Q and D or D

-1.3 V

Output

Driver

Signal

Input
Receiver
Signal

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Output Open, Short, and Safe DC Current

Left open, an output will only swing a few millivolts due

to parasitic "minimum current" leakage paths.

Shorted to V

, a maximum current will develop, limited

only by the output transistor 8

W impedance, and may cause

damage to the output. Worst case short circuit current risks
destruction of the devices.

ISC

VOH

RINT

4 V

= 500 mA!

(eq. 1)

Where:

= 4.0 V

= 5.0 V

= 0.0 V

int

= 8

The continuous safe output current, I

out

(continuous),

maximum limit is 50 mA under all spec operating
conditions. The continuous safe repetitive surge, I

out

(surge), maximum current limit is 100 mA for
10 milliseconds per second duty cycle, provided the device's
total thermal limits are observed. Output current polarity
will always be sinking into the termination scheme during
proper operation.

Static Analysis of Termination Resistor R

The output continuous safe current limit, I

out

(cont),

determines R

minimum DC termination scheme resistance

to V

although this will not provide a practical AC signal

termination as shown in Table A: Minimum R

Values.

VOH

I max

(eq. 2)

Table A. Minimum R

Values

Line

(min)

PECL

4.0 V

LVPECL

2.4 V

LVEP PECL

1.6 V

A DC terminating resistor minimum, R

(min), of 80

while sufficiently limiting the output load current to V

may generate insufficient PECL output LOW and HIGH
state transitions.

The R

maximum is effectively determined by the

application load capacitance, C

, since an RC network is

formed by R

and C

which limits the signal fall time,

discharging the line to the LOW state voltage level. A
sufficiently high value R

or C

can cause the signal fall

time to the V

level to violate specification limits.

Designed R

or C

values may selectively eliminate

undesirable noise.

Dynamic Analysis of Termination Resistor R

The dynamic function of the termination resistor, R

is to

develop the voltage change,

DV, during a high-to-low or

low-to-high transition and present this to the transmission
medium such as coax, twisted pair, microstrip or stripline.
The

DV signal propagates to the receiver and is either

reflected, dissipated, or a combination.

Since the reflection coefficient at the load is of opposite

polarity to that of the source, a reflection will travel back and
forth over the transmission changing polarity after each
reflection until critically damped by line impedance. Thus,
steps may appear in the signal

DV at the receiving gate input

due to impedance mismatch and consequent partial
reflections.

When R

is too large, steps appear in the trailing edge of

the propagating signal,

DV, at the input to the receiving gate,

slowing the edge speed and increasing the net propagation
delay. A reasonable negative-going signal swing at the input
of the receiving gate results when the value of R

is selected

to produce an initial step of 75% of the expected

DV, or a

600 mV step for an 800 mV signal at the driving gate. For
a RSECL expected

DV swing of 400, a 300 mV initial step

is desired. Hence for a 600 mV initial step:

( VOH

VEE )

( Rt

)

Z0 )

* Z0

0.6

I(init) * Z0

0.6

(eq. 3)

The value for R

is found in Table B: Recommended

Values of R

in Dynamic Functional Application. This table

lists recommended R

values for the various ECL devices by

Family Series according to the equation above. The table
assumes operation with various data sheet V

values and

various V

values driving a Z

= 50

W line. Lowering the

value of R

will increase the voltage change,

DV, launched

into the transmission media. Raising the value of R

will

decrease the voltage change,

DV, launched into the

transmission media.

Table B. Recommended Nominal Values of R

Dynamic Functional Application

Series

-V

(

2.5

140

3.3

250

10/100LVEP

2.5

10/100EP, 100LVEL

3.3

120

10/100EL, 10/100E

5.0

235

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SECTION 1. UNTERMINATED LINES

From transmission line theory, when the driver R

develops a

DV swing, the signal propagates from point A

arriving at point B at time Td later as shown in Figure 3. This
configuration is also referred to as a stub or an open line.

Figure 3. Unterminated Transmission Line Stub

T-Line Z

At point B, the signal is reflected as a function of

. If the

input impedance of the receiving gate is large relative to the
line characteristic impedance, according to Equation 4:

(RL

Z0)

(RL

)

Z0)

(eq. 4)

Where:

= Load Reflection Coefficient

= Load Impedance

= Line Characteristic Impedance

A large positive reflection occurs resulting in overshoot.

The reflected signal reaches point A at time 2Td , and a large
negative reflection results because the output impedance of
the driver gate is much less than the line characteristic
impedance (i.e. R

<< Z

When the reflected signal arrives at the source it is

reflected back toward the load with a magnitude dictated by
the source reflection coefficient:

(Rs

Z0)

(Rs

)

Z0)

(eq. 5)

Where:

= Source Reflection Coefficient

= Source Impedance

= Line Characteristic Impedance

The reflected signal continues to be reflected by the source

and load impedances and is attenuated with each passage over
the transmission line. The output response appears as a
damped oscillation asymptotically approaching a steady state
value. This phenomena is often referred to as "ringing."

The importance of minimizing the reflected signals lies in

their adverse affect on noise margin and the potential for
driving the input transistors of the succeeding stage into
saturation. Both of these phenomena can lead to less than
ideal system performance. To maximize signal integrity on
transmission lines, four basic techniques are available:

1. Minimizing Interconnect Line Lengths (Section 1)
2. Parallel Termination (Sections 2 and 3)
3. Series Termination (Section 4)
4. Diode Termination (Section 5)

Interconnect Line Lengths

The output signal Waveform rise (tr) and fall (tf) time are

measured from the 20% and 80% levels of the static signal
levels. This edge rate represents the waveforms highest
harmonic and determines the maximum unterminated open
line trace length, L

max

, permissible without sustaining

signal reflections.

The impetus in restricting interconnect lengths, L, is to

mitigate the effects of overshoot and undershoot. A handy
rule of thumb is that the undershoot can be limited to less
than 15% of the logic swing if the two way line delay is less
than the rise time of the pulse. With an undershoot of <15%,
the physics of the situation will result in an overshoot which
will not cause saturation problems at the receiving input.
Thus, the maximum line length can be determined:

L max

2 * Tpd

(eq. 6)

Where:

max

= Maximum Open Line Length

= Signal Rise Time

= Length Pulse Delay per Unit Length

Further, the propagation delay increases with gate

loading; thus, the effective delay per unit length (T

pdEff

) is

given as:

TpdEff

Tpd

)

L * CO

(eq. 7)

Where:

= Length Pulse Delay per Unit Length

= Distributed Capacitance

= Capacitance per Unit Length (Foot)

L = Line Length

Using the effective delay per unit length, Tpd

Eff,

yields:

(2) (L) (Tpd )

)

L * CO

(eq. 8)

Solving for L

max

line length produces:

L max

0.5

CD
CO

)

tpd

CD
CO

(eq. 9)

Where:

max

= Line Length Maximum

= Distributed Capacitance

= Capacitance per Unit Length (Foot)

= Length Pulse Delay per Unit Length

Assuming a worst case capacitance of 2 pF and a rise time

of 100 ps for EP gives a value of 0.03 inch for the maximum
open line length. Maximum open line lengths derived from
SPICE simulations for single and double gate loads, a
maximum overshoot of 40% and undershoot of 20% was
assumed. The simulation results indicate that for a 50

W line,

a stub length of

x 0.03 inches will limit the overshoot to less

than 40%, and the undershoot to within 20% of the logic
swing. Signal traces will most assuredly be larger than
0.03 inch for most practical applications.

Therefore, it will be necessary to use controlled

impedance environments for EP devices in general and
devices with faster edges.

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TERMINATION OF ECL LOGIC DEVICES

SECTION 2. PARALLEL TERMINATION - EXTERNAL AND INTERNAL

External

Internal

Near (Standard Pair)

Far (Standard Pair)

Near (Standard Pair)

Far (Standard Pair)

Vt1

Vt2

Vt1

Vt2

(Open)

(Shorted)

Parallel termination advantages:

Method of choice for best circuit performance

Particularly excellent for driving distributed loads

Undistorted waveform along the full length of the line

Decreased power consumption.

Far DC Current Return - V

A parallel terminated line is one in which the receiving end

is signal terminated internally or externally (usually to a
voltage V

) through a resistor (R

) with a value equal to the

line characteristic impedance (Figure 4). This line also carries
the biasing current for the drivers output far from the driver.
Output current and power dissipation is decreased due to use

of a V

termination supply. The V

supply must sustain the

emitter follower output transistor in its active operating region
under all operating conditions. A minimum continuous current
occurs for the most negative V

, therefore the V

supply

must remain more negative than the worst case V

OLmin

and

always sink current.

Standard V

is 2.0 V below V

supply. A parallel

resistor, R

, matching the controlled impedance transmission

line, Z

, connects the signal to the V

supply. The Parallel

Termination to V

is shown in Figure 4. The termination

resistors may be internal or external and either ganged into a
Combo pin or offered as Singulated pins. Some devices may
have each internal resistors independently pinned out,
allowing further termination versatility.

Figure 4. Parallel Termination to V

- Differential and Single-Ended with Combo or Singulated Vt Pins (Far Return)

= Z

-2.0 V

T-Line Z

(*or twisted pair)

Driver

Receiver

*T-Line Z

(*or twisted pair)

Driver

Receiver

*T-Line Z

Driver

Receiver

External (Far, Diff.)

Internal Termination Combo Pin (Far, Diff.)

(*or twisted pair)

Driver

Receiver

*T-Line Z

Vt1

Internal Termination Singulated Pins (Far, Diff.)

Vt2

External (Far, S.E.)

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Internal Termination Resistors

Internal termination conveniently uses 50

W values for R

with the most popular being Z

. Note the internal termination

allows the Combo Pin node, V

, from the internal resistors to

be connected to an external V

supply, typically at

- 2.0 V, as shown in Figure 5. Alternatively, this Combo

Pin may be pulled to V

through an external resistor to form

a "Y" type termination variant, as shown in Figure 5. See the
"Y Variance" topic and the "Y Term Table" for R

resistor

values.

Figure 5. Combo Pin V

or "Y" Connection with

Internal Parallel Termination

(*or twisted pair)

Driver

Receiver

*T-Line Z

Connection

(*or twisted pair)

Driver

Receiver

*T-Line Z

Y Connection

Example Calculations

Ideally, V

supply tracks 1:1 with V

; however, supply

tolerances need to be considered. Assume for instance a
MC10EP16, +85

C, nominal +3.3 V

, terminated 50

W (R

)

to V

, where V

is V

- 2.0 V, or 1.3 V:

IOHmax of (VCC )

0.885 V

IOLmin of (VCC )

1.685 V

resulting in the nominal case:

IOHmax

(VOHmax

VTT )

(3.3

0.885)

1.3

22.3 mA

IOLmin

(VOLmin

VTT )

(3.3

1.685)

1.3

6.3 mA

If +5% tolerances are assumed, two worst case conditions result.

Case #1: V

min = V

- 5%, V

max = V

+ 5%

((3.135

0.885)

1.365)

17.7 mA

IOHmax

(VOHmax

VTT)

IOLmin

(VOLmin

VTT)

((3.135

1.685)

1.365)

1.7 mA

Case #2: V

CCmin

+ 5%, V

TTmax

- 5%

((3.465

0.885)

1.235)

26.9 mA

IOHmax

(VOHmax

VTT)

((3.465

1.685)

1.235)

1.09 mA

IOLmin

(VOLmin

VTT)

Y Variance

The "Y" termination for a differential pair may be

preferred when avoiding the use of a V

supply. The design

is shown in Figure 6 and utilizes the following formulas for
calculating resistor values which are found in the Y Term
Table. The voltage at the Node where R

, R

, and R

connect remains at a static V

voltage of V

- 2.0 V, or

1.3 V.

Rt3

Rt1

VTT

VEE

VOH

)

VOL

2VTT

Rt1

Rt2

(eq. 10)

(eq. 11)

VTT

Rt3 ( VOH

)

VOL )

)

( Rt1 * VEE )

Rt1

)

2Rt3

(eq. 12)

Figure 6. "Y" Variance

Driver

Receiver

*T-Line Z

* or Twisted Pair

0.1-0.01

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Table C. Y Term Table

-V

| = 5.0 V

-V

| = 3.3 V

-V

| = 2.5 V

112

21.2

156

29.7

166

31.8

179

33.9

201

38.1

100

223

100

42.4

120

268

120

109

120

50.8

150

335

150

136

150

63.6

Figure 7. Standard Pair with External Parallel

(*or twisted pair)

*T-Line Z

Near DC Current Return - Standard Pair
Termination

The standard pair termination scheme uses a pull-down

resistor, R

, located at each driver pin to return the output

transistor bias current near the driver, and an impedance
matching parallel resistor, R

, located at the receiver input

pins (see Figure 7, standard pair with external parallel, and
Figure

8, standard pair termination with internal

termination, and Figure 9, standard pair termination with
singulated internal termination resistors). The impedance
matching parallel resistor may be internal or external
depending on the receiver device. If internal to the receiver,
the resistor may be singulated or combined ("combo") for
external pinout.

The diagram of Figure 7 shows a Standard Pair

Termination with an R

resistor for DC output current bias

located nearby each driver pin: refer to Table B, for values
of R

. The differential transmission line AC impedance

matching resistance, R

, is located externally near the

receiver input pins.

As a variation of a Standard Pair Termination, a receiver

may provide the differential transmission line AC
impedance matching resistance, R

, internally. This internal

impedance matching termination may be pinned out either
combined into a Combo V

pin or each resistor may be

singulated and pinned out, such as V

and V

When left open, the Combo Pin still provides a passive

100

W termination across the nearby receiver's differential

signal line pair. This can compliment a pull-down resistor, R

located on each line of a differential at the driver pins. This is
illustrated in Figure 8.

Figure 8. Standard Pair Termination with

Internal Termination

Open V

(*or twisted pair)

Driver

Receiver

*T-Line Z

Internal Termination Combo Pin

When the Internal Termination resistors are singulated,

the two V

pins must be shorted to create the 100

W value as

shown in Figure 9.

Figure 9. Standard Pair Termination with

Singulated Internal Termination Resistors

Internal Termination Singulated Pins

(*or twisted pair)

Driver

Receiver

*T-Line Z

Vt1

Vt2

Shorted

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Internal 100

Termination (LVDS)

For some technologies, such as LVDS, this passive 100

internal termination can provide sufficient termination for the
driver as shown in Figure 10. Devices with a Combo Pin will
require this pin to remain open, while devices with singulated
internal resistors require the two pinned out V

nodes for a

differential pair to be shorted together to provide the 100

termination.

Figure 10. LVDS Interconnect with Internal

Termination

Open V

(*or twisted pair)

LVDS Driver

Receiver

*T-Line Z

Internal Termination Combo Pin

Internal Termination Singulated Pins

(*or twisted pair)

LVDS Driver

Receiver

*T-Line Z

Vt1

Vt2

Shorted

Differential ECL outputs can be terminated as independent

complimentary single-ended lines. Both sides of any
differential pair must be terminated as identically as possible
to minimize phase error and pulse width duty cycle skew.

The I

currents in these two cases will vary the DC V

levels by

$40 mV. However in the vast majority of cases, DC

levels are well centered in their specification windows, thus

this variation will simply move the level within the valid
specification window and no loss of worst case noise margin
will be seen.

The I

situation on the other hand does pose a potential

AC problem. In the worst Case #1 I

OLmin

situation, the

output emitter follower could move into the cutoff state
(0 mA). The output emitter followers of ECL devices are
designed to be in the conducting, active region of operation
at all times. When forced into cutoff, the delay of the device
will be increased due to the extra time required to pull the
output emitter follower out of the cutoff state. Again, this
situation will arise only under a number of simultaneous
worst case situations and therefore, is highly unlikely to
occur. But, because of the potential, it should not be
overlooked.

Output Drive Characteristics

Figure 11 shows the nominal output characteristics for

ECL devices operating in negative ECL mode, driving
various load impedances (including the standard 50

returned to a negative two volt supply. The output
resistances, RH (high state output resistance) and RL (low
state output resistance), are obtained from the reciprocal of
the slope at the desired operating point. Many applications
require loads other than 50

W - the resulting V

and V

levels can be estimated using the following technique.

-2.0

-5

-10

-15

-0.75

-1.0

-1.25

-20

-25

-30

-35

-40

-1.75

-0.5 -0.25

OUTPUT VOLTAGE (V)

OUTPUT CURRENT (mA)

SLOPE = 6

- 8

-1.5

Figure 11. Normal Output Levels Driving Various

Load Impedances

=25

to - 2.0 V

150

to - 2.0 V

100

to - 2.0 V

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SECTION 3. THEVENIN EQUIVALENT PARALLEL TERMINATION

Although the single resistor termination to V

conserves

power, it requires an additional supply voltage. An alternate
approach to using a V

power supply is to use a resistor

divider network as shown in Figure 12 to develop a
Thevenin voltage, V

, and provide a parallel impedance

matching AC termination, the Thevenin parallel
termination.

Figure 12. Thevenin Equivalent Parallel Termination

T-Line Z

Driver

Receiver

Driver

Receiver

T-Line Z

or Twisted Pair

VTT

VCC

2.0V

VCC

)

*
*

(eq. 13)

Differential ECL outputs can be terminated as independent

complimentary single-ended lines. Both sides of a
differential pair must be terminated. Balanced, symmetrical
loading of each line must be preserved.

While a Thevenin Parallel technique dissipates more

termination power, it does not require the additional V

supply. This additional power is consumed entirely in the
external resistor divider network and thus will not change
the current being sourced by the device, hence it does not
alter the IC reliability or lifetime. As with standard parallel
termination, variance of V

and V

supplies must be

considered.

The Thevenin equivalent of the two resistors needs to be

equal to the characteristic impedance of the signal
transmission line. Calculated values for resistors R1 and R2
may be obtained from the following relationships.

VCC

VEE

VCC

VTT

(eq. 14)

VCC

VTT

VEE

(eq. 15)

Where:

= V

- 2.0 V

= Characteristic Impedance of the Signal

Transmission Line

For a typical V

= 5.0 V PECL scheme, where V

GND, V

= 3.0 V, and Z

= 50

125

(eq. 16)

125

83.3

(eq. 17)

and cross-checking for V

VTT

125

)

83.3

3.0 V

(eq. 18)

VTT

VCC

2.0 V

3.0 V

(eq. 19)

For the typical V

= 3.3 V LVPECL scheme, where

= GND, V

= 1.3 V, and Z

= 50

3.3

1.3

82.5

(eq. 20)

82.5

3.3

1.3

126

(eq. 21)

and cross-checking for V

VTT

3.3

82.5

126

)

82.5

1.3 V

(eq. 22)

VTT

VCC

2.0 V

1.3 V

(eq. 23)

Table D. Thevenin Term Table

-V

| = 5.0 V

-V

| = 3.3 V

-V

| = 2.5 V

125

127

250

62.5

117

175

178

115

350

87.5

125

188

190

123

375

93.8

133

200

203

132

400

100

150

225

229

149

450

112.5

100

167

250

100

253

165

100

500

125.5

120

200

300

120

305

198

120

600

150

250

375

150

381

248

150

750

187.5

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Because the resistor divider network of R1 and R2 is used

to generate V

, the variation in V

will be intimately tied

to the variation in V

. Differentiating the equation for V

with respect to V

yields:

VTT

VCC

( R1

)

R2 )

VCC

(eq. 24)

For the nominal case, this equation reduces to:

VTT

0.6

VCC

(eq. 25)

$5% = $0.25 V, then DV

$0.15 V.

As mentioned previously, the real potential for problems

will be if the V

level can potentially put the output emitter

follower out of the active operating region and into cutoff.
Because of the relationship between the V

and V

levels,

the only cutoff risk condition occurs at V

CCmin

, the lowest

value of V

. Applying the equation for I

OLmin

under this

-5% V

condition yields:

IOLmin

( VOLmin

VTT )

(eq. 26)

IOLmin

(4.75

1.85)

2.85

1.0 mA

(eq. 27)

The results of this cutoff risk analysis show there is no

potential for the output emitter follower to be in cutoff. This
would indicate a Thevenin equivalent termination scheme is
more robust to variation in V

. Since the designer has the

flexibility of choosing the V

level via the selection of the

R1 and R2 resistors, the following procedure can be used.

At -5% minimal variation case for V

= 4.75 V

= V

- 2.0 V = 2.75 V

R2 = 119

R1 = 86

Thus:

OHmax

= 23 mA

OLmin

= 3.0 mA

At +5% minimal variation case for V

= 5.25 V

= 3.05 V

Thus:

OHmax

= 28 mA

OLmin

= 5.2 mA

Although the output currents are slightly higher than

nominal, the elimination of emitter follower cutoff risk is
well justified.

When the equivalent termination resistance matches the

line impedance, no reflection occurs because all the energy
in the signal is dissipated by the termination. Hence, in
comparing properly terminated schemes parallel and
Thevenin, a primary consideration is the power supply
requirements. As mentioned earlier, the parallel V

scheme

requires an extra power supply; however, the Thevenin
termination dissipates 10 times more DC power.
Fortunately, this extra power dissipation cannot be seen on
the die; therefore, either technique results in similar die
junction temperatures.

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SECTION 4. SERIES TERMINATION

Series Damping is a technique in which a termination

resistance is placed between the driver and the transmission
line with no termination resistance placed at the receiving
end of the line (Figure 13).

*T-Line Z

Driver

* Optional

Receiver

Driver

* Optional

Receiver

Figure 13. Series Termination

or Twisted Pair

Differential ECL outputs can be terminated as

independent complimentary single-ended lines. Both sides
of any differential pair must be terminated as identically as
possible to minimize phase error and pulse width duty cycle
skew.

Series Termination is a special case of series damping in

which the sum of the termination resistor (R

) and the output

impedance of the Driver gate (R

) is equal to the line

characteristic impedance (Figure 14).

)

(eq. 28)

Where:

= Series Termination Resistor

= Output Impedance

= Line Characteristic Impedance

*T-Line Z

Receiver

Figure 14. Series Termination

Driver

Series termination techniques are useful when the

interconnect lengths are long or impedance discontinuities
exist on the line. Additionally, the signal travels down the
line at half amplitude minimizing problems associated with
crosstalk. Unfortunately, a drawback with this technique is
the possibility of a two-step signal appearing when the
driven inputs are far from the end of the transmission line.
To avoid this problem, the distance between the end of the
transmission line and input gates should adhere to the
guidelines specified from the section on unterminated lines.

Series Termination Theory

When the output of the series terminated driver gate

switches levels, this driver output voltage change,

, is

impressed on the input to the transmission line (Point A) as
a change in voltage (

) and propagates to the Receiver at

the output of the transmission line (Point B) as a change in
voltage (

) in Figure 14.

+ D

VO *

)

(eq. 29)

Where:

= Input to the Transmission Line Voltage

Change

= Receiver Input Voltage Change

= Driver Output Voltage Change

= Line Characteristic Impedance

= Output Impedance of the Driver Gate

= Termination Resistance

Since Z

= R

+ R

, substitution into the above equations

yields:

(eq. 30)

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From this relationship,

/ 2, an incident wave

of half amplitude propagates down the transmission line. At
the Receivers input Point B, typically high impedance, the
transmission line sees an unterminated open line and the
signal reflection coefficient at the Receiver load is
approximately unity. The reflection causes the voltage to
double at the receiving end. When the reflected wave arrives
back at the source end, its energy is dissipated by the series
resistor. When the sum of the source and series impedance
is equal to the characteristic impedance of the line, no further
reflections occur.

Calculation of R

The Emitter Pull-Down Resistor, R

, functions to

establish V

and V

levels. Voltage transitions imposed

on R

propagate through R

and Z

to a receiver. Negative

voltage transition are current limited by R

, R

, and Z

when

the driver output switches to the low state. The R

value must

maximize the negative voltage transition and prevent the
output transistor from entering the cutoff operating region in
a low state (Figure 15).

*T-Line Z

Receiver

Figure 15. Equivalent Circuit for RE Determination

Driver

The worst case scenario occurs when the driver output

emitter follower enters into cutoff during a negative going
transition. When this happens, the driver can be considered
opened and, at the instant it opens, the line characteristic
impedance behaves as a linear resistor returned to V

. The

model becomes a simple series resistive network as shown
in Figure 16.

*T-Line Z

Figure 16. Equivalent Circuit with Output Cutoff

The maximum current, I

max

, occurs at the instant the

switch opens and is calculated by:

I max

( VOH

VEE )

( Rt

)

Z0 )

(eq. 31)

An initial current, I

init

must be sufficient to generate a

transient voltage equal to half of the logic swing since the
voltage at the receiver will double due the reflection
coefficient approaching 1.0 for series termination. To
accommodate reflections caused by discontinuities and load
capacitances the transient voltage should be increased by
25%. Thus, I

init

is defined as:

Iinit

1.25 *

Vpp

(eq. 32)

To satisfy the initial constraints of I

max

> I

init

( VOH

VEE )

( Rt

)

Z0 )

1.25 *

VSWING

(eq. 33)

Solving for R

, gives the inequality:

( KZ0 ) Z0

(eq. 34)

Where:

= Line Characteristic Impedance

= Output Impedance of the Driver Gate

= Termination Resistance

= Coefficient to Z

For various series, the coefficient to Z

, KZ

, is presented

in Table E: Coefficient to Z

Table E. Coefficient to Z

Series

10EP

4.0

100LVEL

4.01

10EL

5.99

10E

7.10

100E

6.57

For the 10EP series (LVPECL mode operation),
where V

= 2.4 V, V

SWING

= 0.8 V, and V

= 0.0 V:

(2.4

0.0)

(Rt

)

Z0)

0.5

* Z0

4.0

(eq. 35)

For the 100LVEL series (LVPECL mode operation),
where: V

= 2.345 V, V

SWING

= 0.750 V, V

= 0.0 V:

(2.345

0.0)

(Rt

)

Z0)

0.468

* Z0

4.01

(eq. 36)

For the 10EL series (PECL mode operation),
where: V

= 4.185 V, V

SWING

= 0.958 V, V

= 0.0 V:

(4.185

0.0)

(Rt

)

Z0)

0.599

* Z0

5.99

(eq. 37)

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For the 10E series (ECL mode operation),
where: V

= -0.9 V, V

SWING

= 0.85 V, V

= -5.2 V:

(

0.9)

(

5.2)

)

0.531

* Z0

7.10

(eq. 38)

For the 100E series (ECL mode operation),
where: V

= -0.955 V, V

SWING

= 0.75 V, V

= -4.5 V:

(

0.955)

(

4.5)

)

0.468

* Z0

6.57

(eq. 39)

Parallel Fanout of Series Termination

An extension of the series termination technique, using

parallel fanout, eliminates the problem of lumped loading at
the expense of extra transmission lines (Figure 17).

*T-Line Z

Receiver

Figure 17. Parallel Fanout Using Series Termination

*T-Line Z

Receiver 1

Driver

N number of lines

Figure 17 shows a modification of the series termination

scheme in which several series terminated lines in parallel
fanout are driven using a single ECL gate. The principle
concern when applying this technique is to maintain the
current in the output emitter follower below the maximum
rated value. The value for R

can be calculated by viewing

the circuit in terms of conductances.

Goutput

)

(eq. 40)

From Table B, for each of the series:

( Rt )

(

* Z01

RS1)

)

(

* Z02

RS2)

)

(

* Z0

RS)

(eq. 41)

Where:

n = Number of Parallel Circuits

When:

Z01

Z02

Z0 , and RS1

RS2

(eq. 42)

Then R

is calculated as:

(KZ0 * Z0

Rs)

(eq. 43)

When a single series terminated line is driving more than

a single receiver, the maximum number of loads must be
addressed. The factor limiting the number of loads is the DC
voltage drop across the series termination resistor caused by
the summary input currents I

during the receivers quiescent

high state. Noise margin loss, NM

loss

, will probably

determine the acceptable DC voltage drop limit across R

NMloss

IT * ( Rs

RO )

(eq. 44)

Where:

= Sum of IINH Currents

= Output Impedance of the Driver Gate

= Termination Resistance

Figure 18. Noise Margin Loss Example

*T-Line Z

Receiver 1

Driver

Receiver 2

Receiver

For the majority of ECL devices typical maximum value

for quiescent high state input current is 150 uA. Thus, for the
circuit shown in Figure 18, in which three gate loads are
present in a 50

W environment, the loss in high state noise

margin is calculated as:

NMloss

3 *

150 mA * 50

W + *

22.5 mV

(eq. 45)

This represents a potential shift in the V

level of

-22.5 mV.

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SECTION 5. DIODE TERMINATION

Driver

Receiver

*All Media

Alternative to the resistor network termination schemes,

a Diode method shown in Figure 19 may afford certain
advantages when a design has the following constraints.

1. Impedance controlled media line is not required

(coax, twisted pair, striplines, etc.)

2. Impedance matched termination network is not

required.

3. Overshoot and Noise need to be clamped to logic

HIGH/LOW levels.

Figure 19. Diode Termination

Driver

Receiver

*All Media

Driver

Receiver

*All Media

D1 and D2 diodes may be an MBD301, MMBD301,

MBD701, MMBD701LT1, or a dual package MMBD452LT1.
Diode forward voltage curves from a data sheet, such as shown
in Figure 20, will determine specific current and voltage
operation range. Frequency limitations may be a consideration
when selecting the diodes. The Silicon Hot-Carrier Schottky
Barrier diode MBD701, for example, displays a forward V

about 0.55 V and an I

of about 11 mA (at 25

C) to match a

W impedance line. At higher temperatures, the current

decreases.

Figure 20. MMBD701 Diode Forward Voltage

0.1

1.0

100

0.2

0.4

0.8

1.2

1.6

2.0

, FOR

ARD CURRENT (mA)

, FORWARD VOLTAGE (V)

= 85

=-40

= 25

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SECTION 6. CAPACITIVE COUPLING

Although not strictly a termination, AC or capacitive

coupling is often used to provide features in conjunction
with proper termination. Such capabilities as hot swapping
capability, DC isolation to a receiver, and level shifting are
possible with capacitive coupling.

Data stream characteristics may impose restriction on

both termination and capacitive coupling. AC coupled
signals have the line DC blocked and will require a DC
restoration voltage, V

BIAS

, for the receiver input. Data in

unencoded Non-Return-to-Zero (NRZ) format will require
DC restoration prior to AC coupling into a ECL receiver
input.

A sinusoidal waveform clock signal may be cap coupled

for conversion to a square wave with 50% duty cycle and
sharp rise and fall edges.

The capacitor used to couple the signal must have a

impedance rating of < 50

W over the frequency range of the

input signal. Because large capacitors appear somewhat
inductive at high frequencies, it may be necessary to use a
small capacitor in parallel with a larger one to achieve
satisfactory operation.

A coupling capacitor and the signal load impedance form

an RC network which will boundary the duration of a pulse.
Values for the R (load and leakage total resistance) and C
(coupling capacitor) should be selected to provide a time
constant, T

, of at least 10x the pulse width. Data streams

may require larger T

values to retain logic levels.

Hot Swapping

The desire often arises to remove or install a receiver or

daughter card without powering down the driver or
motherboard. This is termed "Hot Swapping".

Powered Driver and an Unpowered Receiver
Damage Risk

Hot swapping presents a potential risk to an unpowered or

powered down ECL device receiver and driver in either the
Negative or Positive mode when driven by a typical signal
level.

When a receiver PECL receiver V

is off or powered

down, the V

Power Supply typically appears as a low

impedance source at 0.0 V capable of sinking considerable

current. Typical driver signal levels present voltages that
forward bias the input ESD protection diode structure and
the input base collector junction. Potentially lethal current
paths may develop through forwarded junctions to V

There is also a risk for a powered down or off NECL or

LVNECL receiver and driver. A V

supply will typically

appear as a low impedance path to 0.0 V (GND). Typical
negative levels present signal voltages that will forward bias
the input ESD protection diode structure and the input base
collector junction to this low impedance path. Potentially
lethal current paths may develop through the forwarded
junctions and V

to 0.0 V.

Powered down receiver risk may be managed in several

ways.

1. Physical Sequencing - the supplies for V

(Ground) and V

(Power) may be physically

connected prior to signal lines by altering the
daughter board edge connection geometry, making
V

and V

connectors protrude and engage or

sequence first. V

connectors could even be

sequenced prior to V

This insures the supplies

are powered prior to input signal voltages.

2. Switching - a relay (or analog switch) could be

used to open or close the supply lines insuring the
power supply line is opened when powered off.

3. Cap Coupling - DC isolation of potentially

damaging current.

4. Series R - an additional series impedance matching

resistor, R

, will act as power splitter with an

existing parallel termination resistor, R

, to

accomplish some current limiting to help manage
the risk. This will also attenuate the amplitude
50%, easily tolerated by most high gain, high input
sensitivity devices.

Using V

Pin for V

BIAS

Some devices provide a convenient V

pin for use as a

VBIAS reference supply to rebias a DC level. A DC rebias
level must be at the common mode voltage of the input
signal to properly preserve a 50% output duty cycle (see
AND8066). A package V

pin may provide an internally

generated DC switching reference voltage for the device
inputs, and is available only to the package input pins. Do not
port one package V

pin directly to another device without

current amplification. When used, decouple V

to V

(or

) via a 0.01 to 0.001

mF capacitor to suppress noise

injection. Limit current to less than 0.5 mA (Absolute
Maximum Rating source or sink) as shown in Figure 21.
When not used, V

should be left open.

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Figure 21. Differential and Single-Ended AC

Configurations Using V

Reference

Rpu 25 k

to 100 k

Receiver

OUT

INb

1 k

* 0.001

0.001

Rpu 25 k

to 100 k

Receiver

OUT

1 k

* 0.001

0.01 - 0.001

* High Voltage Cap May Be Needed

0.01 - 0.001

A. Differential

B. Single-Ended

In Figure 21A, the IN line has a 1 k

W resistor to V

presenting a 1 K

W impedance across the differential signal

lines. This assumes the signal impedance matching has been
accomplished prior to the cap coupling, on the driver side of
cap. Locate the coupling capacitor as physically close to the
input pin as possible to minimize the trace length and
diminish potential reflections due to the impedance
mismatch.

If signal impedance matching has not been accomplished

prior to the cap coupling, then a characteristic impedance
resistor, 2Z

, would be used across the input lines, on the

receiver side of the cap. The value of the Rpu resistor would
be adjusted to produce an acceptable null signal default
voltage drop.

Auto-Oscillation Suppression with V

If the differential inputs to the AC coupled device are left

open or if the driving signals are lost, both receiver input pin
voltages converge toward the VBIAS reference voltage V

value. Sustained oscillation may autonomously result from
a combination of ambient environmental noise, the device

small signal gain, and feedback from the output to the input
through parasitic capacitive and inductive paths.

As a differential receiver input voltage diverges, the

output responds by transitioning toward a state voltage. A
sufficient voltage

D across the receiver inputs will force the

output to state level. Depending on conditions, about 10 to
50 mV is sufficient to suppress instability oscillation and
force a determined state on the output.

For the configuration using the V

reference, Figure 21,

this input voltage

D may be accomplished by injecting a

minimum current from V

through an external pullup

resistor, Rpu, on ONE input line. The value of Rpu could
range from 25 k

W to 100 kW. As Rpu increases, the phase

error is diminished and the susceptibility to oscillation
increases.

Generally, an internal pull-down resistor ranging in value

from 52 k

W to 75 kW is deployed on an input pin. On some

D-bar (Invert) input pins an additional 36 k

W to 75 kW

resistor is deployed to suppress oscillation by forcing a
determined state on the output under open input or null
voltage conditions. A minimum input voltage

D of 20 to

30 mV may be effective depending on noise, gain, and
layout.

Generating V

for VBIAS

When V

voltages are desired, but not available within

a device, the reference level may be ported from a generator
as illustrated in Figure 22. Any of the "16" type buffers are
recommended for use in a high current gain V

Generator

buffer. For example, the E416, EL16, LVEL16, EP16,
LVEP16, EL17, LVEL17, etc. type devices have a V

available for constructing a V

Generator buffer.

Figure 22. V

Voltage Reference Generator

BB(out)

or V

0.01

1 K

Non-V

Biasing

Alternative to a device supplied V

, any voltage source

may be supplied to bias receiver inputs to provide an
acceptable V

IHCMR

(Voltage Input HIGH Common Mode

Range) DC reference to the receiver (see specific device data
sheet). Signal impedance matching may be accomplished
prior to cap coupling, allowing a wide range values for a
rebiasing resistor network.

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When the coupling capacitor is physically located near

enough to the receiver input pins to prohibit reflections on the
connecting trace length or signal impedance matching has
been accomplished prior to cap coupling, then a simple high
value resistor divider network from V

to V

recommended as shown in Figure 23. Differential and

Single-Ended AC Configurations Using Non-V

Biasing

(A and B). This network total resistance may be from 1 K

to 10 K

W. For 50 W impedance traces, the typical value for the

voltage divider resistors are given in Table F. Typical Rebias
and Impedance Matching Resistor Network Values @
Z

= 50. Note the impedance presented to a signal is

u5 KW.

Table F. Typical Rebias and Impedance Matching Resistor Network Values @ Z

= 50

Resistor

-V

| = 5.0 V

-V

| = 3.3 V

-V

| = 2.5 V

Units

R1 (R1

)

R2 (R2

)

rebias

3.3

2.2

1.7

When the coupling capacitor is physically located at a

distance from receiver over a trace or cable length capable
of sustaining reflections, a Thevenin parallel network
matching the line of impedance is recommended for their
suppression. This is shown in Figure 23. Differential and
Single-Ended AC Configurations Using Non-V

Biasing

(A and B). The rebias voltage may always be safely set at
V

-1.3. For 50

W impedance traces, the typical value for

the voltage divider resistors are given in Table G. Typical
Rebias and Impedance Matching Resistor Network Values @
Z

= 50.

Table G. Typical Rebias and Impedance Matching Resistor Network Values @ Z

= 50

Resistor

-V

| = 5.0 V

-V

| = 3.3 V

-V

| = 2.5 V

Units

R1 (R1

)

96.15

R2 (R2

)

192

127

104.16

rebias

3.7

2.0

1.2

Figure 23. Differential and Single-Ended AC

Configurations Using Non-V

Biasing

Receiver

OUT

OUTb

INb

0.001

Receiver

OUT

OUTb

0.001

A. Differential

B. Single-Ended

The characterized V

reference voltage bias, VBIAS, is

- 1.33 V, but a device is not restricted to this VBIAS

value. The VBIAS range is determined by the Vpp
amplitude and the signal HIGH level, V

. Input HIGH

level, V

, is constrained by the data sheet specification of

common mode range, V

IHCMR

or V

CMR

. Thus, the VBIAS

range is constrained:

VBIAS max

VIHCMRmax

( 0.5 ) ( Vpp )

VBIAS min

VIHCMRmin

( 0.5 ) ( Vpp )

A single-ended source into a differential type input signal
amplitude swing, V

, is typically constrained from

ppmin

= 300 mV to V

ppmax

= 1000 mV.

An input signal must swing symmetrically above and

below VBIAS to preserve a 50% duty cycle out of the
receiver. Differential signals must have identical crosspoint
voltages to preserve minimum phase error and duty cycle
error. Crosspoint voltages are determined by the matched
precision of the resistor divider network from V

to V

Auto-Oscillation Suppression without V

For a configuration without a V

reference pin, such as

illustrated in Figure 23, the resistor network may be
modified to have an input voltage

D of 20 to 30 mV offset

between the input pins. Either a high resistor value divider
or a Thevenin parallel network may be modified to
accomplish this input voltage

D. This is accomplished by

altering the values of R1, R1

, R2, and R2

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Combining the high impedance and impedance matching

networks results in an input voltage scheme shown in
Figure 24. This creates the proper input voltage

D, VBIAS,

using fewer components.

Figure 24. VBIAS and Auto-Oscillation Suppression

with Thevenin Parallel Network

Receiver

OUT

OUTb

0.001

INb

0.001

For a 3.3 V V

, the values of R1 and R2 provide a

Thevenin parallel network divider voltage with V

in the

IHCMR

of the receiver. Current through the divider

develops the default offset across R

and can be adjusted as

needed. For example, in Z

= 50 traces, a 30 mV default

offset difference will be created if V

= 3.3 V and the DC

bias voltage is 2.0 V (typical V

) when:

4.22 k

6.34 k

100

The 0.001 coupling cap may need to be adjusted to

frequency and Vpp amplitude of the receiver input signal.

A similar single-ended network may be used with only

one coupling cap and sufficient bypass capacitance on the
non-driven resistor to preserve a DC level.

Output Level Shifting

Receiver inputs may be level shifted using capacitive

coupling and adjusting VBIAS within the acceptable
common mode range for V

. Output levels may also be

changed independent of input levels. The driver device may
be operated with both V

and V

at shifted values. This

is used at the factory to evaluate devices and conveniently
port signals directly into standard 50

W impedance

equipment modules. The V

is fixed to +2.0 V above Test

System chassis ground and the test equipment internal 50

impedance constitutes a proper signal termination. Thus, the
split V

supply is adjusted to a negative value.

- V

Split V

Unit

3.0

+2.0

-1.0

3.3

+2.0

-1.3

5.0

+2.0

-3.0

5.5

+2.0

-3.5

Output levels may be shifted to symmetrically cross 0.0 V

by a similar method although the advantage of conveniently
directly connecting into standard test equipment is no longer
available.

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
"Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
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