PIN CONNECTIONS
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
Low Noise, Low Drift
Single-Supply Operational Amplifiers
OP113/OP213/OP413
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
Analog Devices, Inc., 1998
FEATURES
Single- or Dual-Supply Operation
Low Noise: 4.7 nV/
Hz @ 1 kHz
Wide Bandwidth: 3.4 MHz
Low Offset Voltage: 100 V
Very Low Drift: 0.2 V/ C
Unity Gain Stable
No Phase Reversal
APPLICATIONS
Digital Scales
Multimedia
Strain Gages
Battery Powered Instrumentation
Temperature Transducer Amplifier
GENERAL DESCRIPTION
The OP113 family of single supply operational amplifiers fea-
tures both low noise and drift. It has been designed for sys-
tems with internal calibration. Often these processor-based
systems are capable of calibrating corrections for offset and
gain, but they cannot correct for temperature drifts and noise.
Optimized for these parameters, the OP113 family can be used
to take advantage of superior analog performance combined
with digital correction. Many systems using internal calibration
operate from unipolar supplies, usually either +5 volts or +12
volts. The OP113 family is designed to operate from single
supplies from +4 volts to +36 volts, and to maintain its low
noise and precision performance.
The OP113 family is unity gain stable and has a typical gain
bandwidth product of 3.4 MHz. Slew rate is in excess of 1 V/
s.
Noise density is a very low 4.7 nV/
Hz, and noise in the 0.1 Hz
to 10 Hz band is 120 nV p-p. Input offset voltage is guaranteed
and offset drift is guaranteed to be less than 0.8
V/
C. Input
common-mode range includes the negative supply and to within
1 volt of the positive supply over the full supply range. Phase
reversal protection is designed into the OP113 family for cases
where input voltage range is exceeded. Output voltage swings
also include the negative supply and go to within 1 volt of the
positive rail. The output is capable of sinking and sourcing
current throughout its range and is specified with 600
loads.
Digital scales and other strain gage applications benefit from the
very low noise and low drift of the OP113 family. Other appli-
cations include use as a buffer or amplifier for both A/D and
8-Lead Plastic DIP
8-Lead Narrow-Body SO
OP213
OUT A
IN A
+IN A
V
V+
OUT B
IN B
+IN B
1
5
8
4
OP213
OUT A
IN A
+IN A
V
1
2
3
4
8
7
6
5
V+
OUT B
IN B
+IN B
16-Lead Wide-Body SO
14-Lead Plastic DIP
1
2
3
4
5
6
7
14
13
12
11
10
9
8
OP413
OUT A
IN A
+IN A
V+
V
OUT B
IN B
+IN B
OUT D
IN D
+IN D
+IN C
IN C
OUT C
OUT C
OUT B
OP413
OUT A
IN A
+IN A
V+
IN B
+IN B
NC
V
OUT D
IN D
+IN D
+IN C
IN C
NC
NC = NO CONNECT
1
16
8
9
8-Lead Narrow-Body SO
OP113
OP113
NULL
IN A
+IN A
V
1
2
3
4
8
7
6
5
NC
V+
OUT A
NULL
NULL
IN A
+IN A
V
NC
V+
OUT A
NULL
NC = NO CONNECT
NC = NO CONNECT
1
5
8
4
8-Lead Plastic DIP
D/A sigma-delta converters. Often these converters have high
resolutions requiring the lowest noise amplifier to utilize their
full potential. Many of these converters operate in either single
supply or low supply voltage systems, and attaining the greater
signal swing possible increases system performance.
The OP113 family is specified for single +5 volt and dual
15
volt operation over the XIND--extended industrial (40
C to
+85
C) temperature range. They are available in plastic and
SOIC surface mount packages.
OP113/OP213/OP413SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
"E" Grade
"F" Grade
Parameter
Symbol
Conditions
Min
Typ
Max
Min
Typ
Max
Units
INPUT CHARACTERISTICS
Offset Voltage
V
OS
OP113
75
150
V
40
C
T
A
+85
C
125
225
V
OP213
100
250
V
40
C
T
A
+85
C
150
325
V
OP413
125
275
V
40
C
T
A
+85
C
175
350
V
Input Bias Current
I
B
V
CM
= 0 V,
240
600
600
nA
40
C
T
A
+85
C
700
700
nA
Input Offset Current
I
OS
V
CM
= 0 V
40
C
T
A
+85
C
50
50
nA
Input Voltage Range
V
CM
15
+14
15
+14
V
Common-Mode Rejection
CMR
15 V
V
CM
+14 V
100
116
96
dB
15 V
V
CM
+14 V,
40
C
T
A
+85
C
97
116
94
dB
Large Signal Voltage Gain
A
VO
OP113, OP213, R
L
= 600
,
40
C
T
A
+85
C
1
2.4
1
V/
V
OP413, R
L
= 1 k
,
40
C
T
A
+85
C
1
2.4
1
V/
V
R
L
= 2 k
,
40
C
T
A
+85
C
2
8
2
V/
V
Long-Term Offset Voltage
1
V
OS
Note 1
150
300
V
Offset Voltage Drift
V
OS
/
T
Note 2
0.2
0.8
1.5
V/
C
O
UTPUT CHARACTERISTICS
Output Voltage Swing High
V
OH
R
L
= 2 k
+14
+14
V
R
L
= 2 k
,
40
C
T
A
+85
C
+13.9
+13.9
V
Output Voltage Swing Low
V
OL
R
L
= 2 k
14.5
14.5
V
R
L
= 2 k
,
40
C
T
A
+85
C
14.5
14.5
V
Short Circuit Limit
I
SC
40
40
mA
POWER SUPPLY
Power Supply Rejection Ratio
PSRR
V
S
=
2 V to
18 V
103
120
100
dB
V
S
=
2 V to
18 V
40
C
T
A
+85
C
100
120
97
dB
Supply Current/Amplifier
I
SY
V
OUT
= 0 V, R
L
=
,
V
S
=
18 V
3
3
mA
40
C
T
A
+85
C
3.8
3.8
mA
Supply Voltage Range
V
S
+4
18
+4
18
V
AUDIO PERFORMANCE
THD + Noise
V
IN
= 3 V rms, R
L
= 2 k
f = 1 kHz,
0.0009
0.0009
%
Voltage Noise Density
e
n
f = 10 Hz
9
9
nV/
Hz
f = 1 kHz
4.7
4.7
nV/
Hz
Current Noise Density
i
n
f = 1 kHz
0.4
0.4
pA/
Hz
Voltage Noise
e
n
p-p
0.1 Hz to 10 Hz
120
120
nV p-p
DYNAMIC PERFORMANCE
Slew Rate
SR
R
L
= 2 k
0.8
1.2
0.8
1.2
V/
s
Gain Bandwidth Product
GBP
3.4
3.4
MHz
Channel Separation
V
OUT
= 10 V p-p
R
L
= 2 k
, f = 1 kHz
105
105
dB
Settling Time
t
S
to 0.01%, 0 V to 10 V Step
9
9
s
NOTES
1
Long-term offset voltage is guaranteed by a 1000-hour life test performed on three independent lots at 125
C, with an LTPD of 1.3.
2
Guaranteed specifications, based on characterization data.
Specifications subject to change without notice.
REV. C
(@ V
S
= 15.0 V, T
A
= +25 C unless otherwise noted)
2
OP113/OP213/OP413
REV. C
3
ELECTRICAL CHARACTERISTICS
"E" Grade
"F" Grade
Parameter
Symbol
Conditions
Min
Typ
Max
Min
Typ
Max
Units
INPUT CHARACTERISTICS
Offset Voltage
V
OS
OP113
125
175
V
40
C
T
A
+85
C
175
250
V
OP213
150
300
V
40
C
T
A
+85
C
225
375
V
OP413
175
325
V
40
C
T
A
+85
C
250
400
V
Input Bias Current
I
B
V
CM
= 0 V, V
OUT
= 2
300
650
650
nA
40
C
T
A
+85
C
750
750
nA
Input Offset Current
I
OS
V
CM
= 0 V, V
OUT
= 2
40
C
T
A
+85
C
50
50
nA
Input Voltage Range
V
CM
0
+4
+4
V
Common-Mode Rejection
CMR
0 V
V
CM
4 V
93
106
90
dB
0 V
V
CM
4 V,
40
C
T
A
+85
C
90
87
dB
Large Signal Voltage Gain
A
VO
OP113, OP213, R
L
= 600
, 2 k
0.01 V
V
OUT
3.9 V
2
2
V/
V
OP413, R
L
= 600, 2 k
,
0.01 V
V
OUT
3.9 V
1
1
V/
V
Long-Term Offset Voltage
1
V
OS
Note 1
200
350
V
Offset Voltage Drift
V
OS
/
T
Note 2
0.2
1.0
1.5
V/
C
O
UTPUT CHARACTERISTICS
Output Voltage Swing High
V
OH
R
L
= 600 k
4.0
4.0
V
R
L
= 100 k
, 40
C
T
A
+85
C
4.1
4.1
V
R
L
= 600
, 40
C
T
A
+85
C
3.9
3.9
V
Output Voltage Swing Low
V
OL
R
L
= 600
, 40
C
T
A
+85
C
8
8
mV
R
L
= 100 k
, 40
C
T
A
+85
C
8
8
mV
Short Circuit Limit
I
SC
30
30
mA
POWER SUPPLY
Supply Current
I
SY
V
OUT
= 2.0 V, No Load
1.6
2.7
2.7
mA
Supply Current
I
SY
40
C
T
A
+85
C
3.0
3.0
mA
AUDIO PERFORMANCE
THD + Noise
V
OUT
= 0 dBu, f = 1 kHz
0.001
0.001
%
Voltage Noise Density
e
n
f = 10 Hz
9
9
nV/
Hz
f = 1 kHz
4.7
4.7
nV/
Hz
Current Noise Density
i
n
f = 1 kHz
0.45
0.45
pA/
Hz
Voltage Noise
e
n
p-p
0.1 Hz to 10 Hz
120
120
nV p-p
DYNAMIC PERFORMANCE
Slew Rate
SR
R
L
= 2 k
0.6
0.9
0.6
V/
s
Gain Bandwidth Product
GBP
3.5
3.5
MHz
Settling Time
t
S
to 0.01%, 2 V Step
5.8
5.8
s
NOTES
1
Long-term offset voltage is guaranteed by a 1000 hour life test performed on three independent lots at 125
C, with an LTPD of 1.3.
2
Guaranteed specifications, based on characterization data.
Specifications subject to change without notice.
(@ V
S
= +5.0 V, T
A
= +25 C unless otherwise noted)
OP113/OP213/OP413
4
REV. C
ABSOLUTE MAXIMUM RATINGS
1
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18 V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18 V
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . .
10 V
Output Short-Circuit Duration to GND . . . . . . . . . . Indefinite
Storage Temperature Range
P, S Package . . . . . . . . . . . . . . . . . . . . . . . . 65
C to +150
C
Operating Temperature Range
OP113/OP213/OP413E, F . . . . . . . . . . . . . . 40
C to +85
C
Junction Temperature Range
P, S Package . . . . . . . . . . . . . . . . . . . . . . . . 65
C to +150
C
Lead Temperature Range (Soldering, 60 sec) . . . . . . . +300
C
Package Type
JA
2
JC
Units
8-Lead Plastic DIP (P)
103
43
C/W
8-Lead SOIC (S)
158
43
C/W
14-Lead Plastic DIP (P)
83
39
C/W
16-Lead SOIC (S)
92
27
C/W
NOTES
1
Absolute maximum ratings apply to both DICE and packaged parts, unless
otherwise noted.
2
JA
is specified for the worst case conditions, i.e.,
JA
is specified for device in socket
for cerdip, P-DIP, and LCC packages;
JA
is specified for device soldered in circuit
board for SOIC package.
ORDERING GUIDE
Temperature
Package
Package
Model
Range
Description
Options
OP113EP
40
C to +85
C
8-Lead Plastic DIP
N-8
OP113ES
40
C to +85
C
8-Lead SOIC
SO-8
OP113FP
40
C to +85
C
8-Lead Plastic DIP
N-8
OP113FS
40
C to +85
C
8-Lead SOIC
SO-8
OP213EP
40
C to +85
C
8-Lead Plastic DIP
N-8
OP213ES
40
C to +85
C
8-Lead SOIC
SO-8
OP213FP
40
C to +85
C
8-Lead Plastic DIP
N-8
OP213FS
40
C to +85
C
8-Lead SOIC
SO-8
OP413EP
40
C to +85
C
14-Lead Plastic DIP
N-14
OP413ES
40
C to +85
C
16-Lead Wide SOIC R-16
OP413FP
40
C to +85
C
14-Lead Plastic DIP
N-14
OP413FS
40
C to +85
C
16-Lead Wide SOIC R-16
OP113/OP213/OP413
REV. C
5
2 mV trim range may be somewhat excessive. Reducing the
trimming potentiometer to a 2 k
value will give a more reason-
able range of
400
V.
16
2
13
6
7
11 12
4
14
15
9
1
3
AD588BD
8
10
3
2
8
1
R5
1k
A2
2N2219A
+10.000V
+15V
15V
10 F
1/2
OP213
+10.000V
6
5
4
7
1/2
OP213
A1
R3
17.2k
0.1%
R4
500
CMRR TRIM
10-TURN
T.C. LESS THAN 50ppm/ C
OUTPUT
0
10V
F.S.
15V
350
LOAD
CELL
100mV
F.S.
R1
17.2k
0.1%
R2
301
0.1%
Figure 1. Precision Load Cell Scale Amplifier
APPLICATION CIRCUITS
A High Precision Industrial Load-Cell Scale Amplifier
The OP113 family makes an excellent amplifier for conditioning
a load-cell bridge. Its low noise greatly improves the signal reso-
lution, allowing the load cell to operate with a smaller output
range, thus reducing its nonlinearity. Figure 1 shows one half of
the OP113 family used to generate a very stable 10.000 V bridge
excitation voltage while the second amplifier provides a differen-
tial gain. R4 should be trimmed for maximum common-mode
rejection.
A Low Voltage Single Supply, Strain-Gage Amplifier
The true zero swing capability of the OP113 family allows the
amplifier in Figure 2 to amplify the strain-gage bridge accurately
even with no signal input while being powered by a single +5
volt supply. A stable 4.000 V bridge voltage is made possible by
the rail-to-rail OP295 amplifier, whose output can swing to
within a millivolt of either rail. This high voltage swing greatly
increases the bridge output signal without a corresponding in-
crease in bridge input.
3
2
8
1
2N2222A
2.500V
1/2
OP295
4
2
4
6
IN
OUT
GND
REF43
R8
12.0k
R7
20.0k
4.000V
350
35mV
F.S.
+5V
1/2
OP213
1
3
2
8
6
5
4
7
R4
100k
R3
20k
R6
27.4
R5
2.10k
R2
20k
R1
100k
1/2
OP295
R
G
= 2,127.4
+5V
OUTPUT
0V 3.5V
Figure 2. Single Supply Strain-Gage Amplifier
APPLICATIONS
The OP113, OP213 and OP413 form a new family of high
performance amplifiers that feature precision performance in
standard dual supply configurations and, more importantly,
maintain precision performance when a single power supply is
used. In addition to accurate dc specifications, it is the lowest
noise single supply amplifier available with only 4.7 nV/
Hz
typical noise density.
Single supply applications have special requirements due to the
generally reduced dynamic range of the output signal. Single
supply applications are often operated at voltages of +5 volts or
+12 volts, compared to dual supply applications with supplies of
12 volts or
15 volts. This results in reduced output swings.
Where a dual supply application may often have 20 volts of
signal output swing, single supply applications are limited to, at
most, the supply range and, more commonly, several volts be-
low the supply. In order to attain the greatest swing the single
supply output stage must swing closer to the supply rails than in
dual supply applications.
The OP113 family has a new patented output stage that allows
the output to swing closer to ground, or the negative supply,
than previous bipolar output stages. Previous op amps had
outputs that could swing to within about ten millivolts of the
negative supply in single supply applications. However, the
OP113 family combines both a bipolar and a CMOS device in
the output stage, enabling it to swing to within a few hundred
microvolts of ground.
When operating with reduced supply voltages, the input range is
also reduced. This reduction in signal range results in reduced
signal-to-noise ratio, for any given amplifier. There are only two
ways to improve this: increase the signal range or reduce the
noise. The OP113 family addresses both of these parameters.
Input signal range is from the negative supply to within one
volt of the positive supply over the full supply range. Com-
petitive parts have input ranges that are a half a volt to five
volts less than this. Noise has also been optimized in the OP113
family. At 4.7 nV/
Hz, it is less than one fourth that of competi-
tive devices.
Phase Reversal
The OP113 family is protected against phase reversal as long as
both of the inputs are within the supply ranges. However, if there
is a possibility of either input going below the negative supply
(or ground in the single supply case), the inputs should be pro-
tected with a series resistor to limit input current to 2 mA.
OP113 Offset Adjust
The OP113 has the facility for external offset adjustment, using
the industry standard arrangement. Pins 1 and 5 are used in
conjunction with a potentiometer of 10 k
total resistance,
connected with the wiper to V (or ground in single supply
applications). The total adjustment range is about
2 mV using
this configuration.
Adjusting the offset to zero has minimal effect on offset
drift (assuming the potentiometer has a tempco of less than
1000 ppm/
C). Adjustment away from zero, however, (like all
bipolar amplifiers) will result in a TCV
OS
of approximately
3.3
V/
C for every millivolt of induced offset.
It is therefore not generally recommended that this trim be used
to compensate for system errors originating outside of the
OP113. The initial offset of the OP113 is low enough that
external trimming is almost never required but, if necessary, the
OP113/OP213/OP413
6
REV. C
A High Accuracy Thermocouple Amplifier
Figure 4 shows a popular K-type thermocouple amplifier with
cold-junction compensation. Operating from a single +12 volt
supply, the OP113 family's low noise allows temperature mea-
surement to better than 0.02
C resolution from 0
C to 1000
C
range. The cold-junction error is corrected by using an inexpen-
sive silicon diode as a temperature measuring device. It should
be placed as close to the two terminating junctions as physically
possible. An aluminum block might serve well as an isothermal
system.
1/2
OP213
1
3
2
8
4
0V TO 10.00V
(0 C TO 1000 C)
+12V
0.1 F
+
10 F
R9
124k
R8
453
R5
40.2k
R1
10.7k
R2
2.74k
REF02EZ
0.1 F
+12V
2
6
4
+
+
D1
1N4148
R3
53.6
R4
5.62k
+5.000V
K-TYPE
THERMOCOUPLE
40.7 V/ C
R6
200
Figure 4. Accurate K-Type Thermocouple Amplifier
R6 should be adjusted for a zero-volt output with the thermo-
couple measuring tip immersed in a zero-degree ice bath. When
calibrating, be sure to adjust R6 initially to cause the output to
swing in the positive direction first. Then back off in the nega-
tive direction until the output just stops changing.
An Ultralow Noise, Single Supply Instrumentation Amplifier
Extremely low noise instrumentation amplifiers can be built
using the OP113 family. Such an amplifier that operates off a
single supply is shown in Figure 5. Resistors R1R5 should be
of high precision and low drift type to maximize CMRR perfor-
mance. Although the two inputs are capable of operating to zero
volt, the gain of 100 configuration will limit the amplifier input
common mode to not less than 0.33 V.
V
IN
+
*R1
10k
1/2
OP213
1/2
OP213
*R2
10k
*R3
10k
*R4
10k
V
OUT
+5V TO +36V
*R
G
(200 + 12.7 )
*ALL RESISTORS 0.1%, 25ppm/ C
GAIN = + 6
20k
R
G
Figure 5. Ultralow Noise, Single Supply Instrumentation
Amplifier
A High Accuracy Linearized RTD Thermometer Amplifier
Zero suppressing the bridge facilitates simple linearization of the
RTD by feeding back a small amount of the output signal to the
RTD (Resistor Temperature Device). In Figure 3 the left leg of
the bridge is servoed to a virtual ground voltage by amplifier
A1, while the right leg of the bridge is also servoed to zero-volt
by amplifier A2. This eliminates any error resulting from
common-mode voltage change in the amplifier. A three-wire
RTD is used to balance the wire resistance on both legs of the
bridge, thereby reducing temperature mismatch errors. The
5.000 V bridge excitation is derived from the extremely stable
AD588 reference device with 1.5 ppm/
C drift performance.
Linearization of the RTD is done by feeding a fraction of the
output voltage back to the RTD in the form of a current. With
just the right amount of positive feedback, the amplifier output
will be linearly proportional to the temperature of the RTD.
6
5
4
7
A2
R5
4.02k
R7
100
8
+15V
15V
1/2
OP213
R4
100
R2
8.25k
R
G
FULL SCALE ADJUST
R
W1
R1
8.25k
R3
50
R8
49.9k
R9
5k
LINEARITY
ADJUST
@1/2 F.S.
V
OUT
(10mV/ C)
1.50V = 150 C
+5.00V = +500 C
A1
3
2
1
R
W2
R
W3
1/2
OP213
100
RTD
6
4
13
11
12
7
9
8
10
16
2
14
15
1
3
+15V
15V
10 F
AD588BD
Figure 3. Ultraprecision RTD Amplifier
To calibrate the circuit, first immerse the RTD in a zero-degree
ice bath or substitute an exact 100
resistor in place of the
RTD. Adjust the ZERO ADJUST potentiometer for a 0.000 V
output, then set R9 LINEARITY ADJUST potentiometer to
the middle of its adjustment range. Substitute a 280.9
resistor
(equivalent to 500
C) in place of the RTD, and adjust the
FULL-SCALE ADJUST potentiometer for a full-scale voltage
of 5.000 V.
To calibrate out the nonlinearity, substitute a 194.07
resistor
(equivalent to 250
C) in place of the RTD, then adjust the
LINEARITY ADJUST potentiometer for a 2.500 V output.
Check and readjust the full-scale and half-scale as needed.
Once calibrated, the amplifier outputs a 10 mV/
C temperature
coefficient with an accuracy better than
0.5
C over an RTD
measurement range of 150
C to +500
C. Indeed the amplifier
can be calibrated to a higher temperature range, up to 850
C.
OP113/OP213/OP413
REV. C
7
Supply Splitter Circuit
The OP113 family has excellent frequency response characteris-
tic that makes it an ideal pseudo-ground reference generator as
shown in Figure 6. The OP113 family serves as a voltage fol-
lower buffer. In addition, it drives a large capacitor that serves
as a charge reservoir to minimize transient load changes, as well
as a low impedance output device at high frequencies. The
circuit easily supplies 25 mA load current with good settling
characteristics.
8
1
4
3
2
1/2 OP113
R3
2.5k
C1
0.1 F
R4
100
C2
1 F
R1
5k
R2
5k
V
S
+ = +5V +12V
V
S
+
2
OUTPUT
+
Figure 6. False Ground Generator
SoundPort is a registered trademark of Analog Devices, Inc.
Low Noise Voltage Reference
Few reference devices combine low noise and high output drive
capabilities. Figure 7 shows the OP113 family used as a two-
pole active filter that band limits the noise of the 2.500 V refer-
ence. Total noise measures 3
V p-p.
8
1
4
3
2
1/2 OP113
10 F
C2
10 F
+5V
+
OUTPUT
+2.500V
3 V p-p NOISE
+
10k
10k
6
2
+5V
IN
OUT
4
GND
REF43
Figure 7. Low Noise Voltage Reference
+5 V Only Stereo DAC for Multimedia
The OP113 family's low noise and single supply capability are
ideally suited for stereo DAC audio reproduction or sound
synthesis applications such as multimedia systems. Figure 8
shows an 18-bit stereo DAC output setup that is powered from a
single +5 volt supply. The low noise preserves the 18-bit dynamic
range of the AD1868. For DACs that operate on dual supplies,
the OP113 family can also be powered from the same supplies.
18-BIT
DAC
18-BIT
SERIAL
REG.
18-BIT
SERIAL
REG.
18-BIT
DAC
V
REF
V
REF
AGND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
L
LL
DL
CK
DR
LR
DGND
VBR
V
S
VOR
VOL
VBL
AD1868
8
1
1/2 OP213
LEFT
CHANNEL
OUTPUT
47k
220 F
+
100pF
7.68k
7.68k
1/2 OP213
7.68k
7.68k
330pF
9.76k
330pF
9.76k
6
5
7
100pF
RIGHT
CHANNEL
OUTPUT
47k
220 F
+
+5V SUPPLY
Figure 8. +5 V Only 18-Bit Stereo DAC
OP113/OP213/OP413
8
REV. C
Precision Voltage Comparator
With its PNP inputs and zero volt common-mode capability, the
OP113 family can make useful voltage comparators. There is
only a slight penalty in speed in comparison to IC comparators.
However, the significant advantage is its voltage accuracy. For
example, V
OS
can be a few hundred microvolts or less, combined
with CMRR and PSRR exceeding 100 dB, while operating on
5 V supply. Standard comparators like the 111/311 family oper-
ate on 5 volts, but not with common-mode at ground, nor with
offset below 3 mV. Indeed, no commercially available single
supply comparator has a V
OS
less than 200
V.
Figure 11 shows the OP113 family response to a 10 mV over-
drive signal when operating in open loop. The top trace shows
the output rising edge has a 15
s propagation delay, while the
bottom trace shows a 7
s delay on the output falling edge. This
ac response is quite acceptable in many applications.
+5V
100
25k
0V
2.5V
+2.5V
t
r =
t
f = 5ms
10mV OVERDRIVE
1/2
OP113
10
90
100
0%
2V
2V
5 s
Figure 11. Precision Comparator
The low noise and 250
V (maximum) offset voltage enhance
the overall dc accuracy of this type of comparator. Note that
zero crossing detectors and similar ground referred comparisons
can be implemented even if the input swings to 0.3 volts below
ground.
Low Voltage Headphone Amplifiers
Figure 9 shows a stereo headphone output amplifier for the
AD1849 16-bit SoundPort
Stereo Codec device. The pseudo-
reference voltage is derived from the common-mode voltage
generated internally by the AD1849, thus providing a conve-
nient bias for the headphone output amplifiers.
1/2
OP213
+5V
1/2
OP213
5k
OPTIONAL
GAIN
1k
V
REF
1/2
OP213
+5V
V
REF
OPTIONAL
GAIN
1k
5k
29
19
31
10k
LOUT1L
LOUT1R
CMOUT
AD1849
V
REF
10 F
10k
L VOLUME
CONTROL
R VOLUME
CONTROL
16
220 F
47k
HEADPHONE
LEFT
HEADPHONE
RIGHT
10 F
+
16
220 F
47k
+
Figure 9. Headphone Output Amplifier for Multimedia
Sound Codec
Low Noise Microphone Amplifier for Multimedia
The OP113 family is ideally suited as a low noise microphone
preamp for low voltage audio applications. Figure 10 shows a
gain of 100 stereo preamp for the AD1849 16-bit SoundPort
Stereo Codec chip. The common-mode output buffer serves as
a "phantom power" driver for the microphones.
+5V
1/2
OP213
10k
50
10 F
20
100
10k
+5V
1/2
OP213
20
50
10 F
10k
1/2
OP213
10k
100
15
17
MINL
MINR
CMOUT
AD1849
RIGHT
ELECTRET
CONDENSER
MIC
INPUT
LEFT
ELECTRET
CONDENSER
MIC
INPUT
19
Figure 10. Low Noise Stereo Microphone Amplifier for
Multimedia Sound Codec
SoundPort is a registered trademark of Analog Device, Inc.
OP113/OP213/OP413
REV. C
9
150
0
1.0
90
30
0.1
60
0
120
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
TCV
OS
V
UNITS
V
S
= 15V
40 C T
A
+85 C
400 OP AMPS
PLASTIC PKG
Figure 13a. OP113 Temperature Drift (TCV
OS
)
Distribution @
15 V
500
0
1.0
300
100
0.1
200
0
400
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
TCV
OS
V
UNITS
V
S
= 15V
40 C T
A
+85 C
896 (PLASTIC) OP AMPS
Figure 13b. OP213 Temperature Drift (TCV
OS
)
Distribution @
15 V
TCV
OS
V
UNITS
600
0
1.0
300
100
0.1
200
0
500
400
0.9
0.7
0.6
0.5
0.8
0.4
0.3
0.2
V
S
= 15V
40 C T
A
+85 C
1220 OP AMPS
PLASTIC PKG
Figure 13c. OP413 Temperature Drift (TCV
OS
)
Distribution @
15 V
100
0
50
60
20
40
40
50
80
40
30
20
10
0
10
20
30
INPUT OFFSET VOLTAGE, V
OS
V
UNITS
V
S
= 15V
T
A
= +25 C
400 OP AMPS
PLASTIC PKG
Figure 12a. OP113 Input Offset (V
OS
) Distribution
@
15 V
500
0
100
300
100
80
200
100
400
80
60
40
20
0
20
40
60
INPUT OFFSET VOLTAGE, V
OS
V
UNITS
V
S
= 15V
T
A
=
+25 C
896 (PLASTIC) OP AMPS
Figure 12b. OP213 Input Offset (V
OS
) Distribution
@
15 V
500
0
140
300
100
40
200
60
400
120
100
80
60
40
20
0
20
INPUT OFFSET VOLTAGE, V
OS
V
UNITS
V
S
= 15V
T
A
= +25 C
1220 OP AMPS
PLASTIC PKG
Figure 12c. OP413 Input Offset (V
OS
) Distribution
@
15 V
OP113/OP213/OP413
10
REV. C
500
0
125
300
100
50
200
400
100
75
50
25
0
25
TEMPERATURE C
INPUT BIAS CURRENT nA
75
V
S
= 15V
V
S
= +5.0V
Figure 17. OP213 Input Bias Current vs. Temperature
15.0
15.0
125
13.5
14.5
50
14.0
75
13.0
12.5
13.5
14.0
14.5
100
75
50
25
0
25
TEMPERATURE C
POSITIVE OUTPUT SWING Volts
V
S
= 15V
+SWING
R
L
= 2k
+SWING
R
L
= 600
SWING
R
L
= 600
SWING
R
L
= 2k
Figure 18. Output Swing vs. Temperature and R
L
@
15 V
20
0
125
6
2
50
4
12
8
10
14
16
18
100
75
50
25
0
25
TEMPERATURE C
OPEN-LOOP GAIN V/
V
75
V
S
= +5.0V
V
O
= 3.9V
R
L
= 2k
R
L
= 600
Figure 19. Open-Loop Gain vs. Temperature @ +5 V
1000
0
125
600
200
50
400
800
100
75
50
25
0
25
TEMPERATURE C
INPUT BIAS CURRENT nA
75
V
S
= 15V
V
CM
= 0V
V
S
= 5.0V
V
CM
= 2.5V
V
CM
= 0V
Figure 14. OP113 Input Bias Current vs. Temperature
5.0
3.0
125
4.5
3.5
50
4.0
75
100
50
25
0
25
TEMPERATURE C
POSITIVE OUTPUT SWING Volts
2.0
0
1.5
0.5
1.0
NEGATIVE OUTPUT SWING mV
75
+SWING
R
L
= 2k
+SWING
R
L
= 600
SWING
R
L
= 2k
SWING
R
L
= 600
V
S
= +5.0V
Figure 15. Output Swing vs. Temperature and R
L
@ +5 V
10
100
10M
1M
100k
10k
1k
FREQUENCY Hz
105
60
40
20
0
20
40
60
80
100
120
CHANNEL SEPARATION dB
V
S
= 15V
T
A
= +25 C
Figure 16. Channel Separation
OP113/OP213/OP413
REV. C
11
12.5
0
125
50
2.5
7.5
5.0
10.0
100
75
50
25
0
25
TEMPERATURE C
OPEN-LOOP GAIN V/
V
75
R
L
= 2k
R
L
= 1k
R
L
= 600
V
S
= 15V
V
D
= 10V
Figure 20. OP413 Open-Loop Gain vs. Temperature
100
40
20
10k
10M
1M
100k
1k
20
0
60
80
FREQUENCY Hz
OPEN-LOOP GAIN dB
90
225
135
180
45
0
PHASE Degrees
V+ = 5V
V = 0V
T
A
= +25 C
GAIN
PHASE
m = 57
Figure 21. Open-Loop Gain, Phase vs. Frequency @ +5 V
50
30
20
10k
10M
1M
100k
1k
40
10
20
10
0
FREQUENCY Hz
CLOSED-LOOP GAIN dB
A
V
= +100
A
V
= +10
A
V
= +1
V+ = 5V
V = 0V
T
A
= +25 C
Figure 22. Closed-Loop Gain vs. Frequency @ +5 V
10
0
125
3
1
50
2
6
4
5
7
8
9
100
75
50
25
0
25
TEMPERATURE C
OPEN LOOP GAIN V/
V
75
R
L
= 2k
R
L
= 600
V
S
= 15V
V
O
= 10V
Figure 23. OP213 Open-Loop Gain vs. Temperature
100
40
20
10k
10M
1M
100k
1k
20
0
60
80
FREQUENCY Hz
OPEN-LOOP GAIN dB
90
225
135
180
45
0
PHASE Degrees
T
A
= +25 C
V
S
= 15V
GAIN
PHASE
m = 72
Figure 24. Open-Loop Gain, Phase vs. Frequency @
15 V
50
30
20
10k
10M
1M
100k
1k
40
10
20
10
0
FREQUENCY Hz
CLOSED-LOOP GAIN dB
A
V
= +100
A
V
= +10
A
V
= +1
T
A
= +25 C
V
S
= 15V
Figure 25. Closed-Loop Gain vs. Frequency @
15 V
OP113/OP213/OP413
12
REV. C
70
50
125
65
55
50
60
75
100
50
25
0
25
TEMPERATURE C
PHASE MARGIN Degrees
5
1
4
2
3
GAIN-BANDWIDTH PRODUCT MHz
75
GBW
m
V+ = 5V
V = 0V
Figure 26. Gain Bandwidth Product and Phase Margin vs.
Temperature @ +5 V
30
15
0
1
10
1k
100
10
5
20
25
FREQUENCY Hz
VOLTAGE NOISE DENSITY nV/
Hz
T
A
= +25 C
V
S
= 15V
Figure 27. Voltage Noise Density vs. Frequency
140
100
0
1k
1M
100k
10k
100
120
60
80
20
40
FREQUENCY Hz
COMMON-MODE REJECTION dB
V+ = 5V
V = 0V
T
A
= +25 C
Figure 28. Common-Mode Rejection vs. Frequency @ +5 V
70
50
125
65
55
50
60
75
100
50
25
0
25
TEMPERATURE C
PHASE MARGIN Degrees
5
1
4
2
3
GAIN-BANDWIDTH PRODUCT MHz
75
m
V
S
= 15V
GBW
Figure 29. Gain Bandwidth Product and Phase Margin vs.
Temperature @
15 V
3.0
1.5
0
1
10
1k
100
1.0
0.5
2.0
2.5
FREQUENCY Hz
CURRENT NOISE DENSITY pA/
Hz
T
A
= +25 C
V
S
= 15V
Figure 30. Current Noise Density vs. Frequency
140
100
0
1k
1M
100k
10k
100
120
60
80
20
40
FREQUENCY Hz
COMMON-MODE REJECTION dB
T
A
= +25 C
V
S
= 15V
Figure 31. Common-Mode Rejection vs. Frequency
@
15 V
OP113/OP213/OP413
REV. C
13
140
100
0
1k
1M
100k
10k
100
120
60
80
20
40
FREQUENCY Hz
POWER SUPPLY REJECTION dB
T
A
= +25 C
V
S
= 15V
+PSRR
PSRR
Figure 32. Power Supply Rejection vs. Frequency
@
15 V
6
3
0
10k
10M
1M
100k
1k
2
1
4
5
FREQUENCY Hz
MAXIMUM OUTPUT SWING Volts
V
S
= +5V
R
L
= 2k
T
A
= +25 C
A
VCL
= +1
Figure 33. Maximum Output Swing vs. Frequency @ +5 V
50
0
500
15
5
100
10
0
30
20
25
35
40
45
400
300
200
LOAD CAPACITANCE pF
OVERSHOOT %
V
S
= +5V
R
L
= 2k
V
IN
= 100mV p-p
T
A
= +25 C
A
VCL
= +1
NEGATIVE
EDGE
POSITIVE
EDGE
Figure 34. Small Signal Overshoot vs. Load Capacitance
@ +5 V
40
20
0
1k
1M
100k
10k
100
10
30
FREQUENCY Hz
IMPEDANCE
T
A
= +25 C
V
S
= 15V
A
V
= +100
A
V
= +10
A
V
= +1
Figure 35. Closed-Loop Output Impedance vs. Frequency
@
15 V
30
15
0
10k
10M
1M
100k
1k
10
5
20
25
FREQUENCY Hz
MAXIMUM OUTPUT SWING Volts
V
S
= 15V
R
L
= 2k
T
A
= +25 C
A
VOL
= +1
Figure 36. Maximum Output Swing vs. Frequency
@
15 V
20
0
500
6
2
100
4
0
12
8
10
14
16
18
400
300
200
LOAD CAPACITANCE pF
OVERSHOOT %
V
S
= 15V
R
L
= 2k
V
IN
= 100mV p-p
T
A
= +25 C
A
VCL
= +1
POSITIVE
EDGE
NEGATIVE
EDGE
Figure 37. Small Signal Overshoot vs. Load Capacitance
@
15 V
OP113/OP213/OP413
14
REV. C
2.0
0
125
1.5
0.5
50
1.0
75
100
50
25
0
25
TEMPERATURE C
SLEW RATE V/
s
75
V
S
= +5, 0
+0.5V
V
OUT
+4.0V
+SLEW RATE
SLEW RATE
Figure 38. Slew Rate vs. Temperature @ +5 V
(0.5 V
V
OUT
+4.0 V)
10
100
0%
90
20mV
1s
Figure 39. Input Voltage Noise @
15 V
(20 nV/div)
t
OUT
A
V
= 100
909
100
0.1 10Hz
A
V
= 1000
Figure 40. Noise Test Diagram
2.0
0
125
1.5
0.5
50
1.0
75
100
50
25
0
25
TEMPERATURE C
SLEW RATE V/
s
75
V
S
= 15V
V
OUT
= 10V
+SLEW RATE
SLEW RATE
Figure 41. Slew Rate vs. Temperature @
15 V
(10
V
V
OUT
+10.0 V)
0%
100
20mV
1s
90
10
Figure 42. Input Voltage Noise @ +5 V
(20 nV/ div)
5
0
125
3
1
50
2
4
100
75
50
25
0
25
TEMPERATURE C
SUPPLY CURRENT mA
75
V
S
= 18V
V
S
= 15V
V
S
= +5.0V
Figure 43. Supply Current vs. Temperature
OP113/OP213/OP413
REV. C
15
9V 9V
+IN
IN
OUT
Figure 44. OP213 Simplified Schematic
*OP113 Family SPICE Macro-Model
*
*Copyright 1992 by Analog Devices, Inc.
*
*Node Assignments
*
*
Noninverting Input
*
Inverting Input
*
Positive Supply
*
Negative Supply
*
Output
*
.SUBCKT OP113 Family
3 2
7
4
6
*
* INPUT STAGE
R3
4
19
1.5E3
R4
4
20
1.5E3
C1
19 20
5.31E12
I1
7
18
106E6
IOS
2
3
25E09
EOS
12 5
POLY(1)
51
4
25E06
1
Q1
19 3
18
PNP1
Q2
20 12
18
PNP1
CIN
3
2
3E12
D1
3
1
DY
D2
2
1
DY
EN
5
2
22
0
1
GN1
0
2
25
0
1E5
GN2
0
3
28
0
1E5
*
* VOLTAGE NOISE SOURCE WITH FLICKER NOISE
DN1
21 22
DEN
DN2
22 23
DEN
VN1
21 0
DC 2
VN2
0
23
DC 2
*
* CURRENT NOISE SOURCE WITH FLICKER NOISE
DN3
24 25
DIN
DN4
25 26
DIN
VN3
24 0
DC 2
VN4
0
26
DC 2
*
* SECOND CURRENT NOISE SOURCE
DN5
27
28
DIN
DN6
28
29
DIN
VN5
27
0
DC 2
VN6
0
29
DC 2
*
* GAIN STAGE & DOMINANT POLE AT .2000E+01 HZ
G2
34
36
19
20
2.65E04
R7
34
36
39E+06
V3
35
4
DC 6
D4
36
35
DX
VB2
34
4
1.6
*
* SUPPLY/2 GENERATOR
ISY
7
4
0.2E3
R10
7
60
40E+3
R11
60
4
40E+3
C3
60
0
1E9
*
* CMRR STAGE & POLE AT 6 kHZ
ECM 50
4
POLY(2) 3
60
2
60
0
1.6
0
1.6
CCM 50
51
26.5E12
RCM1 50
51
1E6
RCM2 51
4
1
*
*
OUTPUT STAGE
R12
37
36
1E3
R13
38
36
500
C4
37
6
20E12
C5
38
39
20E12
M1
39
36
4 4 MN L=9E6 W=1000E6 AD=15E9 AS=15E9
M2
45
36
4 4 MN L=9E6 W=1000E6 AD=15E9 AS=15E9
D5
39
47
DX
D6
47
45
DX
Q3
39
40
41
QPA 8
VB
7
40
DC 0.861
R14
7
41
375
Q4
41
7
43
QNA 1
R17
7
43
15
Q5
43
39
6
QNA 20
Q6
46
45
6
QPA 20
R18
46
4
15
Q7
36
46
4
QNA 1
M3
6
36
4 4 MN L = 9E6 W=2000E6 AD=30E9 AS=30E9
*
* NONLINEAR MODELS USED
*
.MODEL DX D (IS=1E15)
.MODEL DY D (IS=1E15 BV=7)
.MODEL PNP1 PNP (BF=220)
.MODEL DEN D(IS=1E12 RS=1016 KF=3.278E15 AF=1)
.MODEL DIN D(IS=1E12 RS=100019 KF=4.173E15 AF=1)
.MODEL QNA NPN(IS=1.19E16 BF=253 VAF=193 VAR=15 RB=2.0E3
+ IRB=7.73E6 RBM=132.8 RE=4 RC=209 CJE=2.1E13 VJE=0.573
+ MJE=0.364 CJC=1.64E13 VJC=0.534 MJC=0.5 CJS=1.37E12
+ VJS=0.59 MJS=0.5 TF=0.43E9 PTF=30)
.MODEL QPA PNP(IS=5.21E17 BF=131 VAF=62 VAR= 15 RB=1.52E3
+ IRB=1.67E5 RBM=368.5 RE=6.31 RC=354.4 CJE=1.1E13
+ VJE=0.745 MJE=0.33 CJC=2.37E13 VJC=0.762 MJC=0.4
+ CJS=7.11E13 VJS=0.45 MJS=0.412 TF=1.0E9 PTF=30)
.MODEL MN NMOS(LEVEL=3 VTO=1.3 RS=0.3 RD=0.3 TOX=8.5E8
+ LD=1.48E6 WD=1E6 NSUB=1.53E16 UO=650 DELTA=10 VMAX=2E5
+ XJ=1.75E6 KAPPA=0.8 ETA=0.066 THETA=0.01 TPG=1 CJ=2.9E4
+ PB=0.837 MJ=0.407 CJSW=0.5E9 MJSW=0.33)
*
.ENDS OP113 Family
OP113/OP213/OP413
16
REV. C
C1805a02/98
PRINTED IN U.S.A.
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead Plastic DIP
(N-8)
8
1
4
5
0.430 (10.92)
0.348 (8.84)
0.280 (7.11)
0.240 (6.10)
PIN 1
SEATING
PLANE
0.022 (0.558)
0.014 (0.356)
0.060 (1.52)
0.015 (0.38)
0.210 (5.33)
MAX
0.130
(3.30)
MIN
0.070 (1.77)
0.045 (1.15)
0.100
(2.54)
BSC
0.160 (4.06)
0.115 (2.93)
0.325 (8.25)
0.300 (7.62)
0.015 (0.381)
0.008 (0.204)
0.195 (4.95)
0.115 (2.93)
8-Lead Narrow-Body Plastic DIP
(SO-8)
0.1968 (5.00)
0.1890 (4.80)
8
5
4
1
0.2440 (6.20)
0.2284 (5.80)
PIN 1
0.1574 (4.00)
0.1497 (3.80)
0.0688 (1.75)
0.0532 (1.35)
SEATING
PLANE
0.0098 (0.25)
0.0040 (0.10)
0.0192 (0.49)
0.0138 (0.35)
0.0500
(1.27)
BSC
0.0098 (0.25)
0.0075 (0.19)
0.0500 (1.27)
0.0160 (0.41)
8
0
0.0196 (0.50)
0.0099 (0.25)
x 45
14-Lead Plastic DIP
(N-14)
14
1
7
8
0.795 (20.19)
0.725 (18.41)
0.280 (7.11)
0.240 (6.10)
PIN 1
0.325 (8.25)
0.300 (7.62)
0.015 (0.38)
0.008 (0.20)
0.195 (4.95)
0.115 (2.93)
SEATING
PLANE
0.022 (0.558)
0.014 (0.36)
0.060 (1.52)
0.015 (0.38)
0.210 (5.33)
MAX
0.130
(3.30)
MIN
0.070 (1.77)
0.045 (1.15)
0.100
(2.54)
BSC
0.160 (4.06)
0.115 (2.92)
16-Lead Wide Body SOIC
(R-16)
0.2992 (7.60)
0.2914 (7.40)
16
9
8
1
0.4133 (10.50)
0.3977 (10.00)
0.4193 (10.65)
0.3937 (10.00)
PIN 1
SEATING
PLANE
0.0118 (0.30)
0.0040 (0.10)
0.0192 (0.49)
0.0138 (0.35)
0.1043 (2.65)
0.0926 (2.35)
0.0500
(1.27)
BSC
0.0125 (0.32)
0.0091 (0.23)
0.0500 (1.27)
0.0157 (0.40)
0.0291 (0.74)
0.0098 (0.25)
x 45
8
0
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