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Электронный компонент: OP162

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a
OP162/OP262/OP462
15 MHz Rail-to-Rail
Operational Amplifiers
FEATURES
Wide Bandwidth: 15 MHz
Low Offset Voltage: 325 V max
Low Noise: 9.5 nV/
Hz @ 1 kHz
Single-Supply Operation: +2.7 V to +12 V
Rail-to-Rail Output Swing
Low TCV
OS
: 1 V/ C typ
High Slew Rate: 13 V/ s
No Phase Inversion
Unity Gain Stable
APPLICATIONS
Portable Instrumentation
Sampling ADC Amplifier
Wireless LANs
Direct Access Arrangement
Office Automation
GENERAL DESCRIPTION
The OP162 (single), OP262 (dual), OP462 (quad) rail-to-rail
15 MHz amplifiers feature the extra speed new designs require,
with the benefits of precision and low power operation. With
their incredibly low offset voltage of 45
mV (typ) and low noise,
they are perfectly suited for precision filter applications and
instrumentation. The low supply current of 500
mA (typ) is
critical for portable or densely packed designs. In addition, the
rail-to-rail output swing provides greater dynamic range and
control than standard video amplifiers provide.
These products operate from single supplies as low as +2.7 V to
dual supplies of
6 V. The fast settling times and wide output
swings recommend them for buffers to sampling A/D converters.
The output drive of 30 mA (sink and source) is needed for
many audio and display applications; more output current can
be supplied for limited durations.
The OP162 family is specified over the extended industrial
temperature range (40
C to +125C). The single OP162
and dual OP262 are available in 8-lead SOIC and TSSOP
packages. The quad OP462 is available in 14-lead narrow-body
SOIC and TSSOP packages.
PIN CONFIGURATIONS
8-Lead Narrow-Body SO
(S Suffix)
NC = NO CONNECT
NULL
V+
NC
NULL
OUT A
IN A
+IN A
V
1
4
5
8
OP162
8-Lead TSSOP
(RU Suffix)
OP162
1
4
5
8
NULL
IN A
+IN A
V
NULL
V+
OUT A
NC
NC = NO CONNECT
8-Lead Narrow-Body SO
(S Suffix)
OUT A
V+
OUT B
IN A
+IN A
V
+IN B
IN B
1
4
5
8
OP262
8-Lead TSSOP
(RU Suffix)
OP262
1
4
5
8
OUT A
IN A
+IN A
V
V+
OUT B
IN B
+IN B
14-Lead Narrow-Body SO
(S Suffix)
1
7
8
14
OP462
OUT A
IN A
+IN A
V+
+IN B
IN B
OUT B
V
+IN D
IN D
OUT D
OUT C
IN C
+IN C
14-Lead TSSOP
(RU Suffix)
OP462
1
7
8
14
OUT A
IN A
+IN A
V+
+IN B
IN B
OUT B
OUT D
IN D
+IN D
V
+IN C
IN C
OUT C
REV. D
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
Analog Devices, Inc., 2002
OP162/OP262/OP462SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Parameter
Symbol
Conditions
Min
Typ
Max
Units
INPUT CHARACTERISTICS
Offset Voltage
V
OS
OP162G, OP262G, OP462G,
45
325
mV
40
C T
A
+125C
800
mV
H Grade, 40
C T
A
+125C
1
mV
D Grade, 40
C T
A
+125C
0.8
3
mV
5
mV
Input Bias Current
I
B
360
600
nA
40
C T
A
+125C
650
nA
Input Offset Current
I
OS
2.5
25
nA
40
C T
A
+125C
40
nA
Input Voltage Range
V
CM
0
+4
V
Common-Mode Rejection
CMRR
0 V
V
CM
+4.0 V,
40
C T
A
+125C
70
110
dB
Large Signal Voltage Gain
A
VO
R
L
= 2 k
W, 0.5 V
OUT
4.5 V
30
V/mV
R
L
= 10 k
W, 0.5 V
OUT
4.5 V
65
88
V/mV
R
L
= 10 k
W, 40C T
A
+125C
40
V/mV
Long-Term Offset Voltage
V
OS
G Grade
1
600
mV
Offset Voltage Drift
DV
OS
/
DT
Note 2
1
mV/C
Bias Current Drift
DI
B
/
DT
250
pA/
C
OUTPUT CHARACTERISTICS
Output Voltage Swing High
V
OH
I
L
= 250
mA, 40C T
A
+125C
4.95
4.99
V
I
L
= 5 mA
4.85
4.94
V
Output Voltage Swing Low
V
OL
I
L
= 250
mA, 40C T
A
+125C
14
50
mV
I
L
= 5 mA
65
150
mV
Short Circuit Current
I
SC
Short to Ground
80
mA
Maximum Output Current
I
OUT
30
mA
POWER SUPPLY
Power Supply Rejection Ratio
PSRR
V
S
= +2.7 V to +7 V
120
dB
40
C T
A
+125C
90
dB
Supply Current/Amplifier
I
SY
OP162, V
OUT
= 2.5 V
600
750
mA
40
C T
A
+125C
1
mA
OP262, OP462, V
OUT
= 2.5 V
500
700
mA
40
C T
A
+125C
850
mA
DYNAMIC PERFORMANCE
Slew Rate
SR
1 V < V
OUT
< 4 V, R
L
= 10 k
W
10
V/
ms
Settling Time
t
S
To 0.1%, A
V
= 1, V
O
= 2 V Step
540
ns
Gain Bandwidth Product
GBP
15
MHz
Phase Margin
f
m
61
Degrees
NOISE PERFORMANCE
Voltage Noise
e
n
p-p
0.1 Hz to 10 Hz
0.5
mV p-p
Voltage Noise Density
e
n
f = 1 kHz
9.5
nV/
Hz
Current Noise Density
i
n
f = 1 kHz
0.4
pA/
Hz
NOTES
1
Long-term offset voltage is guaranteed by a 1000 hour life test performed on three independent lots at +125
C, with an LTPD of 1.3.
2
Offset voltage drift is the average of the 40
C to +25C delta and the +25C to +125C delta.
Specifications subj]ect to change without notice.
(@ V
S
= +5.0 V, V
CM
= 0 V, T
A
= +25 C, unless otherwise noted)
REV. D
2
OP162/OP262/OP462SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Parameter
Symbol
Conditions
Min
Typ
Max
Units
INPUT CHARACTERISTICS
Offset Voltage
V
OS
OP162G, OP262G, OP462G
50
325
mV
H Grade, 40
C T
A
+125C
1
mV
D Grade, 40
C T
A
+125C
0.8
3
mV
5
mV
Input Bias Current
I
B
360
600
nA
Input Offset Current
I
OS
2.5
25
nA
Input Voltage Range
V
CM
0
+2
V
Common-Mode Rejection
CMRR
0 V
V
CM
+2.0 V,
40
C T
A
+125C
70
110
dB
Large Signal Voltage Gain
A
VO
R
L
= 2 k
W, 0.5 V V
OUT
2.5 V
20
V/mV
R
L
= 10 k
W, 0.5 V V
OUT
2.5 V
20
30
V/mV
Long-Term Offset Voltage
V
OS
G Grade
1
600
mV
OUTPUT CHARACTERISTICS
Output Voltage Swing High
V
OH
I
L
= 250
mA
2.95
2.99
V
I
L
= 5 mA
2.85
2.93
V
Output Voltage Swing Low
V
OL
I
L
= 250
mA
14
50
mV
I
L
= 5 mA
66
150
mV
POWER SUPPLY
Power Supply Rejection Ratio
PSRR
V
S
= +2.7 V to +7 V,
40
C T
A
+125C
60
110
dB
Supply Current/Amplifier
I
SY
OP162, V
OUT
= 1.5 V
600
700
mA
40
C T
A
+125C
1
mA
OP262, OP462, V
OUT
= 1.5 V
500
650
mA
40
C T
A
+125C
850
mA
DYNAMIC PERFORMANCE
Slew Rate
SR
R
L
= 10 k
W
10
V/
ms
Settling Time
t
S
To 0.1%, A
V
= 1, V
O
= 2 V Step
575
ns
Gain Bandwidth Product
GBP
15
MHz
Phase Margin
f
m
59
Degrees
NOISE PERFORMANCE
Voltage Noise
e
n
p-p
0.1 Hz to 10 Hz
0.5
mV p-p
Voltage Noise Density
e
n
f = 1 kHz
9.5
nV/
Hz
Current Noise Density
i
n
f = 1 kHz
0.4
pA/
Hz
NOTES
1
Long-term offset voltage is guaranteed by a 1000 hour life test performed on three independent lots at +125
C, with an LTPD of 1.3.
Specifications subject to change without notice.
OP162/OP262/OP462
REV. D
3
(@ V
S
= +3.0 V, V
CM
= 0 V, T
A
= +25 C, unless otherwise noted)
OP162/OP262/OP462SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Parameter
Symbol
Conditions
Min
Typ
Max
Units
INPUT CHARACTERISTICS
Offset Voltage
V
OS
OP162G, OP262G, OP462G
25
325
mV
40
C T
A
+125C
800
mV
H Grade, 40
C T
A
+125C
1
mV
D Grade, 40
C T
A
+125C
0.8
3
mV
5
mV
Input Bias Current
I
B
260
500
nA
40
C T
A
+125C
650
nA
Input Offset Current
I
OS
2.5
25
nA
40
C T
A
+125C
40
nA
Input Voltage Range
V
CM
5
+4
V
Common-Mode Rejection
CMRR
4.9 V
V
CM
+4.0 V,
40
C T
A
+125C
70
110
dB
Large Signal Voltage Gain
A
VO
R
L
= 2 k
W, 4.5 V V
OUT
4.5 V
35
V/mV
R
L
= 10 k
W, 4.5 V V
OUT
4.5 V
75
120
V/mV
40
C T
A
+125C
25
V/mV
Long-Term Offset Voltage
V
OS
G Grade
1
600
mV
Offset Voltage Drift
DV
OS
/
DT
Note 2
1
mV/C
Bias Current Drift
DI
B
/
DT
250
pA/
C
OUTPUT CHARACTERISTICS
Output Voltage Swing High
V
OH
I
L
= 250
mA, 40C T
A
+125C 4.95
4.99
V
I
L
= 5 mA
4.85
4.94
V
Output Voltage Swing Low
V
OL
I
L
= 250
mA, 40C T
A
+125C
4.99
4.95
V
I
L
= 5 mA
4.94
4.85
V
Short Circuit Current
I
SC
Short to Ground
80
mA
Maximum Output Current
I
OUT
30
mA
POWER SUPPLY
Power Supply Rejection Ratio
PSRR
V
S
=
1.35 V to 6 V,
40
C T
A
+125C
60
110
dB
Supply Current/Amplifier
I
SY
OP162, V
OUT
= 0 V
650
800
mA
40
C T
A
+125C
1.15
mA
OP262, OP462, V
OUT
= 0 V
550
775
mA
40
C T
A
+125C
1
mA
Supply Voltage Range
V
S
+3.0 (
1.5)
+12 (
6) V
DYNAMIC PERFORMANCE
Slew Rate
SR
4 V < V
OUT
< 4 V, R
L
= 10 k
W
13
V/
ms
Settling Time
t
S
To 0.1%, A
V
= 1, V
O
= 2 V Step
475
ns
Gain Bandwidth Product
GBP
15
MHz
Phase Margin
f
m
64
Degrees
NOISE PERFORMANCE
Voltage Noise
e
n
p-p
0.1 Hz to 10 Hz
0.5
mV p-p
Voltage Noise Density
e
n
f = 1 kHz
9.5
nV/
Hz
Current Noise Density
i
n
f = 1 kHz
0.4
pA/
Hz
NOTES
1
Long-term offset voltage is guaranteed by a 1000 hour life test performed on three independent lots at +125
C, with an LTPD of 1.3.
2
Offset voltage drift is the average of the 40
C to +25C delta and the +25C to +125C delta.
Specifications subject to change without notice.
(@ V
S
= 5.0 V, V
CM
= 0 V, T
A
= +25 C, unless otherwise noted)
REV. D
4
5
REV. D
OP162/OP262/OP462
ABSOLUTE MAXIMUM RATINGS
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6 V
Input Voltage
1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6 V
Differential Input Voltage
2
. . . . . . . . . . . . . . . . . . . . .
0.6 V
Internal Power Dissipation
SOIC (S) . . . . . . . . . . . . . . . . . . . Observe Derating Curves
TSSOP (RU) . . . . . . . . . . . . . . . . Observe Derating Curves
Output Short-Circuit Duration . . . . Observe Derating Curves
Storage Temperature Range . . . . . . . . . . . . 65
C to +150C
Operating Temperature Range . . . . . . . . . . 40
C to +125C
Junction Temperature Range . . . . . . . . . . . . 65
C to +150C
Lead Temperature Range (Soldering, 10 sec) . . . . . . . +300
C
Package Type
JA
3
JC
Units
8-Lead SOIC (S)
158
43
C/W
8-Lead TSSOP (RU)
240
43
C/W
14-Lead SOIC (S)
120
36
C/W
14-Lead TSSOP (RU)
180
35
C/W
NOTES
1
For supply voltages greater than 6 volts, the input voltage is limited to less than or
equal to the supply voltage.
2
For differential input voltages greater than 0.6 volts the input current should be
limited to less than 5 mA to prevent degradation or destruction of the input devices.
3
q
JA
is specified for the worst case conditions, i.e.,
q
JA
is specified for device soldered
in circuit board for SOIC and TSSOP packages.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the OP162/OP262/OP462 features proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high energy electrostatic discharges. Therefore, p roper
ESD precautions are recommended to avoid performance degradation or loss of functionality.
ORDERING GUIDE
Temperature
Package
Package
Model
Range
Description
Option
OP162GS
40
C to +125C 8-Lead SOIC
RN-8
OP162DRU 40
C to +125C 8-Lead TSSOP
RU-8
OP162HRU 40
C to +125C 8-Lead TSSOP
RU-8
OP262DRU 40
C to +125C 8-Lead TSSOP
RU-8
OP262GS
40
C to +125C 8-Lead SOIC
RN-8
OP262HRU 40
C to +125C 8-Lead TSSOP
RU-8
OP462DRU 40
C to +125C 14-Lead TSSOP
RU-14
OP462DS
40
C to +125C 14-Lead SOIC
RN-14
OP462GS
40
C to +125C 14-Lead SOIC
RN-14
OP462HRU 40
C to +125C 14-Lead TSSOP
RU-14
WARNING!
ESD SENSITIVE DEVICE
6
REV. D
INPUT OFFSET DRIFT, TCV
OS
V/ C
QUANTITY Amplifiers
100
80
0
60
40
20
0.2
0.3
1.3
1.1
0.7
0.9
0.5
1.5
V
S
= 5V
T
A
= 25 C
COUNT =
360 OP AMPS
Figure 2. OP462 Input Offset Voltage
Drift (TCV
OS
)
TEMPERATURE C
INPUT BIAS CURRENT nA
0
100
500
50
25
150
0
25
50
75
100 125
200
300
400
V
S
= 5V
Figure 5. OP462 Input Bias Current
vs. Temperature
TEMPERATURE C
OUTPUT LOW VOLTAGE mV
0.100
0.080
0.000
75 50
150
25
0
25
75 100 125
50
0.060
0.040
0.020
I
OUT
= 5mA
I
OUT
= 250 A
V
S
= 5V
Figure 8. OP462 Output Low Voltage
vs. Temperature
COMMON-MODE VOLTAGE Volts
INPUT BIAS CURRENT nA
420
100
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
340
260
180
V
S
= 5V
Figure 3. OP462 Input Bias Current
vs. Common-Mode Voltage
TEMPERATURE C
0
75 50
150
25
0
25
75 100 125
50
15
10
5
INPUT OFFSET CURRENT nA
V
S
= 5V
Figure 6. OP462 Input Offset Current
vs. Temperature
TEMPERATURE C
OPEN-LOOP GAIN V
/
m
V
100
80
0
75 50
150
25
0
25
75 100 125
50
60
40
20
V
S
= 5V
R
L
= 2k
R
L
= 600
R
L
= 10k
Figure 9. OP462 Open-Loop Gain
vs. Temperature
INPUT OFFSET VOLTAGE V
QUANTITY Amplifiers
250
200
0
150
100
50
V
S
= 5V
T
A
= 25 C
COUNT =
720 OP AMPS
200 140
160
100
20
40
80
Figure 1. OP462 Input Offset Voltage
Distribution
TEMPERATURE C
INPUT OFFSET VOLTAGE
V
125
100
0
75 50
150
25
0
25
75 100 125
50
75
50
25
V
S
= 5V
Figure 4. OP462 Input Offset Voltage
vs. Temperature
TEMPERATURE C
OUTPUT HIGH VOLTAGE Volts
5.12
5.06
4.82
75 50
150
25
0
25
75 100 125
50
5.00
4.94
4.88
I
OUT
= 250 A
I
OUT
= 5mA
V
S
= 5V
Figure 7. OP462 Output High Voltage
vs. Temperature
OP162/OP262/OP462Typical Performance Characteristics
7
REV. D
OP162/OP262/OP462
LOAD CURRENT mA
OUTPUT VOLTAGE mV
100
80
0
0
1
7
2
3
4
5
6
60
40
20
V
S
= 10V
V
S
= 3V
Figure 10. Output Low Voltage to
Supply Rail vs. Load Current
FREQUENCY Hz
GAIN dB
50
40
30
100k
1M
100M
10M
30
20
20
10
0
10
PHASE SHIFT dB
45
90
270
135
180
225
GAIN
PHASE
V
S
= 5V
T
A
= 25 C
Figure 13. Open-Loop Gain and
Phase vs. Frequency (No Load)
SETTLING TIME ns
STEP SIZE Volts
4
3
4
0
200
1000
400
600
800
0
1
2
3
2
1
V
S
= 5V
T
A
= 25 C
0.1%
0.01%
0.1%
0.01%
Figure 16. Settling Time vs. Step Size
TEMPERATURE C
SUPPLY CURRENT mA
1.0
0
75 50
150
25
0
25
75 100 125
50
0.9
0.5
0.3
0.2
0.1
0.8
0.7
0.4
0.6
V
S
= 10V
V
S
= 5V
V
S
= 3V
Figure 11. Supply Current/Amplifier
vs. Temperature
FREQUENCY Hz
CLOSED-LOOP GAIN dB
60
40
40
10k
100k
100M
1M
10M
20
0
20
V
S
= 5V
T
A
= +25 C
R
L
= 830
C
L
5pF
Figure 14. Closed-Loop Gain vs.
Frequency
CAPACITANCE pF
OVERSHOOT %
60
50
0
10
100
1000
30
20
10
40
V
S
= 5V
T
A
= 25 C
V
IN
= 50mV
R
L
= 10k
+OS
OS
Figure 17. Small-Signal Overshoot
vs. Capacitance
SUPPLY VOLTAGE Volts
SUPPLY CURRENT mA
0
2
12
4
6
8
10
0.4
0.7
0.5
0.6
T
A
= 25 C
Figure 12. OP462 Supply Current/
Amplifier vs. Supply Voltage
FREQUENCY Hz
MAXIMUM OUTPUT SWING V p-p
5
4
0
10k
100k
10M
1M
3
2
1
V
S
= 5V
A
VCL
= 1
R
L
= 10k
C
L
= 15pF
T
A
= 25
C
DISTORTION < 1%
Figure 15. Maximum Output Swing
vs. Frequency
FREQUENCY Hz
NOISE DENSITY nV/
Hz
70
60
0
1
10
1k
100
50
40
30
20
10
V
S
= 5V
T
A
= 25 C
Figure 18. Voltage Noise Density vs.
Frequency
8
REV. D
OP162/OP262/OP462
FREQUENCY Hz
7
6
0
1
10
1k
100
5
4
3
2
1
V
S
= 5V
T
A
= 25 C
NOISE DENSITY pA/
Hz
Figure 19. Current Noise Density vs.
Frequency
PSRR dB
FREQUENCY Hz
90
80
20
1k
10k
10M
100k
1M
70
60
50
40
30
V
S
= 5V
T
A
= 25 C
PSRR
+PSRR
Figure 22. PSRR vs. Frequency
10
0%
100
90
200ns
20mV
V
S
= 5V
A
V
= 1
T
A
= 25 C
C
L
= 100pF
Figure 25. Small Signal Transient
Response
FREQUENCY Hz
OUTPUT IMPEDANCE
300
250
0
100k
1M
10M
150
100
50
200
V
S
= 5V
T
A
= 25 C
A
VCL
= 10
A
VCL
= 1
Figure 20. Output Impedance vs.
Frequency
100
90
10
0%
2s
20mV
V
S
= 5V
A
V
= 100k
e
n
= 0.5 V p-p
Figure 23. 0.1 Hz to 10 Hz Noise
10
0%
100
90
100 s
500mV
V
S
= 5V
A
V
= 1
T
A
= 25 C
C
L
= 100pF
Figure 26. Large Signal Transient
Response
FREQUENCY Hz
CMRR dB
90
80
20
1k
10k
10M
100k
1M
70
60
50
40
30
V
S
= 5V
T
A
= 25 C
Figure 21. CMRR vs. Frequency
10
0%
100
90
20 s
2V
V
IN
= 12V p-p
V
S
= 5V
A
V
= 1
2V
Figure 24. No Phase Reversal; [V
IN
=
12 V p-p, V
S
=
5 V, A
V
= 1]
9
REV. D
OP162/OP262/OP462
V
CC
. It is important to avoid accidentally connecting the wiper
to V
EE
, as this will damage the device. The recommended value
for the potentiometer is 20 k
W.
6
7
4
1
2
3
8
5V
20k
OP162
+5V
V
OS
Figure 28. Schematic Showing Offset Adjustment
Rail-to-Rail Output
The OP162/OP262/OP462 has a wide output voltage range that
extends to within 60 mV of each supply rail with a load current
of 5 mA. Decreasing the load current will extend the output
voltage range even closer to the supply rails. The common-
mode input range extends from ground to within 1 V of the
positive supply. It is recommended that there be some minimal
amount of gain when a rail-to-rail output swing is desired. The
minimum gain required is based on the supply voltage and can
be found as:
A
V, min
=
V
S
V
S
1
where V
S
is the positive supply voltage. With a single supply
voltage of +5 V, the minimum gain to achieve rail-to-rail output
should be 1.25.
Output Short-Circuit Protection
To achieve a wide bandwidth and high slew rate, the output of
the OP162/OP262/OP462 is not short-circuit protected. Short-
ing the output directly to ground or to a supply rail may destroy
the device. The typical maximum safe output current is
30 mA.
Steps should be taken to ensure the output of the device will not
be forced to source or sink more than 30 mA.
In applications where some output current protection is needed,
but not at the expense of reduced output voltage headroom, a
low value resistor in series with the output can be used. This is
shown in Figure 29. The resistor is connected within the feed-
back loop of the amplifier so that if V
OUT
is shorted to ground
and V
IN
swings up to +5 V, the output current will not exceed
30 mA.
For single +5 V supply applications, resistors less than 169
W
are not recommended.
OPx62
V
IN
169
V
OUT
+5V
Figure 29. Output Short-Circuit Protection
APPLICATIONS SECTION
Functional Description
The OPx62 family is fabricated using Analog Devices' high
speed complementary bipolar process, also called XFCB. The
process includes trench isolating each transistor to lower para-
sitic capacitances thereby allowing high speed performance.
This high speed process has been implemented without trading
off the excellent transistor matching and overall dc performance
characteristic of Analog Devices' complementary bipolar pro-
cess. This makes the OPx62 family an excellent choice as an
extremely fast and accurate low voltage op amp.
Figure 27 shows a simplified equivalent schematic for the OP162.
A PNP differential pair is used at the input of the device. The
cross connecting of the emitters is used to lower the transcon-
ductance of the input stage, which improves the slew rate of the
device. Lowering the transconductance through cross connect-
ing the emitters has another advantage in that it provides a
lower noise factor than if emitter degeneration resistors were
used. The input stage can function with the base voltages taken
all the way to the negative power supply, or up to within 1 V of
the positive power supply.
V
CC
V
EE
+IN
IN
V
OUT
Figure 27. Simplified Schematic
Two complementary transistors in a common-emitter configura-
tion are used for the output stage. This allows the output of the
device to swing to within 50 mV of either supply rail at load
currents less than 1 mA. As load current increases, the maxi-
mum voltage swing of the output will decrease. This is due to
the collector-to-emitter saturation voltages of the output transis-
tors increasing. The gain of the output stage, and consequently
the open-loop gain of the amplifier, is dependent on the load
resistance connected at the output. And because the dominant
pole frequency is inversely proportional to the open-loop gain,
the unity-gain bandwidth of the device is not affected by the
load resistance. This is typically the case in rail-to-rail output
devices.
Offset Adjustment
Because the OP162/OP262/OP462 has such an exceptionally
low typical offset voltage, adjustment to correct offset voltage
may not be needed. However, the OP162 does have pinouts
where a nulling resistor can be attached. Figure 28 shows how
the OP162 offset voltage can be adjusted by connecting a poten-
tiometer between Pins 1 and 8, and connecting the wiper to
OP162/OP262/OP462
10
REV. D
Input Overvoltage Protection
The input voltage should be limited to
6 V or damage to the
device can occur. Electrostatic protection diodes placed in the
input stage of the device help protect the amplifier from static
discharge. Diodes are connected between each input as well as
from each input to both supply pins as shown in the simplified
equivalent circuit in Figure 27. If an input voltage exceeds
either supply voltage by more than 0.6 V, or if the differential
input voltage is greater than 0.6 V, these diodes begin to ener-
gize and overvoltage damage could occur. The input current
should be limited to less than 5 mA to prevent degradation or
destruction of the device.
This can be done by placing an external resistor in series with
the input that could be overdriven. The size of the resistor can
be calculated by dividing the maximum input voltage by 5 mA.
For example, if the differential input voltage could reach 5 V,
the external resistor should be 5 V/5 mA = 1 k
W. In practice,
this resistance should be placed in series with both inputs to
balance any offset voltages created by the input bias current.
Output Phase Reversal
The OP162/OP262/OP462 is immune to phase reversal as long
as the input voltage is limited to
6 V. Figure 24 shows a photo
of the output of the device with the input voltage driven beyond
the supply voltages. Although the device's output will not
change phase, large currents due to input overvoltage could
result, damaging the device. In applications where the possibility
of an input voltage exceeding the supply voltage exists, over-
voltage protection should be used, as described in the previous
section.
Power Dissipation
The maximum power that can be safely dissipated by the
OP162/OP262/OP462 is limited by the associated rise in junc-
tion temperature. The maximum safe junction temperature is
150
C, and should not be exceeded or device performance
could suffer. If this maximum is momentarily exceeded, proper
circuit operation will be restored as soon as the die temperature
is reduced. Leaving the device in an "overheated" condition for
an extended period can result in permanent damage to the device.
To calculate the internal junction temperature of the OPx62,
the following formula can be used:
T
J
= P
DISS
q
JA
+ T
A
where: T
J
= OPx62 junction temperature;
P
DISS
= OPx62 power dissipation;
q
JA
= OPx62 package thermal resistance, junction-to-
ambient; and
T
A
= Ambient temperature of the circuit.
The power dissipated by the device can be calculated as:
P
DISS
= I
LOAD
(V
S
V
OUT
)
where:
I
LOAD
is the OPx62 output load current;
V
S
is the OPx62 supply voltage; and
V
OUT
is the OPx62 output voltage.
Figures 30 and 31 provide a convenient way to see if the device
is being overheated. The maximum safe power dissipation can
be found graphically, based on the package type and the ambi-
ent temperature around the package. By using the previous
equation, it is a simple matter to see if P
DISS
exceeds the device's
power derating curve. To ensure proper operation, it is impor-
tant to observe the recommended derating curves shown in
Figures 30 and 31.
AMBIENT TEMPERATURE C
2.0
1.5
0
40
120
20
0
20
40
60
80
100
1.0
0.5
8-PIN SOIC
PACKAGE
8-PIN TSSOP
PACKAGE
MAXIMUM POWER DISSIPATION Watts
Figure 30. Maximum Power Dissipation vs. Temperature
for 8-Pin Package Types
AMBIENT TEMPERATURE C
2.0
1.5
0
40
120
20
0
20
40
60
80
100
1.0
0.5
14-PIN SOIC
PACKAGE
14-PIN TSSOP
PACKAGE
MAXIMUM POWER DISSIPATION Watts
Figure 31. Maximum Power Dissipation vs. Temperature
for 14-Pin Package Types
Unused Amplifiers
It is recommended that any unused amplifiers in a dual or a
quad package be configured as a unity gain follower with a 1 k
W
feedback resistor connected from the inverting input to the
output and the noninverting input tied to the ground plane.
Power On Settling Time
The time it takes for the output of an op amp to settle after a
supply voltage is delivered can be an important consideration in
some power-up sensitive applications. An example of this
would be in an A/D converter where the time until valid data
can be produced after power-up is important.
The OPx62 family has a rapid settling time after power-up.
Figure 32 shows the OP462 output settling times for a single
supply voltage of V
S
= +5 V. The test circuit in Figure 33 was
used to find the power on settling times for the device.
11
REV. D
OP162/OP262/OP462
10
0%
100
90
500ns
2V
50mV
V
S
= 5V
A
V
= 1
R
L
= 10k
Figure 32. Oscilloscope Photo of V
S
and V
OUT
OP462
V
OUT
10k
+1
+
0 TO +5V
SQUARE
Figure 33. Test Circuit for Power On Settling Time
Capacitive Load Drive
The OP162/OP262/OP462 is a high speed, extremely accurate
device and can tolerate some capacitive loading at its output.
As load capacitance increases, however, the unity-gain band-
width of the device will decrease. There will also be an increase
in overshoot and settling time for the output. Figure 35 shows
an example of this with the device configured for unity gain and
driving a 10 k
W resistor and 300 pF capacitor placed in parallel.
By connecting a series R-C network, commonly called a "snub-
ber" network, from the output of the device to ground, this
ringing can be eliminated and overshoot can be significantly
reduced. Figure 34 shows how to set up the snubber network,
and Figure 36 shows the improvement in output response with
the network added.
OPx62
V
IN
V
OUT
+5V
R
X
C
X
C
L
Figure 34. Snubber Network Compensation for Capacitive
Loads
50mV
V
S
= 5V
A
V
= 1
C
L
= 300pF
R
L
= 10k
1 s
100
90
10
0%
Figure 35. A Photo of a Ringing Square Wave
10
0%
100
90
50mV
1 s
V
S
= 5V
A
V
= 1
C
L
= 300pF
R
L
= 10k
WITH SNUBBER:
R
X
= 140
C
X
= 10nF
Figure 36. A Photo of a Nice Square Wave at the Output
The network operates in parallel with the load capacitor, C
L
,
and provides compensation for the added phase lag. The actual
values of the network resistor and capacitor are determined
empirically to minimize overshoot while maximizing unity-gain
bandwidth. Table I shows a few sample snubber networks for
large load capacitors:
Table I. Snubber Networks for Large Capacitive Loads
C
LOAD
R
X
C
X
<300 pF
140
W
10 nF
500 pF
100
W
10 nF
1 nF
80
W
10 nF
10 nF
10
W
47 nF
Obviously, higher load capacitance will also reduce the unity-
gain bandwidth of the device. Figure 37 shows a plot of unity-
gain bandwidth versus capacitive load. The snubber network
will not provide any increase in bandwidth, but it will substan-
tially reduce ringing and overshoot, as shown in the difference
between Figures 35 and 36.
BANDWIDTH MHz
C
LOAD
10
9
0
10pF
10nF
100pF
1nF
4
3
2
1
6
5
8
7
Figure 37. Unity Gain Bandwidth vs. C
LOAD
Total Harmonic Distortion and Crosstalk
The OPx62 device family offers low total harmonic distortion.
This makes it an excellent device choice for audio applications.
Figure 38 shows a graph of THD plus noise figures at 0.001%
for the OP462.
Figure 39 shows a graph of the worst case crosstalk between two
amplifiers in the OP462 device. A 1 V rms signal is applied to
one amplifier while measuring the output of an adjacent ampli-
fier. Both amplifiers are configured for unity gain and supplied
with
2.5 V.
OP162/OP262/OP462
12
REV. D
THD+N %
FREQUENCY Hz
0.010
0.0001
20
10k
100
1k
0.001
20k
V
S
= 2.5V
A
V
= 1
V
IN
= 1.0V rms
R
L
= 10k
BANDWIDTH:
<10Hz TO 22kHz
Figure 38. THD+N vs. Frequency Graph
XTALK dBV
FREQUENCY Hz
40
140
20
10k
100
1k
90
20k
50
60
70
80
100
110
120
130
A
V
= 1
V
IN
= 1.0V rms
R
L
= 10k
V
S
= 2.5V
(0dBV)
Figure 39. Crosstalk vs. Frequency Graph
PCB Layout Considerations
Because the OP162/OP262/OP462 can provide gain at high
frequency, careful attention to board layout and component
selection is recommended. As with any high speed application,
a good ground plane is essential to achieve the optimum perfor-
mance. This can significantly reduce the undesirable effects of
ground loops and I
R losses by providing a low impedance refer-
ence point. Best results are obtained with a multilayer board
design with one layer assigned to ground plane.
Chip capacitors should be used for supply bypassing, with one
end of the capacitor connected to the ground plane and the
other end connected within 1/8 inch of each power pin. An
additional large tantalum electrolytic capacitor (4.7
mF10 mF)
should be connected in parallel. This capacitor does not need to
be placed as close to the supply pins, as it is to provide current
for fast large-signal changes at the device's output.
APPLICATION CIRCUITS
Single Supply Stereo Headphone Driver
Figure 40 shows a stereo headphone output amplifier that can
be run from a single +5 V supply. The reference voltage is
derived by dividing the supply voltage down with two 100 k
W
resistors. A 10
mF capacitor prevents power supply noise from
contaminating the audio signal and establishes an ac ground for
the volume control potentiometers.
The audio signal is ac coupled to each noninverting input
through a 10
mF capacitor. The gain of the amplifier is con-
trolled by the feedback resistors and is: (R2/R1) + 1. For this
example, the gain is 6. By removing R1 altogether, the amplifier
would have unity gain. A 169
W resistor is placed at the output
in the feedback network to short-circuit protect the output of
the device. This would prevent any damage to the device from
occurring if the headphone output became shorted. A 270
mF
capacitor is used at the output to couple the amplifier to the
headphone. This value is much larger than that used for the
input because of the low impedance of headphones, which can
range from 32
W to 600 W or more.
OP262-A
5V
169
270 F
47k
HEADPHONE
LEFT
L VOLUME
CONTROL
R1 = 10k
10 F
10 F
10k
5V
100k
10 F
100k
R2
= 50k
LEFT IN
OP262-B
5V
169
270 F
47k
HEADPHONE
RIGHT
10k
R VOLUME
CONTROL
10 F
RIGHT IN
R2
= 50k
10 F
R1
= 10k
Figure 40. Headphone Output Amplifier
Instrumentation Amplifier
Because of its high speed, low offset voltages and low noise
characteristics, the OP162/OP262/OP462 can be used in a wide
variety of high speed applications, including a precision instru-
mentation amplifier. Figure 41 shows an example of such an
application.
OP462-A
OP462-B
OP462-C
OP462-D
V
IN
+V
IN
1k
10k
2k
1.9k
200
10 TURN
(OPTIONAL)
OUTPUT
R
G
1k
10k
2k
2k
Figure 41. A High Speed Instrumentation Amplifier
13
REV. D
OP162/OP262/OP462
The differential gain of the circuit is determined by R
G
, where:
A
DIFF
= 1+
2
R
G
with the R
G
resistor value in k
W. Removing R
G
will set the cir-
cuit gain to unity.
The fourth op amp, OP462-D, is optional and is used to im-
prove CMRR by reducing any input capacitance to the ampli-
fier. By shielding the input signal leads and driving the shield
with the common-mode voltage, input capacitance is eliminated
at common-mode voltages. This voltage is derived from the
midpoint of the outputs of OP462-A and OP462-B by using two
10 k
W resistors followed by OP462-D as a unity gain buffer.
It is important to use 1% or better tolerance components for the
2 k
W resistors, as the common-mode rejection is dependent on
their ratios being exact. A potentiometer should also be con-
nected in series with the OP462-C noninverting input resistor to
ground to optimize common-mode rejection.
The circuit in Figure 41 was implemented to test its settling
time. The instrumentation amp was powered with
5 V, so the
input step voltage went from 5 V to +4 V to keep the OP462
within its input range. Therefore, the 0.05% settling range is
when the output is within 4.5 mV. Figure 42 shows the positive
slope settling time to be 1.8
ms, and Figure 43 shows a settling
time of 3.9
ms for the negative slope.
10
0%
100
90
5mV
1 s
2V
Figure 42. Positive Slope Settling Time
10
0%
100
90
5mV
1s
2V
10
0%
100
90
5mV
1 s
Figure 43. Negative Slope Settling Time
Direct Access Arrangement
Figure 44 shows a schematic for a +5 V single supply transmit/
receive telephone line interface for 600
W transmission systems.
It allows full duplex transmission of signals on a transformer
coupled 600
W line. Amplifier A1 provides gain that can be
adjusted to meet the modem output drive requirements. Both
A1 and A2 are configured so as to apply the largest possible
differential signal to the transformer. The largest signal available
on a single +5 V supply is approximately 4.0 V p-p into a 600
W
transmission system. Amplifier A3 is configured as a difference
amplifier to extract the receive information from the transmis-
sion line for amplification by A4. A3 also prevents the transmit
signal from interfering with the receive signal. The gain of A4
can be adjusted in the same manner as A1's to meet the modem's
input signal requirements. Standard resistor values permit the
use of SIP (Single In-line Package) format resistor arrays. Couple
this with the OP462 14-lead SOIC or TSSOP package and this
circuit can offer a compact solution.
6.2V
6.2V
TRANSMIT
TXA
RECEIVE
RXA
C1
0.1 F
R1
10k
R2
9.09k
2k
P1
TX GAIN
ADJUST
A1
A2
A3
A4
A1, A2 = 1/2 AD8532
A3, A4 = 1/2 AD8532
R3
360
1:1
T1
TO TELEPHONE
LINE
1
2
3
7
6
5
2
3
1
6
5
7
10 F
R7
10k
R8
10k
R5
10k
R6
10k
R9
10k
R14
14.3k
R10
10k
R11
10k
R12
10k
R13
10k
C2
0.1 F
P2
RX GAIN
ADJUST
2k
Z
O
600
5V DC
MIDCOM
671-8005
Figure 44. A Single-Supply Direct Access Arrangement for
Modems
OP162/OP262/OP462
14
REV. D
Spice Macro-Model
* OP162/OP262/OP462 SPICE Macro-model
* 7/96, Ver. 1
* Troy Murphy / ADSC
*
* Copyright 1996 by Analog Devices
*
* Refer to "README.DOC" file for License Statement. Use of this model
* indicates your acceptance of the terms and provisions in the License
* Statement
*
* Node Assignments
*
noninverting input
*
|
inverting input
*
|
|
positive supply
*
|
|
|
negative supply
*
|
|
|
|
output
*
|
|
|
|
|
*
|
|
|
|
|
.SUBCKT OP162
1
2
99
50
45
*
*INPUT STAGE
*
Q1
5
7
3
PIX 5
Q2
6
2
4
PIX 5
Ios
1
2
1.25E-9
I1
99
15
85E-6
EOS 7
1
POLY(1)
(14, 20)
45E-6 1
RC1 5
50
3.035E+3
RC2 6
50
3.035E+3
RE1 3
15
607
RE2 4
15
607
C1
5
6
600E-15
D1
3
8
DX
D2
4
9
DX
V1
99
8
DC 1
V2
99
9
DC 1
*
* 1st GAIN STAGE
*
EREF 98 0
(20, 0)
1
G1
98 10 (5, 6)
10.5
R1
10 98 1
C2
10 98 3.3E-9
*
* COMMON-MODE STAGE WITH ZERO AT 4kHz
*
ECM
13 98 POLY (2)
(1, 98)
(2, 98)
0
0.5
0.5
R2
13 14 1E+6
R3
14 98 70
C3
13 14 80E-12
*
* POLE AT 1.5MHz, ZERO AT 3MHz
*
G2
21 98 (10, 98)
.588E-6
R4
21 98 1.7E6
R5
21 22 1.7E6
C4
22 98 31.21E-15
*
* POLE AT 6MHz, ZERO AT 3MHz
*
E1
23
98
(21, 98)
2
R6
23
24
53E+3
R7
24
98
53E+3
C5
23
24
1E-12
*
* SECOND GAIN STAGE
*
G3
25
98
(24, 98)
40E-6
R8
25
98
1.65E+6
D3
25
99
DX
D4
50
25
DX
*
* OUTPUT STAGE
*
GSY 99
50
POLY (1)
(99, 50)
277.5E-6 7.5E-6
R9
99
20
100E3
R10 20
50
100E3
Q3
45
41
99
POUT
4
Q4
45
43
50
NOUT 2
EB1 99
40
POLY (1)
(98, 25)
0.70366
1
EB2 42
50
POLY (1)
(25, 98)
0.73419
1
RB1 40
41
500
RB2 42
43
500
CF
45
25
11E-12
D5
46
99
DX
D6
47
43
DX
V3
46
41
0.7
V4
47
50
0.7
.
MODEL
PIX
PNP (Bf=117.7)
.MODEL POUT PNP (BF=119, IS=2.782E-17, VAF=28, KF=3E-7)
.MODEL NOUT NPN (BF=110, IS=1.786E-17, VAF=90, KF=3E-7)
.MODEL DX
D()
.ENDS
15
REV. D
OP162/OP262/OP462
OUTLINE DIMENSIONS
8-Lead Standard Small Outline Package [SOIC]
Narrow Body
(RN-8)
Dimensions shown in millimeters and (inches)
0.25 (0.0098)
0.19 (0.0075)
1.27 (0.0500)
0.41 (0.0160)
0.50 (0.0196)
0.25 (0.0099)
45
8
0
1.75 (0.0688)
1.35 (0.0532)
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0040)
8
5
4
1
5.00 (0.1968)
4.80 (0.1890)
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
6.20 (0.2440)
5.80 (0.2284)
0.51 (0.0201)
0.33 (0.0130)
COPLANARITY
0.10
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MS-012AA
14-Lead Standard Small Outline Package [SOIC]
Narrow Body
(RN-14)
Dimensions shown in millimeters and (inches)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COPLANARITY
0.10
14
8
7
1
6.20 (0.2441)
5.80 (0.2283)
4.00 (0.1575)
3.80 (0.1496)
8.75 (0.3445)
8.55 (0.3366)
1.27 (0.0500)
BSC
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0039)
0.51 (0.0201)
0.33 (0.0130)
1.75 (0.0689)
1.35 (0.0531)
8
0
0.50 (0.0197)
0.25 (0.0098)
45
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.19 (0.0075)
14-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-14)
Dimensions shown in millimeters
4.50
4.40
4.30
14
8
7
1
6.40
BSC
PIN 1
5.10
5.00
4.90
0.65
BSC
SEATING
PLANE
0.15
0.05
0.30
0.19
1.20
MAX
1.05
1.00
0.80
0.20
0.09
8
0
0.75
0.60
0.45
COMPLIANT TO JEDEC STANDARDS MO-153AB-1
COPLANARITY
0.10
8-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-8)
Dimensions shown in millimeters
8
5
4
1
PIN 1
0.65
BSC
SEATING
PLANE
0.15
0.05
0.30
0.19
1.20
MAX
0.20
0.09
8
0
6.40 BSC
0.75
0.60
0.45
4.50
4.40
4.30
3.10
3.00
2.90
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153AA
C00288010/02(D)
PRINTED IN U.S.A.
16
Revision History
Location
Page
10/02--Data Sheet changed from REV. C to REV. D.
Deleted 8-Lead Plastic DIP (N-8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Universal
Deleted 14-Lead Plastic DIP (N-14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Universal
Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Edits to Figure 30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Edits to Figure 31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
OP162/OP262/OP462
REV. D