REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
a
OP221
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
Analog Devices, Inc., 2002
Dual Low Power Operational Amplifier,
Single or Dual Supply
FEATURES
Excellent TCVos Match, 2 V/ C Max
Low Input Offset Voltage, 150 V Max
Low Supply Current, 550 A Max
Single Supply Operation, 5 V to 30 V
Low Input Offset Voltage Drift, 0.75 V/ C
High Open-Loop Gain, 1500 V/mV Min
High PSRR, 3 V/V
Wide Common-Mode Voltage
Range, V to within 1.5 V of V+
Pin Compatible with 1458, LM158, LM2904
Available in Die Form
GENERAL DESCRIPTION
The OP221 is a monolithic dual operational amplifier that can
be used either in single or dual supply operation. The wide
supply voltage range, wide input voltage range, and low supply
current drain of the OP221 make it well-suited for operation
from batteries or unregulated power supplies.
The excellent specifications of the individual amplifiers combined
with the tight matching and temperature tracking between channels
SIMPLIFIED SCHEMATIC
Q1
IN
+IN
*ACCESSIBLE IN CHIP FORM ONLY
Q3
Q4
Q5
Q6
Q2
Q7
Q9
Q10
Q12
Q11
Q4
Q13
NULL*
Q26
Q28
Q27
Q29
Q33
V+
OUTPUT
V
8-Lead SO
(S-Suffix)
8
7
6
5
1
2
3
4
NC = NO CONNECT
+IN A
V
+IN B
IN A
OUT A
V+
OUT B
IN B
8-Lead
HERMETIC DIP
(Z-Suffix)
8
7
6
5
1
2
3
4
NC = NO CONNECT
+IN A
V
+IN B
IN A
OUT A
V+
IN B
OUT B
PIN CONNECTIONS
provide high performance in instrumentation amplifier designs.
The individual amplifiers feature very low input offset voltage,
low offset voltage drift, low noise voltage, and low bias current.
They are fully compensated and protected.
Matching between channels is provided on all critical parameters
including input offset voltage, tracking of offset voltage vs. tem-
perature, non-inverting bias currents, and common-mode rejection.
REV. A
2
OP221SPECIFICATIONS
.
OP221A/E
OP221G
Parameter
Symbol
Conditions
Min
Typ
Max
Min
Typ
Max
Unit
Input Offset Voltage V
OS
75
150
250
500
V
Input Offset Current Ios
V
CM
= 0
0.5
3
1.5
7
nA
Input Bias Current
I
B
V
CM
= 0
55
100
70
120
nA
Input Voltage Range IVR
V+ = 5 V, V = 0 V (Note 2)
0/3.5
0/3.5
V
V
S
=
15 V
15/13.5
15/13.5
Common-Mode
CMRR
V+ = 5 V, V = 0 V
Rejection Ratio
0 V
V
CM
3.5 V
90
100
75
85
V
S
=
15 V
dB
15 V
V
CM
13.5 V
95
100
80
90
Power Supply
PSRR
V
S
=
2.5 V to 15 V
3
10
32
100
V/V
Rejection Ratio
V = 0 V, V+ = 5 V to 30 V
6
18
57
180
Large-Signal
Avo
V
S
=
15 V, R
L
= 10 k
Voltage Gain
V
O
=
10 V
1500
800
V/mV
Output Voltage
V
O
V+ = 5 V, V = 0 V
0.7/4.1
0.8/4
V
Swing
R
L
= 10 k
V
S
= 15 V, R
L
= 10 k
13.8
13.5
Slew Rate
SR
R
L
= 10 k
(Note 1)
0.2
0 3
0.2
0.3
V/
S
Bandwidth
BW
600
600
kHz
Supply Current
I
SY
V
S
=
2.5 V, No Load
450
550
550
650
A
(Both Amplifiers)
V
S
=
15 V, No Load
600
800
850
900
NOTES
1
Sample tested.
2
Guaranteed by CMRR test limits.
(Electrical Characteristics at V
s
= 2.5 V to 15 V, T
A
= 25 C, unless otherwise noted.)
REV. A
3
OP221
SPECIFICATIONS
(Electrical Characteristics at V
S
= 2.5 V to 15 V, 55 C
T
A
+125 C for OP221A,
25 C
T
A
+85 C for OP221E, 40 C T
A
+85 C for OP221G, unless otherwise noted.)
.
OP221A/E
OP221G
Parameter
Symbol
Conditions
Min
Typ
Max
Min
Typ
Max
Unit
Average Input
TCV
OS
0.75
1.5
2
3
V/C
Offset Voltage
Input Offset Voltage
V
OS
150
300
400
700
V
Input Offset Current
I
OS
V
CM
= 0
1
5
2
10
nA
Input Bias Current
I
B
V
CM
= 0
55
100
80
140
nA
Input Voltage Range
IVR
V+ = 5 V, V = 0 V (Note 2)
0/3.2
0/3.2
V
V
S
=
15 V
15/13.2
15/13.2
Common-Mode
CMRR
V+ = 5 V, V = 0 V
Rejection Ratio
0 V
V
CM
3.5 V
85
90
70
80
V
S
=
15 V
dB
15 V
V
CM
13.5 V
90
95
75
85
Power Supply
PSRR
V
S
=
2.5 V to 15 V
6
18
57
180
V/V
Rejection Ratio
V = 0 V, V+ = 5 V to 30 V
10
32
100
320
Large-Signal
A
VO
V
S
=
15 V, R
L
= 10 k
Voltage Gain
V
O
=
10 V
1000
600
V/mV
Output Voltage
V
O
V+ = 5 V, V = 0 V
0.8/3.8
0.9/3.7
Swing
R
L
= 10 k
V
V
S
= 15 V, R
L
= 10 k
13.5
13.2
Supply Current
I
SY
V
S
=
2.5 V, No Load
500
650
600
750
A
(Both Amplifiers)
V
S
=
15 V, No Load
700
900
950
1000
NOTES
1
Sample tested.
2
Guaranteed by CMRR test limits.
.
OP221A/E
OP221G
Parameter
Symbol
Conditions
Min
Typ
Max
Min
Typ
Max
Unit
Input Offset
Voltage Match
V
OS
50
200
250
600
V
Average Noninverting
Bias Current
I
B
+
80
120
nA
Noninverting Input
I
OS
+
2
5
4
10
nA
Offset Current
Common-Mode
Rejection Ratio
CMRR V
CM
= 15 V to 13.5 V
92
72
dB
Match (Note 1)
Power Supply
Rejection Ratio
PSRR
V
S
=
2.5 V to 15 V
14
140
V/V
Match (Note 1)
Matching Characteristics at V
s
= 15 V, T
A
= 25 C, unless otherwise noted.
REV. A
4
OP221SPECIFICATIONS
.
OP221A/E
OP221G
Parameter
Symbol
Conditions
Min
Typ
Max
Min
Typ
Max
Unit
Input Offset
Voltage Match
V
OS
100
400
400
800
V
Average Noninverting I
B
+
V
CM
= 0
100
140
nA
Bias Current
Input Offset
IC
V
OS
1
2
3
5
VC
Voltage Tracking
Noninverting Input
I
OS
+
V
CM
= 0
3
7
6
12
nA
Offset Current
Common-Mode
Rejection Ratio
CMRR V
CM
= 15 V to 13.2 V
87
90
72
80
dB
Match (Note 1)
Power Supply
Rejection Ratio
PSRR
26
140
V/V
Match (Note 1)
NOTES
1
CMRR is 20 log
10
V
CM
/
CME, where V
CM
is the voltage applied to both noninverting inputs and
CME is the difference in common-mode input-referred error.
2
PSRR is: Input-Referred Differential Error
V
S
(Matching Characteristics at V
s
= 15 V, 55 C
T
A
+125 C for OP221A,
25 C
T
A
+85 C for OP221E, 40 C T
A
+85 C for OP221G, unless otherwise noted.
Grades E and G are sample tested.)
.
OP221N
Parameter
Symbol
Conditions
Limit
Unit
Input Offset Voltage
V
OS
200
V Max
Input Offset Current
I
OS
V
CM
= 0
3.5
nA Max
Input Bias Current
I
B
V
CM
= 0
85
nA Max
Input Voltage Range
IVR
V+ = 5 V, V = 0 V
0/3.5
V Min/Max
V
S
=
15 V
15/13.5
V Min
Common-Mode
CMRR
V = 0 V, V+ = 5 V,
88
Rejection Ratio
0 V
V
CM
3.5 V
V
S
=
15 V
dB Min
15 V
V
CM
13.5 V
93
Power Supply
PSRR
V
S
=
2.5 V to 15 V
12.5
Rejection Ratio
V = 0 V, V+ = 5 V to 30 V
22.5
V/mV Min
Large-Signal
Avo
V
S
=
15 V
1500
Voltage Gain
R
L
= 10 k
V/mV Max
Output Voltage Swing
V
O
V+ = 5 V, V = 0 V, R
L
= 10 k
0.7/4.1
V Min/Max
V
S
= 15 V, R
L
= 10 k
13.8
V Min
Supply Current
I
SY
V
S
=
2.5 V, No Load
560
A Max
(Both Amplifiers)
V
S
=
15 V, No Load
810
NOTE
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed
for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.
Wafer Test Limits at V
s
= 2.5 V to 15 V, T
A
= 25 C, unless otherwise noted.
REV. A
OP221
5
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the OP221 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ABSOLUTE MAXIMUM RATINGS (Note 1)
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18 V
Differential Input Voltage . . . . . . . . . . 30 V or Supply Voltage
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . Supply Voltage
Output Short-Circuit Duration . . . . . . . . . . . . . . . . Indefinite
Storage Temperature Range . . . . . . . . . . . . 65
C to +150C
Operating Temperature Range
OP221A . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
C to +125C
OP221E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
C to +85C
OP221G . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
C to +85C
Lead Temperature (Soldering 60 sec) . . . . . . . . . . . . . . 300
C
Junction Temperature (T
J
) . . . . . . . . . . . . . 65
C to +150C
Figure 1. Dice Characteristics
Package Type
JA
(Note 2)
JC
Unit
8-Lead Hermetic DIP (Z)
148
16
C/W
8-Lead Plastic DIP (P)
103
43
C/W
8-Lead SO (S)
158
43
C/W
NOTES
1
Absolute maximum ratings apply to both DICE and packaged parts, unless
otherwise noted.
2
JA
is specified for worst case mounting conditions, i.e.,
JA
is specified for device
in socket for TO, Cerdip, and PDIP packages; elA is specified for device soldered
to printed circuit board for SO package.
ORDERING INFORMATION
1,2
T
A
= +25 C
Packages
Operating
Package
V
OS
MAX
Cerdip
Plastic
Temperature
Options
( V)
8-Lead
8-Lead
Range
150
OP221AZ
3
MIL
Q-8
150
OP221 EZ
3
IND
300
500
500
OP221GP
3
XIND
R-8
500
OP221GS
XIND
1
Burn-in is available on commercial and industrial temperature range parts in CerDIP, plastic DIP, and
TO-can packages.
2
For devices processed in total compliance to MIL-STD-883, add/883 after part number. Consult factory
for 883 data sheet.
3
Not for new design, obsolete April 2002.
REV. A
Typical Perfomance Characteristics OP221
6
TEMPERATURE C
OPEN-LOOP GAIN
dB
140
50
120
100
80
60
40
20
0
25
0
25
50
75
100
125
dc
10Hz
100Hz
1kHz
V
S
= 15V
TPC 1. Open-Loop Gain at
15 V vs.
Temperature
FREQUENCY Hz
OPEN-LOOP GAIN
dB
120
0
0.1
80
60
40
20
100
1
10
100
1k
10k 100k 1M
10M
V
S
= 5V
V
S
= 15V
TPC 4. Open-Loop Gain at
15 V vs.
Frequency
TEMPERATURE C
PHASE MARGIN
Degrees
55
50
50
45
40
0.35
0.30
0.25
0.20
25
0
25
50
75
100
125
850k
800k
750k
700k
650k
GAIN B
AND
WIDTH
Hz
SLEW RA
TE
V/
sec
SLEW RATE
GAIN BANDWIDTH
PHASE MARGIN
V
S
= 15V
TPC 7. Phase Margin, Gain Bandwidth,
and Slew Rate vs. Temperature
TEMPERATURE C
OPEN-LOOP GAIN
dB
140
50
120
100
80
60
40
20
0
25
0
25
50
75
100
125
dc
10Hz
100Hz
1kHz
V
S
= 15V
TPC 2. Open-Loop Gain at
5 V vs.
Temperature
FREQUENCY Hz
1
10
100
CLOSED-LOOP GAIN
dB
70
10
60
30
20
10
0
50
40
1k
10k
100k
1M 10M
TPC 5. Closed-Loop Gain vs.
Frequency
FREQUENCY Hz
PSRR
dB
120
10
+PSRR
PSRR
100
80
60
40
20
0
T
A
= 25 C
V
S
= 15V
100
1k
10k
100k
TPC 8. PSRR vs. Frequency
SUPPLY VOLTAGE V
OPEN-LOOP GAIN
dB
140
0
120
100
80
60
40
20
0
5
10
15
R
L
= 15k
T
A
= 25 C
TPC 3. Open-Loop Gain at vs.
Supply Voltage
FREQUENCY Hz
V
O
L
T
A
GE GAIN
dB
25
10
100k
1M
10M
5
PHASE SHIFT
Degrees
20
15
10
0
5
80
220
200
180
140
160
120
100
T
A
= 25 C
V
S
= 15V
GAIN
PHASE
m = 42
TPC 6. Gain and Phase Shift vs.
Frequency
CMRR
Hz
T
A
= 25 C
V
S
= 15V
FREQUENCY Hz
120
1
100
80
60
40
20
0
10
100
1k
10k
100k
TPC 9. CMRR vs. Frequency
REV. A
OP221
7
FREQUENCY Hz
PEAK-T
O
-PEAK AMPLITUTDE
V
30
1K
1M
10k
100k
28
24
20
16
12
8
4
0
T
A
= 25 C
V
S
= 15V
R
L
= 10k
TPC 10. Maximum Output Swing
vs. Frequency
FREQUENCY Hz
VOLTAGE
NOISE
nV/
Hz
1
1k
10
100
100
10
80
70
60
50
40
20
30
TPC 13. Voltage Noise Density vs.
Frequency
LOAD RESISTANCE
MAXIMUM OUTPUT
V
16
100
100k
1k
10k
14
12
10
8
6
4
2
T
A
= 25 C
V
S
= 15V
POSITIVE
NEGATIVE
0
TPC 11. Maximum Output Voltage
vs. Load Resistance
FREQUENCY Hz
CURRENT NOISE
pA
Hz
10
0.1
1
1k
1.0
10
100
TPC 13. Current Noise Density vs.
Frequency
LOAD RESISTANCE
MAXIMUM OUTPUT
V
100
100k
1k
10k
2.0
1.0
T
A
= 25 C
V
S
= 2.5V
NEGATIVE
POSITIVE
0
TPC 12. Maximum Output Voltage
vs. Load Resistance
REV. A
OP221
8
Figure 3a. Inverting Step Response
Figure 3b. Inverting Step Response
INPUT
OUTPUT
10k
10k
Figure 5. TBD.
Figure 2a. Noninverting Step Response
Figure 2b. Noninverting Step Response
INPUT
OUTPUT
10k
Figure 4. TBD.
REV. A
OP221
9
SPECIAL NOTES ON THE APPLICATION OF DUAL
MATCHED OPERATIONAL AMPLIFIERS
Advantages of Dual Monolithic Operational Amplifiers
Dual matched operational amplifiers provide the engineer with a
powerful tool for designing instrumentation amplifiers and many
other differential-input circuits. These designs are based on the
principle that careful matching between two operational amplifiers
can minimize the effect of dc errors in the individual amplifiers.
Reference to the circuit shown in Figure 6, a differential-in,
differential-out amplifier, shows how the reductions in error can
be accomplished. Assuming the resistors used are ideally matched,
the gain of each side will be identical. If the offset voltages of
each amplifier are perfectly matched, then the net differential
voltage at the amplifier's output will be zero. Note that the output
offset error of this amplifier is not a function of the offset voltage
of the individual amplifiers, but only a function of the difference
(degree of matching) between the amplifiers' offset voltages. This
error-cancellation principle holds for a considerable number of
input referred error parameters--offset voltage, offset voltage
drift, inverting and noninverting bias currents, common mode
and power supply rejection ratios. Note also that the impedances
of each input, both common-mode and differential-mode, are
high and tightly matched, an important feature not practical with
single operation amplifier circuits.
INPUT
OUTPUT
SIDE
`A'
SIDE
`R'
R1
R2
R3
R4
OP221
+
+
Figure 6. Differential-In, Differential-Out Amplifier
INSTRUMENTATION AMPLIFIER APPLICATIONS
Two-Op Amp Configuration
The two-op amp circuit (Figure 7) is recommended where the
common-mode input voltage range is relatively limited; the
common-mode and differential voltage both appear at V1. The
high open-loop gain of the OP221 is very important in achieving
good CMRR in this configuration. Finite open-loop gain of A1
(Ao1) causes undesired feedthrough of the common-mode input.
For Ad/Ao, << 1, the common-mode error (CME) at the out-
put due to this effect is approximately (2 Ad/Ao1) x VCM. This
circuit features independent adjustment of CMRR and differ-
ential gain.
Three-Op Amp Configuration
The three-op amp circuit (Figure 8) has increased common-
mode voltage range because the common-mode voltage is not
amplified as it is in Figure 7. The CMR of this amplifier is directly
proportional to the match of the CMR of the input op amps. CMRR
can be raised even further by trimming the output stage resistors.
R1
R2
GAIN
ADJ
R0
V1
R3
A1
A2
1/2
OP221
1/2
OP221
V
CM
1/2V
D
V
CM
+ 1/2V
D
A
D
= 2 1+
R1
R0
R4
V
O
A
D
V
D
V
O
=
1 +
1
2
R2
R1
+
R2 + R3
R0
+
V
d
+
VCM
R3
R4
R4
R3
R4
R3
R3
R4
R2
R1
IF R1 = R2 = R3 = R4, THEN V
O
= 2 1 +
V
D
R1
R0
V
d
+
Figure 7. Two-Op Amp Circuit
A1
A2
R1
R2
R0
1/2
OP221
V
CM
1/2V
D
V
O
= 2 1 +
V
D
2R1
R0
A3
1/2
OP221
OP221
R2
R2
V
CM
+ 1/2V
D
V
V+
V
d
V+
V
R2
V
O
R1
V2
V1
Figure 8. Three-Op Amp Circuit
REV. A
OP221
10
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead CERDIP Package
(Q-8)
1
4
8
5
0.310 (7.87)
0.220 (5.59)
PIN 1
0.005 (0.13)
MIN
0.055 (1.4)
MAX
0.100 (2.54) BSC
15
0
0.320 (8.13)
0.290 (7.37)
0.015 (0.38)
0.008 (0.20)
SEATING
PLANE
0.200 (5.08)
MAX
0.405 (10.29) MAX
0.150
(3.81)
MIN
0.200 (5.08)
0.125 (3.18)
0.023 (0.58)
0.014 (0.36)
0.070 (1.78)
0.030 (0.76)
0.060 (1.52)
0.015 (0.38)
8-Lead SOIC Package
(R-8)
0.0098 (0.25)
0.0075 (0.19)
0.0500 (1.27)
0.0160 (0.41)
0.0196 (0.50)
0.0099 (0.25)
45
8
0
0.102 (2.59)
0.094 (2.39)
SEATING
PLANE
0.0098 (0.25)
0.0040 (0.10)
0.0192 (0.49)
0.0138 (0.35)
8
5
4
1
0.1968 (5.00)
0.1890 (4.80)
PIN 1
0.1574 (4.00)
0.1497 (3.80)
0.0500 (1.27)
BSC
0.2440 (6.20)
0.2284 (5.80)
REV. A
OP221
11
Revision History
Location
Page
09/01--Data Sheet changed from REV. 0 to REV. A.
Edits to PIN CONNECTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Global deletion of references to OP221B and OP221C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2, 3, 4
Edits to WAFER TEST LIMITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Edits to PACKAGE TYPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
12
PRINTED IN U.S.A.
C0032401/02(A)
PDF 
ZIP