FUNCTIONAL BLOCK DIAGRAMS
GENERAL DESCRIPTION
The SSM2018T and SSM2118T represent continuing evolu-
tion of the Frey Operational Voltage Controlled Element
(OVCE) topology that permits flexibility in the design of high
performance volume control systems. Voltage (SSM2018T)
and differential current (SSM2118T) output versions are of-
fered, both laser-trimmed for gain core symmetry and offset. As
a result, the SSM2018T is the first professional audio quality
VCA to offer trimless operation. The SSM2118T is ideal for
low noise summing in large VCA based systems.
Due to careful gain core layout, the SSM2018T/SSM2118T
combine the low noise of Class AB topologies with the low dis-
tortion of Class A circuits to offer an unprecedented level of
sonic transparency. Additional features include differential in-
puts, a 140 dB gain range, and a high impedance control port.
The SSM2018T provides an internal current-to-voltage con-
verter; thus no external active components are required. The
SSM2118T has fully differential current outputs that permit
high noise-immunity summing of multiple channels.
Both devices are offered in 16-pin plastic DIP and SOIC pack-
ages and guaranteed for operation over the extended industrial
temperature range of 40
C to +85
C.
*Protected by U.S. Patent Nos. 4,471,320 and 4,560,947.
FEATURES
117 dB Dynamic Range
0.006% Typical THD+N (@ 1 kHz, Unity Gain)
140 dB Gain Range
No External Trimming Required
Differential Inputs
Complementary Gain Outputs
Buffered Control Port
IV Converter On-Chip (SSM2018T)
Differential Current Outputs (SSM2118T)
Low External Parts Count
Low Cost
Trimless
Voltage Controlled Amplifiers
SSM2018T/SSM2118T*
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106,
U.S.A. Tel: 617/329-4700
Fax: 617/326-8703
REV. A
a
V
C
IN
+IN
V
G
V
1G
I
G
I
1G
GAIN
CORE
G
1G
SSM-2018T
V
C
IN
+IN
+I
G
V
1G
I
G
I
1G
GAIN
CORE
G
1G
SSM-2118T
REV. A
2
SSM1018T/SSM2118TSPECIFICATIONS
ELECTRICAL SPECIFICATIONS
Parameter
Conditions
Min
Typ
Max
Units
AUDIO PERFORMANCE
1
Noise
V
IN
= GND, 20 kHz Bandwidth
95
93
dBu
Headroom
Clip Point = 1% THD+N
+22
dBu
Total Harmonic Distortion plus Noise
2nd and 3rd Harmonics Only (+25
C to +85
C)
A
V
= 0 dB, V
IN
= +10 dBu
0.006
0.025
%
A
V
= +20 dB, V
IN
= 10 dBu
0.013
0.04
%
A
V
= 20 dB, V
IN
= +10 dBu
2
0.013
0.04
%
INPUT AMPLIFIER
Bias Current
V
CM
= 0 V
0.25
1
A
Offset Voltage
V
CM
= 0 V
1
15
mV
Offset Current
V
CM
= 0 V
10
100
nA
Input Impedance
4
M
Common-Mode Range
13
V
Gain Bandwidth
VCA Configuration
0.7
MHz
VCP Configuration
14
MHz
Slew Rate
5
V/
s
OUTPUT AMPLIFIER (SSM2018T)
Offset Voltage
V
IN
= 0 V, V
C
= +4 V
1.0
15
mV
Output Voltage Swing
I
OUT
= 1.5 mA
Positive
+10
+13
V
Negative
10
14
V
Minimum Load Resistance
For Full Output Swing
9
k
CONTROL PORT
Bias Current
0.36
1
A
Input Impedance
1
M
Gain Constant
Device Powered in Socket > 60 sec
30
mV/dB
Gain Constant Temperature Coefficient
3500
ppm/
C
Control Feedthrough
0 dB to 40 dB Gain Range
1
4
mV
Maximum Attenuation
V
C
= +4 V
100
dB
POWER SUPPLIES
Supply Voltage Range
5
18
V
Supply Current
11
15
mA
Power Supply Rejection Ratio
80
dB
NOTES
1
SSM2118T tested and characterized using OP275 as current-to-voltage converter, see figure next page.
2
Guaranteed by characterization data and testing at A
V
= 0 dB.
Specifications subject to change without notice.
[V
S
=
15 V, A
V
= 0 dB, R
L
= 100 k
, f = 1 kHz, 0 dBu = 0.775 V rms, simple VCA application
circuit with 18 k
resistors, V
IN
floating, and Class AB gain core bias (R
B
= 150 k
), 40
C < T
A
< +85
C, unless otherwise noted. Typical
specifications apply at T
A
= +25
C.]
REV. A
3
SSM2018T/SSM2118T
ABSOLUTE MAXIMUM RATINGS
1
Supply Voltage
Dual Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18 V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
V
S
Operating Temperature Range . . . . . . . . . . . . . 40
C to +85
C
Storage Temperature . . . . . . . . . . . . . . . . . . . 65
C to +150
C
Junction Temperature (T
J
) . . . . . . . . . . . . . . . . . . . . . +150
C
Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . . . +300
C
THERMAL CHARACTERISTICS
Thermal Resistance
2
16-Pin Plastic DIP
JA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
C/W
JC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
C/W
16-Pin SOIC
JA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
C/W
JC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
C/W
TRANSISTOR COUNT
Number of Transistors
SSM2018T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
SSM2118T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
ESD RATINGS
883 (Human Body) Model . . . . . . . . . . . . . . . . . . . . . . . 500 V
EIAJ Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 V
1
Stresses above those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operation section of this specification is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may affect device reliability.
2
JA
is specified for worst-case conditions, i.e.,
JA
is specified for device in socket
for P-DIP and device soldered in circuit board for SOIC package.
ORDERING GUIDE
Model
Temperature Range
Package Option*
SSM2018TP
40
C to +85
C
N-16
SSM2018TS
40
C to +85
C
R-16
SSM2118TP
40
C to +85
C
N-16
SSM2118TS
40
C to +85
C
R-16
*N = Plastic DIP; R = SOL.
PIN CONFIGURATIONS
16-Lead Plastic DIP
and SOL
16-Lead Plastic DIP
and SOL
+I
1G
V+
BAL
COMP 1
+IN
IN
MODE
V
C
V
I
1G
I
G
V
G
GND
COMP 2
COMP 3
1
2
16
15
5
6
7
12
11
10
3
4
14
13
8
9
TOP VIEW
(Not to Scale)
SSM2018T
V
1G
+I
1G
V+
BAL
COMP 1
+IN
IN
MODE
V
C
V
I
1G
GND
COMP 2
COMP 3
1
2
16
15
5
6
7
12
11
10
3
4
14
13
8
9
TOP VIEW
(Not to Scale)
SSM2118T
V
1G
I
G
+I
G
SSM2018T Typical Application Circuit
SSM2118T Typical Application Circuit
1
F 18k
V
IN+
V
150k
A1
10k
10k
18k
18k
500k
50pF
V
OUT
GLOBAL
SYMMETRY
TRIM
FROM
ADDITIONAL
SSM2118Ts
V
1
F 18k
V
IN
47pF
1
F
3k
V
CONTROL
V+
50pF
*
470k
OPTIONAL
TRIM
47k
47k
A1, A2: OP275
1
2
5
6
7
3
4
8
16
15
12
11
10
14
13
9
SSM2118T
A2
1k
*
FOR MORE THAN 2 SSM2118Ts
WARNING!
ESD SENSITIVE DEVICE
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the SSM2018T/SSM2118T features proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.
V+
1
F
150k
18k
V+
18k
V
IN+
1
F 18k
V
IN
47pF
1
F
50pF
1k
V
CONTROL
3k
V
OUT
V
1
2
16
15
5
6
7
12
11
10
3
4
14
13
8
9
SSM2018T
4
SSM2018T/SSM2118TTypical Characteristics
REV. A
0.1
0.010
0.001
THD + N %
20
100
1k
10k
20k
FREQUENCY Hz
AV = +20dB
AV = 20dB
AV = 0dB
T
A
= +25
C
V
S
=
15V
R
F
= 18k
Figure 1. SSM2018T THD + N Frequency (80 kHz Low-Pass
Filter, for A
V
= 0 dB, V
IN
= 3 V rms; for A
V
= +20 dB,
V
IN
= 0.3 V rms; for A
V
= 20 dB, V
IN
= 3 V rms)
100
0
0.025
30
10
20
0.000
60
40
50
70
80
90
0.020
0.015
0.010
0.005
DISTORTION %
UNITS
T
A
= +25
C
A
V
= 0dB
300 UNITS
V
IN
= 10dBu
V
S
=
15V
Figure 2. SSM2018T Distortion Distribution
1
0.1
0.010
0.001
THD + N %
0.1
1
10
20
AMPLITUDE V
RMS
T
A
= +25
C
R
F
= 18k
V
S
=
15V
Figure 3. SSM2018T THD + N vs. Amplitude (Gain = 0 dB,
f
IN
= 1 kHz, 80 kHz Low-Pass Filter)
1
0.1
0.010
0.001
THD + N %
10m
0.1
1
2
AMPLITUDE V
RMS
T
A
= +25
C
V
S
=
15V
R
F
= 18k
Figure 4. SSM2018T THD + N vs. Amplitude
(Gain = +20 dB, f
IN
=1 kHz, 80 kHz Low-Pass Filter)
1.0
0.01
0.001
60
40
20
20
0.1
0
40
T
A
= +25
C
V
S
=
15V
R
F
= 18k
GAIN dB
THD + N %
Figure 5. SSM2018T THD + N vs. Gain (f
IN
= 1 kHz;
for 60 dB
A
V
20 dB, V
IN
= 10 V rms;
for 0 dB
A
V
+20 dB, V
IN
= 1 V rms)
THD + N %
0.1
0.001
0
12
0.01
T
A
= +25
C
R
F
= 18k
3
6
9
15
18
SUPPLY VOLTAGE Volts
Figure 6. SSM2018T THD + N vs. Supply Voltage
(A
V
= 0 dB, V
IN
= 1 V rms, f
IN
= 1 kHz, 80 kHz
Low-Pass Filter)
REV. A
5
SSM2018T/SSM2118T
LOAD RESISTANCE
MAXIMUM OUTPUT SWING V
PEAK
15
12
0
100
1k
100k
10k
9
6
3
R
F
= 18k
T
A
= +25
C
V
S
=
15V
Figure 10. SSM2018T Maximum Output Swing vs.
Load Resistance, (THD = 1 % max)
100
0
40
30
10
60
20
80
60
40
50
70
80
90
20
0
20
40
T
A
= +25
C
V
S
=
15V
GAIN dB
OUTPUT OFFSET mV
Figure 11. SSM2018T Output Offset vs. Gain
+10
0
15
1k
1M
100k
10k
100
5
10
+5
FREQUENCY Hz
T
A
= +25
C
V
S
=
15V
GAIN dB
0
135
45
90
PHASE Degrees
GAIN
PHASE
Figure 12. SSM2018T Gain/Phase vs. Frequency
Figure 7. SSM2018T Noise Density vs. Frequency
0
15
5
5
10
0
20
20
15
10
SUPPLY VOLTAGE Volts
OUTPUT VOLTAGE SWING V
PEAK
R
L
=
R
L
= 10k
R
F
= 18k
T
A
= +25
C
Figure 8. SSM2018T Maximum Output Swing vs.
Supply Voltage (THD = 1% max)
FREQUENCY Hz
MAXIMUM OUTPUT SWING V
PEAK
R
L
=
R
L
= 10k
R
F
= 18k
T
A
= +25
C
V
S
=
15V
9
0
1k
10k
100k
3
6
12
15
Figure 9. SSM2018T Maximum Output Swing vs.
Frequency (THD = 1 % max)
500
300
0
100
100k
10k
1k
10
200
100
400
FREQUENCY Hz
NOISE DENSITY nV/
Hz
T
A
= +25
C
V
S
=
15V
REV. A
6
SSM2018T/SSM2118TTypical Characteristics
60
40
80
100
1k
10M
1M
100k
10k
20
0
20
40
60
FREQUENCY Hz
T
A
= +25
C
V
S
=
15V
GAIN dB
Figure 13. SSM2018T Gain vs. Frequency
THD + N %
0.1
0.010
0.001
20
100
1k
10k
20k
FREQUENCY Hz
T
A
= +25
C
R
F
= 18k
A
V
= 0dB
A
V
= +20dB
A
V
= 20dB
Figure 14. SSM2118T THD + N Frequency (80 kHz
Low-Pass Filter, for A
V
= 0 dB, V
IN
= 1 V rms;
for A
V
= +20 dB, V
IN
= 0.1 V rms; for A
V
= 20 dB,
V
IN
= 10 V rms)
100
0
0.025
30
10
20
0.000
60
40
50
70
80
90
0.020
0.015
0.010
0.005
DISTORTION %
UNITS
T
A
= +25
C
A
V
= 0dB
300 UNITS
V
IN
= 10dBu
V
S
=
15V
Figure 15. SSM2118T Distortion Distribution
AMPLITUDE V
RMS
T
A
= +25
C
V
S
=
15V
0.1
1
10
20
1
0.1
0.010
0.001
THD + N %
Figure 16. SSM2118T THD + N vs. Amplitude
(Gain = 0 dB, f
IN
= 1 kHz, 80 kHz Low-Pass Filter)
AMPLITUDE V
RMS
T
A
= +25
C
V
S
=
15V
10m
0.1
1
2
1
0.1
0.010
0.001
THD + N %
Figure 17. SSM2118T THD + N vs. Amplitude
(Gain = +20 dB, f
IN
= 1 kHz, 80 kHz Low-Pass Filter)
1.0
0.001
60
40
20
0
+20
+40
0.1
0.01
GAIN dB
THD + N %
T
A
= +25
C
V
S
=
15V
Figure 18. SSM2118T THD + N vs. Gain (f
IN
= 1 kHz;
for 60 dB
A
V
20 dB, V
IN
= 10 V rms;
for 0 dB
A
V
+20 dB, V
IN
= 1 V rms)
REV. A
7
SSM2018T/SSM2118T
SUPPLY VOLTAGE Volts
THD + N %
T
A
= +25
C
0.1
0.01
0.001
0
3
6
9
12
15
18
Figure 19. SSM2118T THD + N vs. Supply Voltage
(A
V
= 0 dB, V
IN
= 1 V rms, f
IN
= 1 kHz, 80 kHz
Low-Pass Filter)
Figure 20. SSM2118T Noise Density vs. Frequency
0
15
5
10
0
5
10
15
20
20
SUPPLY VOLTAGE Volts
OUTPUT VOLTAGE SWING V
PEAK
R
L
=
20
T
A
= +25
C
Figure 21. SSM2118T Maximum Output Swing vs.
Supply Voltage (THD = 1% max)
9
0
1k
10k
100k
3
6
12
15
FREQUENCY Hz
MAXIMUM OUTPUT SWING V
PEAK
T
A
= +25
C
V
S
=
15V
Figure 22. SSM2118T Maximum Output Swing vs.
Frequency (THD = 1 % max)
10
0
40
3
1
60
2
80
6
4
5
7
8
9
20
0
20
40
GAIN dB
OUTPUT OFFSET CURRENT A
T
A
= +25
C
V
S
=
15V
Figure 23. SSM2118T Output Offset Current vs. Gain
+10
0
15
1k
1M
100k
10k
100
5
10
+5
FREQUENCY Hz
GAIN dB
0
135
45
90
PHASE Degrees
T
A
= +25
C
V
S
=
15V
PHASE
GAIN
Figure 24. SSM2118T Gain/Phase vs. Frequency
500
300
0
10 100 1k 10k
100k
200
100
400
T
A
= +25
C
V
S
=
15V
FREQUENCY Hz
NOISE DENSITY nV/
Hz
REV. A
8
SSM2018T/SSM2118T
60
40
80
100
1k
10M
1M
100k
10k
20
0
20
40
60
FREQUENCY Hz
GAIN dB
T
A
= +25
C
V
S
=
1.5V
OP275 AS
I/V CONV.
Figure 25. SSM2118T Gain vs. Frequency
0.06
0
100
0.03
0.01
20
0.02
40
0.05
0.04
80
40
20
0
60
TEMPERATURE
C
DISTORTION %
T
A
= +25
C
V
S
=
15V
V
IN
= 10dBu
A
V
= 20dB
AND
V
IN
= 10dBu
A
V
= 20dB
V
IN
= 10dBu
A
V
= 0dB
Figure 26. SSM2018T and SSM2118T Distortion vs.
Temperature
60
110
40
80
100
40
90
60
70
20
0
20
GAIN dB
OUTPUT NOISE dBu
T
A
= +25
C
V
S
=
15V
Figure 27. SSM2018T and SSM2118T Output Noise vs.
Gain (V
IN
= GND, 20 kHz Bandwidth)
100
0
30
10
20
60
40
50
70
80
90
UNITS
CONTROL FEEDTHROUGH mV
T
A
= +25
C
0V < V
C
< 1.2V
FREQ = 0Hz
300 UNITS
3.0
2.0
1.0
0
1.0
2.0
Figure 28. SSM2018T Control Feedthrough Distribution
0
20
100
100
1k
100k
10k
40
60
80
FREQUENCY Hz
V
S
=
15V
T
A
= +25
C
V
C
= 100mV
RMS
CONTROL FEEDTHROUGH dB
Figure 29. SSM2018T and SSM2118T Control
Feedthrough vs. Frequency
3
3
100
0
2
20
1
40
2
1
80
40
20
0
60
TEMPERATURE
C
CONTROL FEEDTHROUGH mV
V
S
=
15V
0V < V
C
< 1.2V
FREQ = 0Hz
Figure 30. SSM2018T and SSM2118T Control
Feedthrough vs. Temperature
REV. A
9
SSM2018T/SSM2118T
20
40
40
100
25
35
20
30
60
80
40
20
0
TEMPERATURE
C
GAIN CONSTANT mV/dB
V
S
=
15V
Figure 31. SSM2018T and SSM2118T Gain Constant vs.
Temperature
28
33
60
30
32
60
31
80
29
40
20
0
20
40
GAIN dB
GAIN CONSTANT mV/dB
T
A
= +25
C
V
S
=
15V
Figure 32. SSM2018T and SSM2118T Gain Constant
Linearity vs. Gain
0.1
0.0
0.4
100
1k
100k
10k
0.1
0.2
0.3
FREQUENCY Hz
GAIN dB
T
A
= +25
C
V
S
=
15V
A
V
= 0dB
V
IN
= 100V
RMS
Figure 33. SSM2018T and SSM2118T Gain Flatness vs.
Frequency
0
40
100
100
100k
10k
1k
10
60
80
20
FREQUENCY Hz
CMRR dB
V
S
=
15V
T
A
= +25
C
Figure 34. SSM2018T and SSM2118T CMRR vs.
Frequency
T
A
= +25
C
15.0
0
15
7.5
2.5
5
5.0
0
12.5
10.0
10
SUPPLY VOLTAGE Volts
SLEW RATE V/s
+ SLEW RATE
SLEW RATE
Figure 35. SSM2018T and SSM2118T Slew Rate vs.
Supply Voltage
0
40
100
100
100k
10k
1k
10
60
80
20
FREQUENCY Hz
+ PSRR
PSRR
V
S
=
15V
T
A
= +25
C
PSRR dB
Figure 36. SSM2018T and SSM2118T PSRR vs. Frequency
REV. A
10
SSM2018T/SSM2118T
to run it in the noninverting single-ended mode. If either input
is unused, the associated 18 k
resistor and coupling capacitor
should be removed to prevent any additional noise.
The common-mode rejection in balanced mode is typically
55 dB up to 1 kHz, decreasing at higher frequencies as shown in
Figure 34. To ensure good CMRR in the balanced configura-
tion, the input resistors must be balanced. For example, a 1%
mismatch results in a CMRR of 40 dB. To achieve 55 dB,
these resistors should have an absolute tolerance match of 0.1%.
The output of the basic VCA is taken from Pin 14, which is the
output of an internal amplifier. Notice that the second voltage
output (Pin 16) is connected to the negative supply. This is
normal and actually disables that output amplifier ensuring that
it will not oscillate and cause interference problems. Shorting
the output to the negative supply does not cause the supply cur-
rent to increase. This amplifier is only used in the "OVCE" ap-
plication explained later.
The control port follows a 30 mV/dB control law. The applica-
tion circuit shows a 3 k
and 1 k
resistor divider from a con-
trol voltage. The choice of these resistors is arbitrary and could
be any values to properly scale the control voltage. In fact, these
resistors could be omitted if the control voltage is already prop-
erly scaled. The 1
F capacitor is in place to provide some fil-
tering of the control signal. Although the control feedthrough is
trimmed at the factory, the feedthrough increases with fre-
quency (Figure 29). Thus, high frequency noise can
feedthrough and add to the noise of the VCA. Filtering the
control signal helps minimize this source of noise.
Theory of Operation of the SSM2018T
The SSM2018T has the same internal circuitry as the original
SSM2018. The detailed diagram in Figure 38 shows the main
components of the VCA. The essence of the SSM2018T is the
gain core, which is comprised of two differential pairs (Q1Q4).
When the control voltage, V
C
, is adjusted, current through the
gain core is steered to one side or the other of the two differen-
tial pairs. The tail current for these differential pairs is set by
the mode bias of the VCA (Class A or AB), which is labeled as
I
M
in the diagram. I
M
is then modulated by a current propor-
tional to the input voltage, labeled I
S
. For a positive input volt-
age, more current is steered (by the "Splitter") to the left
differential pair, and the opposite is true for a negative input.
To understand how the gain control works, a simple example is
best. Take the case of a positive control voltage on Pin 11. No-
tice that the bases of Q2 and Q3 are connected to ground via a
200
resistor. A positive control voltage produces a positive
voltage on the bases of Q1 and Q4. Concentrating on the left
most differential pair, this raises the base voltage of Q1 above
that of Q2. Thus, more of the tail current is steered through Q1
than through Q2. The current from the collector of Q2 flows
through the external 18 k
feedback resistor around amplifier
A3. When this current is reduced, the output voltage is also re-
duced. Thus, a positive control voltage results in an attenuation
of the input signal, which explains why the gain constant is
negative.
The collector currents of Q2 and Q3 produce the output volt-
age. The output of Q3 is mirrored by amplifier A1 to add to the
overall output voltage. On the other hand, the collector cur-
rents of Q1 and Q4 are used for feedback to the differential in-
puts. Because Pins 6 and 4 are shorted together, any input
voltage produces an input current which flows into Pin 4. The
APPLICATIONS
The SSM2018T is a trimless Voltage Controlled Amplifier
(VCA) for volume control in audio systems. The SSM2018T is
identical to the original SSM2018 in functionality and pinout;
however, it is the first professional quality audio VCA
in the marketplace that does not require an external trim-
ming potentiometer to minimize distortion. Instead, the
SSM2018T is laser trimmed before it is packaged to ensure the
specified THD and control feedthrough performance. This has
a significant savings in not only the cost of external trimming
potentiometers, but also the manufacturing cost of performing
the trimming during production.
The SSM2118T is identical to the SSM2018T except that dif-
ferential current outputs are provided as opposed to a voltage
output. This output configuration is ideal for bus summing ap-
plications where multiple audio signals are summed together.
These signals often require long lead lengths or cable runs to
reach the summing stage. Transmitting the signals in a differen-
tial current mode minimizes the chance for noise pickup and for
line impedances to upset the balance of the system. The
SSM2118T is also factory trimmed to minimize distortion and
control feedthrough. Thus, no individual trim is required for
each part. One global trim at the summing amplifier stage may
be necessary to properly balance the resistors in this stage, as ex-
plained later.
Basic VCA Configuration
The primary application circuit for the SSM2018T is the basic
VCA configuration, which is shown in Figure 37. This configu-
ration uses differential current feedback to realize the VCA. A
complete description of the internal circuitry of the VCA and
this configuration is given in the Theory of Operation section
below. The SSM2018T and SSM2118T are trimmed at the factory
for operation in the basic VCA configuration with class AB biasing.
Thus, for optimal distortion and control feedthrough perfor-
mance, the same configuration and biasing should be used. All
of the graphs for the SSM2018T in the data sheet have been
measured using the circuit of Figure 37.
V+
1
F
R
B
150k
18k
V+
18k
V
IN+
1
F 18k
V
IN
47pF
1
F
50pF
1k
V
CONTROL
3k
V
OUT
V
1
2
16
15
5
6
7
12
11
10
3
4
14
13
8
9
SSM2018T
Figure 37. SSM2018T Basic VCA Application Circuit
In the simple VCA configuration, the SSM2018T inputs are at a
virtual ground. Thus, 18 k
resistors are required to convert
the input voltages to input currents. The schematic also shows
ac coupling capacitors. These are inserted to minimize dc off-
sets generated by bias current through the resistors. Without the
capacitors, the dc offset due to the input bias current is typically
5 mV. The input stage has the flexibility to run either inverting,
noninverting, or balanced. The most common configuration is
REV. A
11
SSM2018T/SSM2118T
same is true for the inverting input, which is connected to Pin 1.
The overall feedback ensures that the current flowing through
the input resistors is balanced by the collector currents in Q1
and Q4.
Basic VCA Configuration for the SSM2118T
The SSM2118T behaves very much in the same way as the
SSM2018T except that it has differential current outputs in-
stead of a voltage output. The basic VCA configuration is
shown in Figure 39. A dual output amplifier is needed to re-
place the internal amplifiers in the SSM2018T. However, mul-
tiple SSM2118Ts can share the output amplifiers. The op amps
are configured so that the SSM2118T's output current is flow-
ing into a virtual ground. This same virtual ground is presented
to all the VCAs, allowing their currents to be summed without
interaction.
1
F 18k
V
IN+
V
150k
A1
10k
10k
18k
18k
500k
50pF
V
OUT
GLOBAL
SYMMETRY
TRIM
FROM
ADDITIONAL
SSM2118Ts
V
1
F 18k
V
IN
47pF
1
F
3k
V
CONTROL
V+
50pF
*
470k
OPTIONAL
TRIM
47k
47k
A1, A2: OP275
1
2
5
6
7
3
4
8
16
15
12
11
10
14
13
9
SSM2118T
A2
1k
*
FOR MORE THAN 2 SSM2118Ts
Figure 39. SSM2118T Typical Bus Summing Application
A global symmetry trim may be necessary, but since it is at the
output amplifiers, only one trim is needed for any number of
SSM2118Ts connected to the summing bus. This trim bal-
ances the resistors around the two amplifiers. If precision,
matched resistors are used, the trim can be removed. However,
to achieve 0.006% distortion, these resistors need to be matched
to approximately 0.01%.
If the choice is made to perform the trim, then one of two meth-
ods may be used. The first method minimizes the distortion of
an audio signal with the SSM2118T in the circuit. To perform
the trim, a 0 dBu, 1 kHz sine wave is applied to one of the
VCAs, and the output distortion is monitored. As the symmetry
trim is adjusted, the output distortion will vary. The optimal
adjustment produces the lowest distortion over the entire trim
range. The second method is to insert a common mode signal
by connecting two 47 k
resistors (matched to 0.01%) to the
inverting inputs of each amplifier, as shown in the Figure 39.
The signal is typically a 0 dBu, 1 kHz sine wave, although other
signals can be used. The output is monitored with an oscillo-
scope, and the potentiometer is adjusted to achieve a minimum
output signal.
The SSM2118T has the exact same input and gain core con-
struction as the SSM2018T. Thus, any discussion of these por-
tions of the SSM2018T apply equally to the SSM2118T. The
main difference, which is apparent by comparing Figure 40 to
Figure 38, is the removal of two output amplifiers, A1 and A3.
Instead, the output currents come directly from the collectors of
Q2 and Q3. Notice that the two external amplifiers in Figure
39 are configured the same as the internal amplifiers in the
SSM2018T.
Two important characteristics of these current outputs must be
considered: the output compliance and the effects of capacitive
loading. Normally, the outputs are connected to a virtual
ground node at the summing stage, which is biased at ground.
This bias point can be altered somewhat. The part maintains
good distortion performance for an output compliance from
A4
Q3 Q4
Q1 Q2
200
1G
G
G
1G
200
1.8k
GAIN
CORE
14
8
5
2
COMP 1
COMPENSATION
NETWORK
9
V
REF
Im
SPLITTER
A1
A3
V
G
+I
1-G
3
1
15
4
16
11
13
12
BAL
I
1-G
V
1-G
V
C
GND
MODE
I
G
COMP 3
COMP 2
V+
7
6
10
V
+IN
IN
Im+(Is)
2
Im(Is)
2
A2
A4
Figure 38. SSM2018T Detailed Functional Diagram
REV. A
12
SSM2018T/SSM2118T
A2
A4
Q3 Q4
Q1 Q2
200
1G
G
G
1G
200
1.8k
GAIN
CORE
14
8
5
16
COMP 2
COMP 1
9
V
REF
Im
SPLITTER
+I
G
3
1
15
4
2
11
13
12
BAL
I
1G
V
1G
V
C
GND
MODE
I
G
COMP 3
7
6
10
V
+IN
IN
+I
1G
V+
COMPENSATION
NETWORK
Im(Is)
2
Im+(Is)
2
A4
0.1 V to +6.0 V. The negative compliance is much smaller be-
cause the gain core transistors (Q1 and Q3) begin to saturate
when the collector potential is brought below their base poten-
tial. These outputs have high immunity to capacitive loads. In
fact, the load on either or both outputs can be as large as 10 nF
with no change in the distortion performance. For values above
10 nF, the distortion does start to increase. For example, a
100 nF load causes the distortion to increase from 0.006% to
0.02% at 1 kHz.
The noise performance of a single SSM2118T with an OP275
output amplifier is shown in Figure 20. When multiple
SSM2118T parts are operated in parallel, the noise does in-
crease by a factor equal to the square root of the number of
parts paralleled. For example, if five parts are in parallel, the
total output noise is 100 nV
(Hz)
5
= 220 nV/
Hz
.
Compensating the SSM2018T and SSM2118T
Both parts employ the same compensation network. This net-
work uses an adaptive compensation scheme that adjusts the op-
timum compensation level for a given gain. The control voltage
not only adjusts the gain core steering, it also adjusts the com-
pensation. The SSM2018T and SSM2118T have three com-
pensation pins: COMP1, COMP2, and COMP3. COMP3 is
normally left open. Grounding this pin actually defeats the
adaptive compensation circuitry, giving the VCA a fixed com-
pensation point. The only time that this is desirable is when the
VCA has fixed feedback, such as the Voltage Controlled Panner
(VCP) circuit shown later in the data sheet. Thus, for the Basic
VCA circuit or the OVCE circuit, COMP3 should be left open.
A compensation capacitor does need to be added between
COMP1 and COMP2. Because the VCA operates over such a
wide gain range, ideally the compensation should be optimized
for each gain. When the VCA is in high attenuation, there is
very little "loop gain," and the part needs to have high compen-
sation. On the other hand, at high gain, the same compensation
capacitor would overcompensate the part and roll off the high
frequency performance. Thus, the SSM2018T and SSM2118T
employ a patented adaptive compensation circuit. The compen-
sation capacitor is "Miller" connected between the base and col-
lector of an internal transistor. By changing the gain of this
transistor via the control voltage, the compensation is changed.
Increasing the compensation capacitor causes the frequency re-
sponse and slew rate to decrease, which will tend to cause high
frequency distortion to increase. For the basic VCA circuit,
47 pF was chosen as the optimal value. The OVCE circuit de-
scribed later uses a 220 pF capacitor. The reason for the in-
crease is to compensate for the extra phase shift from the
additional output amplifier used in the OVCE configuration.
The compensation capacitor can be adjusted over a practical
range from 47 pF to 220 pF, if desired. Below 47 pF, the parts
may oscillate, and above 220 pF the frequency response is sig-
nificantly degraded.
Control Section
As mentioned before, the control voltage on Pin 11 steers the
current through the gain core transistors to set the gain. The
output gain formula is as follows:
V
OUT
=
V
IN
e
(aV
C
)
The exponential term arises from the standard Ebers-Moll
equation describing the relationship of a transistor's collector
current as a function of the base-emitter voltage:
I
C
=
I
S
e
(V
BE
/V
T
)
.
The factor "a" is a function of not only V
T
but also the scaling
due to the resistor divider of the 200
and 1.8 k
resistors
shown in Figures 38 and 40. The resulting expression for "a" is
as follows: a = 1/(10
V
T
) which is approximately equal to four
at room temperature. Substituting a = 4 in the above equation
results in a 28.8 mV/dB control law at room temperature.
The 28.8 mV/dB number is slightly different from the data
sheet specification of 30 mV/dB. The difference arises from
the temperature dependency of the control law. The term V
T
is known as the thermal voltage, and it has a direct dependency
Figure 40. SSM2118T Detailed Functional Diagram
REV. A
13
SSM2018T/SSM2118T
on temperature: V
T
= kT/q (k = Boltzmann's constant =
1.38E-23, q = electron charge = 1.6E-19, and T = absolute
temperature in Kelvin). This temperature dependency leads to
the 3500 ppm/
C drift of the control law. It also means that
the control law changes as the part warms up. Thus, our speci-
fication for the control law states that the part has been powered
up for 60 seconds.
When the part is initially turned on, the temperature of the die
is still at the ambient temperature (25
C for example), but the
power dissipation causes the die to warm up. With
15 V sup-
plies and a supply current of 11 mA, 330 mW is dissipated.
This number is multiplied by
JA
to determine the rise in the
die's temperature. In this case, the die increases from 25
C to
approximately 50
C. A 25
C temperature change causes a
8.25% increase in the gain constant, resulting in a gain constant
of 30 mV/dB. The graph in Figure 31 shows how the gain con-
stant varies over the full temperature range.
Proper Operating Mode for the SSM2018T and SSM2118T
Both parts have the flexibility of operating in either Class A or
Class AB. This is accomplished by adjusting the amount of cur-
rent flowing in the gain core (I
M
in Figure 38). The traditional
trade-off between the two classes is that Class A tends to have
lower THD but higher noise than Class AB. However, by utiliz-
ing well matched gain core transistors, distortion compensation
circuitry, and laser trimming, the SSM2018T and SSM2118T
have excellent THD performance in Class AB. Thus, the parts
offer the best of both worlds in having the low noise of Class AB
with low THD.
Because the parts operate optimally in Class AB, the distortion
trim is performed for this class. To guarantee conformance to the
data sheet THD specifications, both the SSM2018T and SSM2118T
must be operated in Class AB. This does not mean that the parts
cannot be operated in Class A, but the optimal THD trim point
is different for the two classes. Using Class A operation results
in a shift of THD performance from a typical value of 0.006%
to 0.05% without trim. An external potentiometer could be
added to change the trim back to its optimal point as shown in
the OVCE application circuit, but this adds the expense and
time in adjusting a potentiometer.
The class of operation is set by selecting the proper value for R
B
shown in Figure 37. R
B
determines the current flowing into the
MODE input (Pin 12). For class AB operation with
15 V
supplies, R
B
should be 150 k
. This results in a current of 95
A. For other supply voltages, adjust the value of R
B
such that
current remains at 95
A. This current follows the formula:
I
MODE
=
(V
CC
0.7V )
R
B
The factor of 0.7 V arises from the fact that the dc bias on Pin
12 is a diode drop above ground.
Output Drive
The SSM2018T is buffered by an internal op amp to provide a
low impedance output. This output is capable of driving to
within 1.2 V of either rail at 1% distortion for a 100 k
load.
(Note: This 100 k
load is in parallel with the feedback resistor
of 18 k
, so the effective load is 15.3 k
.) For better than
0.01% distortion, the output should remain about 3.5 V away
from either rail as shown in Figure 3. As the graph of output
swing versus load resistance shows (Figure 10), to maintain less
than 1% distortion, the output current should be limited to
approximately
1.3 mA. If higher current drive is required,
then the output should be buffered with a high quality op amp
such as the OP176 or AD797.
The internal amplifiers are compensated for unity gain stability
and are capable of driving a capacitive load up to 4700 pF.
Larger capacitive loads should be isolated from the output of the
SSM2018T by the use of a 50
series resistor.
Upgrading SSM2018 Sockets
The SSM2018T easily replaces the SSM2018 in the basic VCA
configuration. The parts are pin for pin compatible allowing di-
rect replacement. At the same time, the trimming potentiom-
eters for symmetry and offset should be removed, as shown in
Figure 41. Upgrading to the SSM2018T immediately saves the
expense of the potentiometers and the time in production of
trimming for minimum distortion and control feedthrough.
18k
50pF
V+
V
OUT
47pF
NC
1F
1k
3k
V
V+
1F 18k
1F 18k
R
B
: 150k
FOR CLASS AB
NC = NO CONNECT
R
B
V
CONTROL
V
IN+
V
IN
1
2
3
4
5
6
7
8
16
15
14
13
12
10
9
SSM2018T
11
470k
500k
100k
10M
OFFSET
TRIM
V+
V
SYMMETRY
TRIM
REMOVE FOR SSM2018T
Figure 41. Upgrading SSM2018 Sockets
If the SSM2018 is used in the OVCE or VCP configuration, the
SSM2018T can still directly replace it. However, the potenti-
ometers cannot necessarily be removed, as explained in the
OVCE and VCP sections.
Temperature Compensation of the Gain Constant
As explained above, the gain constant has a 3500 ppm/
C tem-
perature drift due to the inherent nature of the control port.
Over the full temperature range of 40
C to +85
C, the drift
causes the gain to change by 7 dB if the part is in a gain of
20 dB. If the application requires that the gain constant be the
same over a wide temperature range, then external temperature
compensation should be employed. The simplest form of com-
pensation is a temperature compensating resistor (TCR), such
as the PT146 from Precision Resistor Co. These elements are
different from a standard thermistor in that they are linear over
temperature to better match the linear drift of the gain constant.
REV. A
14
SSM2018T/SSM2118T
such that full scale produces 80 dB of attenuation. The resistor
divider can be adjusted to provide other attenuation ranges. If a
parallel interface is needed, then the DAC8562 may be used, or
for a dual DAC, the AD8582.
0.1
F
+15V
18k
V
IN
6
DAC8512
8
7
CS
CLR
2
1
0.1
F
18k
50pF
47pF
V
OUT
150k
+15V
15V
0.1
F
+5V
C
CON
1
F
R6
825
R7
1k
0V
V
C
+2.24V
5
LD
3
SCLK
4
SDI
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SSM2018T
NC
NC
NC
NC
NC = NO CONNECT
Figure 44. 12-Bit DAC Controls the VCA Gain
Supply Considerations and Single Supply Operation
The SSM2018T and SSM2118T have a wide operating supply
range. Many of the graphs in this data sheet show the perfor-
mance of the part from
5 V to
18 V. These graphs offer typi-
cal performance specifications and are a good indication of the
parts capabilities. The minimum operating supply voltage is
4.5 V. Below this voltage, the parts are inoperable. Thus, to
account for supply variations, the recommended minimum sup-
ply is
5 V.
The circuits in the data sheet do not show supply decoupling for
simplicity; however, to ensure best performance, each supply
pin should be decoupled with a 0.1
F ceramic (or other low re-
sistance and inductance type) capacitor as close to the package
as possible. This minimizes the chance of supply noise feeding
through the part and causing excessive noise in the audio fre-
quency range.
The SSM2018T and SSM2118T can be operated in single sup-
ply mode as long as the circuit is properly biased. Figure 45
shows the proper configuration, which includes an amplifier to
create a false ground node midway between the supplies. A
high quality, wide bandwidth audio amplifier such as the OP176
or AD797 should be used to ensure a very low impedance
ground over the full audio frequency range. The minimum op-
erating supply for the SSM2018 is
5 V, which gives a mini-
mum single supply of +10 V and ground. The performance of
the circuit with +10 V is identical to graphs that show operation
of the SSM2018T with
5 V supplies.
1F
2k
V
C
(PIN 11)
SSM2018T OR SSM2118T
1k
*
3500ppm/
C
1k
*
3500ppm/
C
CONTROL
VOLTAGE
*PRECISION RESISTOR CO.
10601 75
TH
ST. NORTH
LARGO, FL 34647
(813) 541-5771
Figure 42. Two TCRs Compensate for Temperature Drift
of Gain Constant
+15V
15V
R3
10k
50pF
R4
1k
R5
9k
R1
10k
OP176
R2
10k
1k
*
3500ppm/
C
V
C
(PIN 11)
SSM2018T OR SSM2118T
CONTROL
VOLTAGE
Figure 43. Current Source Allows Temperature Compen-
sation with One TCR
One of the resistors in the divider to the control port can be sub-
stituted with an appropriately chosen TCR to compensate the
SSM2018T or the SSM2118T as shown in Figure 42. Because
the resistor divider effectively cuts the temperature coefficient in
half, two TCRs must be used. The combined drift of the two is
7000 ppm/
C, given an effective drift for to the control voltage
of 3500 ppm/
C. Of course, a single TCR with the appropriate
coefficient can be used. The 3500 ppm parts were chosen be-
cause they are a standard item and do not need to be special
ordered.
In many applications, an op amp is used to drive the control
voltage. If this is the case, it may be more economical to use the
op amp and a single TCR for temperature compensation. The
op amp is configured as a Howland current source as shown in
Figure 43. The current then flows through a single TCR to
create the control voltage. Because the resistor divider is not
present, the temp coefficient is equivalent to the TCR's coef-
ficient. Using this technique, the drift was reduced from
3500 ppm/
C to 150 ppm/
C, which results in a total com-
pensated gain shift of 0.4 dB over the full temperature range at a
gain of
20 dB.
Digital Control of the Gain
A common method of controlling the gain of a VCA is to use a
digital-to-analog converter to set the control voltage. Figure 44
shows a 12-bit DAC, the DAC8512, controlling the SSM2018T
(or SSM2118T). The DAC8512 is a complete 12-bit converter
in an 8-pin package. It includes an on board reference and a
output amplifier to produce an output voltage from 0 V to
+4.095 V, which is 1 mV/bit. Since the voltage is always posi-
tive, this circuit only provides attenuation. The resistor divider
on the output of the DAC8512 is set to scale the output voltage
REV. A
15
SSM2018T/SSM2118T
V+
1
F
R
B
18k
V+
18k
V
IN+
1
F 18k
V
IN
47pF
1
F
50pF
1k
V
CONTROL
3k
V
OUT
1
2
16
15
5
6
7
12
11
10
3
4
14
13
8
9
SSM2018T
V+
OP176
100k
100k
V+
10
F
Figure 45. Single Supply Operation of SSM2018T
Operational Voltage Controlled Element
The SSM2018T has considerable flexibility beyond the basic
VCA circuit utilized throughout this data sheet. The name
"Operational Voltage Controlled Element" comes from the fact
that the part behaves much like an operational amplifier with a
second voltage controlled output. The symbol for the OVCE
connected as a unity gain follower/VCA is shown in Figure 46.
The voltage output labeled V
1G
is fed back to the inverting in-
put just as for an op amp's feedback. The V
G
output is ampli-
fied or attenuated depending upon the control voltage. Because
the OVCE works just like an op amp, the feedback could just as
easily have included resistors to add gain, or a filter network to
add frequency shaping. The full circuit for the OVCE is shown
in Figure 47. Notice that the amplifier whose output (Pin 16)
was originally connected to V
MINUS
is now the output for feed-
back. As mentioned before, because the SSM2018T is trimmed
for the basic VCA configuration, potentiometers are needed for
the OVCE configuration to ensure the best THD and control
feedthrough performance.
If a symmetry trim is to be performed, it should precede the
control feedthrough trim and be done as follows:
1. Apply a 1 kHz sine wave of +10 dBu to the input, with the
control voltage set for unity gain.
2. Adjust the symmetry trim potentiometer to minimize distor-
tion of the output signal.
Next the control feedthrough trim is done as follows:
1. Ground the input signal port and apply a 60 Hz sine wave
to the control port. The sine wave should have its high and
low peaks correspond to the highest gain to be used in the
application and 30 dB of attenuation, respectively. For ex-
ample, a range of +20 dB gain to 30 dB attenuation requires
that the sine wave amplitude ranges between 560 mV and
+840 mV on Pin 11.
2. Adjust the control feedthrough potentiometer to null the sig-
nal seen at the output.
V
IN
V
C
V
G
V
1G
Figure 46. OVCE Follower/VCA Connection
18k
50pF
470k
500k
V+
100k
10M
CONTROL
FEEDTHROUGH
TRIM
V+
V
V
1G
V
G
INPUTS
220pF
NC
V
1F
1k
3k
V
CONTROL
R
B
: 30k
FOR CLASS A
150k
FOR CLASS AB
NC = NO CONNECT
SYMMETRY
TRIM
V+
R
B
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SSM2018T
18k
50pF
Figure 47. OVCE Application Circuit
REV. A
16
SSM2018T/SSM2118T
PRINTED IN U.S.A.
C193757/94
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
16-Pin Plastic DIP (N-16) Package
PIN 1
0.280 (7.11)
0.240 (6.10)
9
16
1
8
0.210
(5.33)
MAX
0.160 (4.06)
0.115 (2.93)
0.022 (0.558)
0.014 (0.356)
0.100 (2.54)
BSC
SEATING
PLANE
0.060 (1.52)
0.015 (0.38)
0.130
(3.30)
MIN
0.070 (1.77)
0.045 (1.15)
0.840 (21.33)
0.745 (18.93)
0.325 (8.25)
0.300 (7.62)
0.015 (0.381)
0.008 (0.204)
0.195 (4.95)
0.115 (2.93)
16-Pin SOIC (R-16) Package
PIN 1
0.2992 (7.60)
0.2914 (7.40)
0.4193 (10.65)
0.3937 (10.00)
1
16
9
8
0.0192 (0.49)
0.0138 (0.35)
0.0500 (1.27)
BSC
0.1043 (2.65)
0.0926 (2.35)
0.4133 (10.50)
0.3977 (10.00)
0.0118 (0.30)
0.0040 (0.10)
0.0500 (1.27)
0.0157 (0.40)
8
0
0.0291 (0.74)
0.0098 (0.25)
x 45
0.0125 (0.32)
0.0091 (0.23)
Voltage Controlled Panner
An interesting circuit that is built with the OVCE building block
is a voltage controlled panner. Figure 48 shows the feedback
connection for the circuit. Notice that the average of both out-
puts is fed back to the input. Thus, the average must be equal
to the input voltage. When the control voltage is set for gain at
V
G
, this causes V
1-G
to attenuate (to keep the average the same).
On the other hand, when V
G
is attenuated, V
1-G
is amplified.
The result is that the control voltage causes the input to "pan"
from one output to the other. The following expressions show
how this circuit works mathematically:
V
G
=
2 K
V
IN
and V
I G
=
2 (1 K )
V
IN
where K varies between 0 and 1 as the control voltage is
changed from full attenuation to full gain respectively. When
V
C
= 0, then K = 0.5 and V
G
= V
1-G
= V
IN
. Again, trimming is
required for best performance. Pin 9 should be grounded. This
is possible because the feedback is constant and the adaptive
network is not needed. The VCP is the only application shown
in this data sheet where Pin 9 is grounded.
V
IN
V
C
V
G
V
1G
18k
18k
Figure 48. Basic VCP Connection
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