Features
eroflex Circuit Technology RISC TurboEngines For The Future SCD5230 REV 1 12/22/98
Block Diagram
s
Full militarized QED RM5230 microprocessor
s
Dual Issue superscalar microprocessor - can issue one
integer and one floating-point instruction per cycle
q
100, 133 and 150 MHz operating frequency Consult
Factory for latest speeds
q
228 Dhrystone2.1 MIPS
q
SPECInt95 4.2 SPECfp95 4.5
s
System interface optomized for embedded
applications
q
32-bit system interface lowers total system cost with up to
87.5 MHz operating frequency
q
High performance write protocols maximize uncached
write bandwidth
q
Operates at processor clock divisors 2 through 8
q
5V tolerant I/O's
q
IEEE 1149.1 JTAG boundary scan
s
Integrated on-chip caches
q
16KB instruction - 2 way set associative
q
16KB data - 2 way set associative
q
Virtually indexed, physically tagged
q
Write-back and write-through on per page basis
q
Early restart on data cache misses
s
Integrated memory management unit
q
Fully associative joint TLB (shared by I and D translations)
q
48 dual entries map 96 pages
q
Variable page size (4KB to 16MB in 4x increments)
s
High-performance floating point unit
q
Single cycle repeat rate for common single precision
operations and some double precision operations
q
Two cycle repeat rate for double precision multiply and
double precision combined multiply-add operations
q
Single cycle repeat rate for single precision combined
multiply-add operation
s
MIPS IV instruction set
q
Floating point multiply-add instruction increases
performance in signal processing and graphics
applications
q
Conditional moves to reduce branch frequency
q
Index address modes (register + register)
s
Embedded application enhancements
q
Specialized DSP integer Multiply-Accumulate instruction
and 3 operand multiply instruction
q
I and D cache locking by set
q
Optional dedicated exception vector for interrupts
s
Fully static CMOS design with power down logic
q
Standby reduced power mode with WAIT instruction
q
2.5 Watts typical with less than 70 mA standby current
s
128-pin Power Quad-4 package (F22),
Consult Factory for
package configuration
Preliminary
Store Buffer
Data Set A
Data Tag A
DTLB Physical
Data Tag B
Instruction Set A
Integer Instruction Register
FP Instruction Register
Instruction Set B
Address Buffer
Instruction Tag A
ITLB Physical
Instruction Tag B
Sys AD
Write Buffer
Read Buffer
Data Set B
DBus
Control
Floating-point
Register File
Joint TLB
Tag
Aux Tag
IntIBus
Floating-point
Coprocessor 0
Unpacker/Packer
MAdd, Add, Sub,Cvt
PC Incrementer
Branch Adder
DVA
Load Aligner
Integer Register File
Integer/Address Adder
Data TLB Virtual
Shifter/Store Aligner
Logic Unit
Integer Multiply, Divide
I
n
t
e
ge
r
C
ont
r
o
l
Instruction TLB Virtual
Fl
oa
t
i
ng
po
i
n
t
C
ont
r
o
l
Phase Lock Loop
Instruction Select
FPIBus
ABus
System/Memory
Control
Program Counter
IVA
Div, SqRt
32-Bit Superscaler Microprocessor
ACT5230
Aeroflex Circuit Technology
SCD5230 REV 1 12/22/98 Plainview NY (516) 694-6700
2
DESCRIPTION
The ACT5230 is a highly integrated superscalar
microprocessor that implements a superset of the
MIPS IV Instruction Set Architecture(ISA). It has a
high performance 64-bit integer unit, a high
throughput, fully pipelined 64-bit floating point unit,
an operating system friendly memory management
unit with a 48-entry fully associative TLB, a 16 KByte
2-way set associative instruction cache, a 16 KByte
2-way set associative data cache, and a
high-performance 32-bit system interface. The
ACT5230 can issue both an integer and a floating
point instruction in the same cycle.
The ACT5230 is ideally suited for high-end
embedded control applications such as
internetworking, high performance image
manipulation, high speed printing, and 3-D
visualization.
HARDWARE OVERVIEW
The ACT5230 offers a high-level of integration
targeted at high-performance embedded
applications. Some of the key elements of the
ACT5230 are briefly described below.
Superscalar Dispatch
The ACT5230 has an efficient asymmetric
superscalar dispatch unit which allows it to issue an
integer instruction and a floating-point computation
instruction simultaneously. With respect to
superscalar issue, integer instructions include alu,
branch, load/store, and floating-point load/store,
while floating-point computation instructions include
floating-point add, subtract, combined multiply-add,
converts, etc. In combination with its high throughput
fully pipelined floating-point execution unit, the
superscalar capability of the ACT5230 provides
unparalleled price/performance in computationally
intensive embedded applications.
CPU Registers
Like all MIPS ISA processors, the ACT5230 CPU
has a simple, clean user visible state consisting of 32
general purpose registers, two special purpose
registers for integer multiplication and division, a
program counter, and no condition code bits.
Pipeline
For integer operations, loads, stores, and other
non-floating-point operations, the ACT5230 uses the
simple 5-stage pipeline also found in the QED
circuits R4600, R4700, and R5000. In addition to this
standard pipeline, the ACT5230 uses an extended
seven stage pipeline for floating-point operations.
Like the QED R5000, the ACT5230 does virtual to
physical translation in parallel with cache access.
Integer Unit
Like the QED R5000, the ACT5230 implements
the MIPS IV Instruction Set Architecture, and is
therefore fully upward compatible with applications
that run on processors implementing the earlier
generation MIPS I-III instruction sets. Additionally,
the ACT5230 includes two implementation specific
instructions not found in the baseline MIPS IV ISA
but that are useful in the embedded market place.
Described in detail in the QED RM5230 datasheet,,
these instructions are integer multiply-accumulate
and 3-operand integer multiply.
The ACT5230 integer unit includes thirty-two
general purpose 64-bit registers, a load/store
architecture with single cycle ALU operations (add,
sub, logical, shift) and an autonomous multiply/divide
unit. Additional register resources include: the HI/LO
result registers for the two-operand integer multiply/
divide operations, and the program counter(PC).
Register File
The ACT5230 has thirty-two general purpose
registers with register location 0 hard wired to zero.
These registers are used for scalar integer
operations and address calculation. The register file
has two read ports and one write port and is fully
bypassed to minimize operation latency in the
pipeline.
ALU
The ACT5230 ALU consists of the integer adder/
subtractor, the logic unit, and the shifter. The adder
performs address calculations in addition to
arithmetic operations, the logic unit performs all
logical and zero shift data moves, and the shifter
performs shifts and store alignment operations. Each
of these units is optimized to perform all operations in
a single processor cycle
For Detail Information regarding the operation of
the Quantum Effect Design (QED) RISCMark
TM
RM5230
TM
, 32-Bit Superscalar Microprocessor see
the QED datasheet (Revision 1.2 July 1998).
Aeroflex Circuit Technology
SCD5230 REV 1 12/22/98 Plainview NY (516) 694-6700
3
Absolute Maximum Ratings
1
Symbol
Rating
Range
Units
T
TERM
Terminal Voltage with respect to GND
-0.5
2
to 4.6
V
T
CASE
Operating Temperature
0 to +85
C
T
BIAS
Case Temperature under Bias
-55 to +125
C
T
STG
Storage Temperature
-55 to +125
C
I
IN
DC Input Current
20
3
mA
I
OUT
DC Output Current
50
mA
Notes:
1. Stresses above those listed under "AbsoluteMaximums Rating" may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2. V
IN
minimum = -2.0V for pulse width less than 15nS. V
IN
maximum should not exceed +5.5 Volts.
3. When V
IN
< 0V or V
IN
> Vcc.
4. No more than one output should be shorted at one time. Duration of the short should not exceed more than 30 second.
Recommended Operating Conditions
Symbol
Parameter
Minimum
Maximum
Units
V
CC
Power Supply Voltage
+3.135
+3.465
V
V
IH
Input High Voltage
0.7V
CC
V
CC
+ 0.5
V
V
IL
Input Low Voltage
-0.5
0.2V
CC
V
T
C
Operating Temperature Case (Commercial)
0 +85
C
DC Characteristics
(V
CC
= 3.3V 5%; T
CASE
= 0C to +85C)
Parameter
Sym
Conditions
133 / 150MHz
Units
Min
Max
Output Low Voltage
V
OL1
I
OL
= 20 A
0.1
V
Output High Voltage
V
OH1
I
OL
= 20 A
Vcc - 0.1
V
Output Low Voltage
V
OL2
I
OL
= 4 mA
0.4
V
Output High Voltage
V
OH2
I
OL
= 4 mA
2.4
V
Input High Voltage
V
IH
0.7V
CC
V
CC
+ 0.5
V
Input Low Voltage
V
IL
-0.5
0.2V
CC
V
Input Current
I
IN1
V
IN
= 0V
-20
+20
A
Input Current
I
IN2
V
IN
= V
CC
-20
+20
A
Input Current
I
IN3
V
IN
= 5.5V
-250
+250
A
Input Capacitance
C
IN
10
pF
Output Capacitance
C
OUT
10
pF
Aeroflex Circuit Technology
SCD5230 REV 1 12/22/98 Plainview NY (516) 694-6700
4
AC Characteristics
(V
CC
= 3.3V 5%; T
CASE
= 0C to +85C)
Power Consumption
Parameter
Symbol
Conditions
133MHz, 3.3V
150MHz, 3.3V
Units
Typ
5
Max
Typ
5
Max
Active Operating
Supply Current
I
CC1
C
L
= 0pF, 150/75MHz, No SysAD
activity
TBD
TBD
TBD
TBD
mA
I
CC2
C
L
= 50pF, 150/75MHz, R4000 write
protocol without FPU operation
1000
1750
1150
1950
mA
I
CC3
C
L
= 50pF, 150/75MHz, write
re-issue or pipelined writes
1100
2000
1250
2250
mA
Standby Current
I
SB1
C
L
= 0pF, 150/75MHz
TBD
TBD
mA
I
SB1
C
L
= 50pF, 150/75MHz
TBD
TBD
mA
Notes:
5. Typical integer instruction mix and cache miss rates.
Capacitive Load Deration
Symbol
Parameter
133 / 150MHz
Units
Minimum
Maximum
C
LD
Load Derate
2
ns/25pF
Clock Parameters
Parameter
Symbol
Test Conditions
133/150MHz
Units
Min
Max
SysClock High
t
SCHigh
Transition < 5ns
4
ns
SysClock Low
t
SCLow
Transition < 5ns
4
ns
SysClock Frequency
6
33
75
MHz
SysClock Period
t
SCP
30
ns
Clock Jitter for SysClock
t
JitterIn
250
ps
SysClock Rise Time
t
SCRise
5
ns
SysClock Fall Time
t
SCFall
5
ns
ModeClock Period
t
ModeCKP
256*t
SCP
ns
JTA Clock Period
t
JTAGCKP
4*t
SCP
ns
Notes:
6. Operation of the ACT5230 is only guaranteed with the Phase Loop enabled.
Aeroflex Circuit Technology
SCD5230 REV 1 12/22/98 Plainview NY (516) 694-6700
5
System Interface Parameters
7
Parameter
Symbol
Test Conditions
133MHz
150MHz
Units
Min
Max
Min
Max
Data Output
8
t
DO
mode
14...13
= 10 (fastest)
TBD
TBD
TBD
TBD
ns
mode
14...13
= 11
TBD
TBD
TBD
TBD
ns
mode
14...13
= 00
1.0
8.0
1.0
8.0
ns
mode
14...13
= 01 (slowest)
TBD
TBD
TBD
TBD
ns
Data Setup
t
DS
t
RISE
= 5ns
4.0
4.0
ns
Data Hold
t
DH
t
FALL
= 5ns
0
0
ns
Notes:
7. Timmings are are measured from from 1.5V of the clock to 1.5V of the signal.
8. Capacitive load for all output timing is 50pF.
Boot Time Interface Parameters
Parameter
Symbol
Test Conditions
133/150MHz
Units
Min
Max
Mode Data Setup
t
DS
4
SysClock cycles
Mode Data Hold
t
DH
0
SysClock cycles
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