Features
eroflex Circuit Technology RISC TurboEngines For The Future SCD5231 REV 1 12/22/98
Block Diagram
s
Full militarized QED RM5231 microprocessor
s
Pinout compatible with popular RM5230 with split power sup
plies (2.5V and 3.3V)
s
Dual Issue superscalar microprocessor - can issue one
integer and one floating-point instruction per cycle
q
133, 150 and 200 MHz operating frequencies Consult Factory for
latest speeds
q
325 Dhrystone2.1 MIPS
q
SPECInt95 5.0, SPECfp95 5.25
s
System interface optimized for embedded applications
q
32-bit system interface lowers total system cost
q
High performance write protocols maximize uncached write
bandwidth with 600 MB per second peak throughput
q
Operates at processor clock divisors 2, 2.5, 3, 3.5,4, 4.5, 5, 6, 7, 8, 9
q
IEEE 1149.1 JTAG boundary scan
s
Integrated on-chip caches
q
32KB instruction and 32KB data - 2 way set associative and per
set locking
q
Virtually indexed, physically tagged
q
Write-back and write-through on per page basis
q
Pipeline restart on first double for data cache misses
s
Integrated memory management unit
q
Fully associative joint TLB (shared by I and D translations)
q
48 dual entries map 96 pages
q
Variable page size (4KB to 16MB in 4x increments)
s
High-performance floating point unit
q
532 MFLOPS single-precision performance
q
Single cycle repeat rate for common single precision opera-tions
and some double precision operations
q
Two cycle repeat rate for double precision multiply and double
precision combined multiply-add operations
q
Single cycle repeat rate for single precision combined multiply-
add operation
s
MIPS IV instruction set
q
Floating point multiply-add instruction increases performance in
signal processing and graphics applications
q
Conditional moves to reduce branch frequency
q
Index address modes (register + register)
s
Embedded application enhancements
q
Specialized DSP integer Multiply-Accumulate instruction and 3
operand multiply instruction
q
I and D cache locking by set
q
Optional dedicated exception vector for interrupts
s
Fully static CMOS design with power down logic
q
Standby reduced power mode with WAIT instruction
q
2.7 W typical power @ 200MHz
q
2.5V core with 3.3V IO's
s
128-pin Power Quad-4 package (F22),
Consult Factory for
package configuration
Preliminary
32-Bit Superscaler Microprocessor
ACT5231
Aeroflex Circuit Technology
SCD5231 REV 1 12/22/98 Plainview NY (516) 694-6700
2
DESCRIPTION
The ACT5231 is a highly integrated superscalar
microprocessor that implements a superset of the
MIPS IV Instruction Set Architecture(ISA). It has a
high performance 64-bit integer unit, a high
throughput, fully pipelined 64-bit floating point unit,
an operating system friendly memory management
unit with a 48-entry fully associative TLB, a 32KB
2-way set associative instruction cache, a 32KB
2-way set associative data cache, and an efficient
32-bit system interface. The ACT5231 can issue
both an integer and a floating point instruction in the
same cycle.
The ACT5231 is ideally suited for high-end
embedded control applications such as
internetworking, high performance image
manipulation, high speed printing, and 3-D
visualization.
HARDWARE OVERVIEW
The ACT5231 offers a high-level of integration
targeted at high-performance embedded
applications. The key elements of the ACT5231 are
briefly described below.
Superscalar Dispatch
The ACT5231 has an efficient asymmetric
superscalar dispatch unit which allows it to issue an
integer instruction and a floating-point computation
instruction simultaneously. With respect to
superscalar issue, integer instructions include alu,
branch, load/store, and floating-point load/ store,
while floating-point computation instructions
include floating-point add, subtract, combined
multiply-add, converts, etc. In combination with its
high throughput fully pipelined floating-point
execution unit, the superscalar capability of the
ACT5231 provides unparalleled price/performance
in computationally intensive embedded
applications.
CPU Registers
Like all MIPS ISA processors, the ACT5231 CPU
has a simple, clean user visible state consisting of
32 general purpose registers, two special purpose
registers for integer multiplication and division, a
program counter, and no condition code bits.
Pipeline
For integer operations, loads, stores, and other
non-floating-point operations, the ACT5231 uses
the simple 5-stage pipeline also found in the
ACT52xx family, R4600, R4700, and R5000. In
addition to this standard pipeline, the ACT5231
uses an extended seven stage pipeline for
floating-point operations. The ACT5231 does
virtual to physical translation in parallel with cache
access.
Integer Unit
The ACT5231 implements the MIPS IV
Instruction Set Architecture, and is therefore fully
upward compatible with applications that run on
processors implementing the earlier generation
MIPS I-III instruction sets. Additionally, the
ACT5231 includes two implementation specific
instructions not found in the baseline MIPS IV ISA
but that are useful in the embedded market place.
Described in detail in the QED RM5231 datasheet,
these instructions are integer multiply-accumulate
and 3-operand integer multiply.
The ACT5231 integer unit includes thirty-two
general purpose 64-bit registers, a load/store
architecture with single cycle ALU operations (add,
sub, logical, shift) and an autonomous multiply/
divide unit. Additional register resources include:
the HI/LO result registers for the two-operand
integer multiply/divide operations, and the program
counter(PC).
Register File
The ACT5231 has thirty-two general purpose
registers with register location 0 hard wired to zero.
These registersich allo are used for scalar integer
operations and address calculation. The register
file has two read ports and one write port and is fully
bypassed to minimize operation latency in the
pipeline.
ALU
The ACT5231 ALU consists of the integer adder/
subtractor, the logic unit, and the shifter. The adder
performs address calculations in addition to
arithmetic operations, the logic unit performs all
logical and zero shift data moves, and the shifter
performs shifts and store alignment operations.
Each of these units is optimized to perform all tions
in a single processor cycle.
For additional Detail Information regarding the
operation of the Quantum Effect Design (QED)
RISCMark
TM
RM 5231
TM
, 32-Bit Superscalar
Microprocessor see the latest QED datasheet.
Aeroflex Circuit Technology
SCD5231 REV 1 12/22/98 Plainview NY (516) 694-6700
3
ACT5231 Microprocessor PQUAD Pinouts
(Pinouts subject to change Contact Factory)
Pin #
Function
Pin #
Function
Pin #
Function
Pin #
Function
1
Vcc
53
NC
105
Vcc
157
NC
2
NC
54
NC
106
NMI*
158
NC
3
NC
55
NC
107
ExtRqst*
159
NC
4
Vcc
56
Vcc
108
Reset*
160
NC
5
Vss
57
Vss
109
ColdReset*
161
Vcc
6
SysAD4
58
ModeIn
110
VccOK
162
Vss
7
SysAD36
59
RdRdy*
111
BigEndian
163
SysAD28
8
SysAD5
60
WrRdy*
112
Vcc
164
SysAD60
9
SysAD37
61
ValidIn*
113
Vss
165
SysAD29
10
Vcc
62
ValidOut*
114
SysAD16
166
SysAD61
11
Vss
63
Release*
115
SysAD48
167
Vcc
12
SysAD6
64
VccP
116
Vcc
168
Vss
13
SysAD38
65
VssP
117
Vss
169
SysAD30
14
Vcc
66
SysClock
118
SysAD17
170
SysAD62
15
Vss
67
Vcc
119
SysAD49
171
Vcc
16
SysAD7
68
Vss
120
SysAD18
172
Vss
17
SysAD39
69
Vcc
121
SysAD50
173
SysAD31
18
SysAD8
70
Vss
122
Vcc
174
SysAD63
19
SysAD40
71
Vcc
123
Vss
175
SysADC2
20
Vcc
72
Vss
124
SysAD19
176
SysADC6
21
Vss
73
SysCmd0
125
SysAD51
177
Vcc
22
SysAD9
74
SysCmd1
126
Vcc
178
Vss
23
SysAD41
75
SysCmd2
127
Vss
179
SysADC3
24
Vcc
76
SysCmd3
128
SysAD20
180
SysADC7
25
Vss
77
Vcc
129
SysAD52
181
Vcc
26
SysAD10
78
Vss
130
SysAD21
182
Vss
27
SysAD42
79
SysCmd4
131
SysAD53
183
SysADC0
28
SysAD11
80
SysCmd5
132
Vcc
184
SysADC4
29
SysAD43
81
Vcc
133
Vss
185
Vcc
30
Vcc
82
Vss
134
SysAD22
186
Vss
31
Vss
83
SysCmd6
135
SysAD54
187
SysADC1
32
SysAD12
84
SysCmd7
136
Vcc
188
SysADC5
33
SysAD44
85
SysCmd8
137
Vss
189
SysAD0
34
Vcc
86
SysCmdP
138
SysAD23
190
SysAD32
35
Vss
87
Vcc
139
SysAD55
191
Vcc
36
SysAD13
88
Vss
140
SysAD24
192
Vss
37
SysAD45
89
Vcc
141
SysAD56
193
SysAD1
38
SysAD14
90
Vss
142
Vcc
194
SysAD33
39
SysAD46
91
Vcc
143
Vss
195
Vcc
40
Vcc
92
Vss
144
SysAD25
196
Vss
41
Vss
93
Int0*
145
SysAD57
197
SysAD2
42
SysAD15
94
Int1*
146
Vcc
198
SysAD34
43
SysAD47
95
Int2*
147
Vss
199
SysAD3
44
Vcc
96
Int3*
148
SysAD26
200
SysAD35
45
Vss
97
Int4*
149
SysAD58
201
Vcc
46
ModeClock
98
Int5*
150
SysAD27
202
Vss
47
JTDO
99
Vcc
151
SysAD59
203
NC
48
JTDI
100
Vss
152
Vcc
204
NC
49
JTCK
101
NC
153
Vss
205
NC
50
JTMS
102
NC
154
NC
206
NC
51
Vcc
103
NC
155
NC
207
Vcc
52
Vss
104
NC
156
Vss
208
Vss
These V
CC
pins may be 2.5V in future higher performance devices
(P
ack
ag
e &
P
in
ou
ts
su
bje
ct
to
ch
an
ge
Co
nta
ct
Fa
cto
ry
)
Aeroflex Circuit Technology
SCD5231 REV 1 12/22/98 Plainview NY (516) 694-6700
4
Sample Ordering Information
Part Number
Screening
Speed (MHz)
Package
ACT-5231PC-133F22C
Commercial Temperature
133
128 Lead PQUAD
ACT-5231PC-150F22T
Military Temperature
150
128 Lead PQUAD
ACT-5231PC-200F22M
Military Screening
200
128 Lead PQUAD
Aeroflex Circuit Technology
35 South Service Road
Plainview New York 11803
Telephone: (516) 694-6700
FAX: (516) 694-6715
Toll Free Inquiries: (800) 843-1553
www.aeroflex.com/act1.htm
E-Mail: sales-act@aeroflex.com
Specifications subject to change without notice.
C I R C U I T T E C H N O L O G Y
Part Number Breakdown
ACT 5231 PC 200 F22 M
Aeroflex Circuit
Technology
Base Processor Type
133 = 150MHz
150 = 150MHz
200 = 200MHz
Cache Style
Package Type & Size
C = Commercial Temp, 0C to +70C
I = Industrial Temp, -40C to +85C
T = Military Temp, -55C to +125C
M = Military Temp, -55C to +125C, Screened
*
Q = MIL-PRF-38534 Compliant/SMD if applicable
Screening
*
Screened to the individual test methods of MIL-STD-883
PC = Primary Cache
Maximum Pipeline Freq.
Surface Mount Package
F22 = 1.10" SQ 128 Lead PQUAD
PDF 
ZIP